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31. 发明授权

US07821007B2 Thin film transistor and flat panel display device 有权
标题翻译：薄膜晶体管和平板显示装置
公开(公告)号：US07821007B2
公开(公告)日：2010-10-26
申请号：US11971191
申请日：2008-01-08
申请人： Jong-Hyun Choi
发明人： Jong-Hyun Choi
IPC分类号： H01L29/76 , H01L31/036 , H01L31/112
CPC分类号： H01L29/78675 , H01L27/1214 , H01L29/66757 , H01L29/78621 , H01L2029/7863
摘要： A thin film transistor, a method of fabricating the same, and a flat panel display device including the same, are provided. According to the method, low resistance regions and high resistance regions can be manufactured through one doping process. The thin film transistor includes: a substrate; a semiconductor layer disposed on the substrate and including source and drain regions, high resistance regions smaller than the source and drain regions, a channel region, and connection regions disposed between the high resistance regions and the channel region; a gate insulating layer disposed on the semiconductor layer; a gate electrode disposed on the gate insulating layer above the channel region; an interlayer insulating layer disposed on the gate electrode; and source and drain electrodes disposed on the interlayer insulating layer and electrically connected to the source and drain regions, respectively.
摘要翻译：提供薄膜晶体管，其制造方法和包括该薄膜晶体管的平板显示装置。根据该方法，可以通过一个掺杂工艺制造低电阻区域和高电阻区域。薄膜晶体管包括：基板; 设置在所述基板上并且包括源极和漏极区域的半导体层，小于所述源极和漏极区域的高电阻区域，沟道区域和设置在所述高电阻区域和所述沟道区域之间的连接区域; 设置在所述半导体层上的栅极绝缘层; 设置在所述沟道区域上方的所述栅极绝缘层上的栅电极; 设置在所述栅电极上的层间绝缘层; 以及设置在层间绝缘层上并分别与源极和漏极区电连接的源极和漏极。

32. 发明申请

US20090302332A1 SEMICONDUCTOR CIRCUIT HAVING CAPACITOR AND THIN FILM TRANSISTOR, FLAT PANEL DISPLAY INCLUDING THE SEMICONDUCTOR CIRCUIT, AND METHOD OF MANUFACTURING THE SEMICONDUCTOR CIRCUIT 有权
标题翻译：具有电容器和薄膜晶体管的半导体电路，包括半导体电路的平面板显示器和制造半导体电路的方法
公开(公告)号：US20090302332A1
公开(公告)日：2009-12-10
申请号：US12475136
申请日：2009-05-29
申请人： Chul-Kyu Kang , Do-Hyun Kwon , Ju-Won Yoon , Jong-Hyun Choi , Jun-woo Lee
发明人： Chul-Kyu Kang , Do-Hyun Kwon , Ju-Won Yoon , Jong-Hyun Choi , Jun-woo Lee
IPC分类号： H01L33/00 , H01L27/06 , H01L21/336
CPC分类号： H01L27/1288 , H01L27/1255 , H01L29/4908
摘要： A flat panel display including a semiconductor circuit, and a method of manufacturing the semiconductor circuit are disclosed. In one embodiment, the semiconductor circuit includes i) a substrate, ii) a semiconductor layer and a first capacitor electrode formed on the substrate, the first capacitor electrode being doped to be conductive, iii) an insulating layer covering the semiconductor layer and the first capacitor electrode, iv) a gate electrode disposed on the insulating layer and corresponding to a portion of the semiconductor layer, and v) a second capacitor electrode disposed on the insulating layer and corresponding to the first capacitor electrode, wherein the gate electrode is thicker than the second capacitor electrode.
摘要翻译：公开了一种包括半导体电路的平板显示器和制造该半导体电路的方法。在一个实施例中，半导体电路包括i）衬底，ii）形成在衬底上的半导体层和第一电容器电极，第一电容器电极被掺杂为导电，iii）覆盖半导体层和第一电容器电极，iv）设置在所述绝缘层上并对应于所述半导体层的一部分的栅电极，以及v）设置在所述绝缘层上并对应于所述第一电容器电极的第二电容器电极，其中所述栅电极比第二电容器电极。

33. 发明授权

US07558128B2 Semiconductor memory device having a voltage boosting circuit 有权
标题翻译：具有升压电路的半导体存储器件
公开(公告)号：US07558128B2
公开(公告)日：2009-07-07
申请号：US11473402
申请日：2006-06-24
申请人： Chang-Ho Shin , Jong-Hyun Choi
发明人： Chang-Ho Shin , Jong-Hyun Choi
IPC分类号： G11C5/14
CPC分类号： G11C5/145 , G11C5/147
摘要： A semiconductor memory device includes a cell array internal voltage generating circuit for generating cell array reference voltage and a cell array internal voltage from a first external power voltage, a peripheral circuit internal voltage generating circuit for generating a peripheral circuit reference voltage and a peripheral circuit internal voltage from the first external power voltage, and a voltage boosting circuit power voltage generating circuit for generating a voltage boosting circuit reference voltage and a voltage boosting circuit power voltage from a second external power voltage.
摘要翻译：一种半导体存储器件，包括用于产生单元阵列参考电压的单元阵列内部电压产生电路和来自第一外部电源电压的单元阵列内部电压，用于产生外围电路参考电压的外围电路内部电压产生电路和外部电路内部电路的外围电路来自第一外部电源电压的电压，以及用于从第二外部电源电压产生升压电路参考电压和升压电路电源电压的升压电路电源电压产生电路。

34. 发明授权

US07528644B2 Temperature detecting circuit 有权
标题翻译：温度检测电路
公开(公告)号：US07528644B2
公开(公告)日：2009-05-05
申请号：US11482448
申请日：2006-07-07
申请人： Jong-Hyun Choi , Dong-Il Seo
发明人： Jong-Hyun Choi , Dong-Il Seo
IPC分类号： H01L35/00
CPC分类号： G01K7/015 , G01K2219/00
摘要： A temperature detecting circuit is provided. The temperature detecting circuit includes a reference and detection voltage generator for generating a reference voltage corresponding to a first and a second reference current, and changing first to M-th (M being a natural number) detection currents based on first to M-th temperature detection codes to generate first to M-th detection voltages corresponding to the changed first to M-th detection currents and the second reference current; a temperature detection signal generator for comparing each of the first to M-th detection voltages with the reference voltage to generate first to M-th temperature detection signals; and a temperature detection controller for detecting an operation temperature of a semiconductor device while changing the first to M-th temperature detection codes in response to the first to M-th temperature detection signals from the temperature detection signal generator.
摘要翻译：提供温度检测电路。温度检测电路包括用于产生对应于第一和第二参考电流的参考电压的参考和检测电压发生器，并且基于第一至第M温度首先改变为第M（M为自然数）检测电流检测码，用于产生对应于改变的第一至第M检测电流和第二参考电流的第一至第M检测电压; 温度检测信号发生器，用于将第一至第M检测电压中的每一个与参考电压进行比较，以产生第一至第M温度检测信号; 以及温度检测控制器，用于响应于来自温度检测信号发生器的第一至第M温度检测信号，在改变第一至第M温度检测代码的同时检测半导体器件的工作温度。

35. 发明申请

US20090046531A1 CIRCUIT AND METHOD FOR CONTROLLING REFRESH PERIODS IN SEMICONDUCTOR MEMORY DEVICES 有权
标题翻译：用于控制半导体存储器件中的刷新周期的电路和方法
公开(公告)号：US20090046531A1
公开(公告)日：2009-02-19
申请号：US12111468
申请日：2008-04-29
申请人： Kwang-Sook Noh , Young-Hun Seo , Jong-Hyun Choi
发明人： Kwang-Sook Noh , Young-Hun Seo , Jong-Hyun Choi
IPC分类号： G11C7/04
CPC分类号： G11C11/402 , G11C11/406 , G11C11/40611 , G11C11/40626 , G11C2211/4061
摘要： An integrated circuit memory device includes a refresh control circuit that generates an internal memory refresh command signal having a period that is changed relative to a period of an external memory refresh command signal received by the memory device. This change in the period of the internal memory refresh command may be in response to detecting a change in temperature of the memory device. In particular, the refresh control circuit is configured so that the period of the internal memory refresh command signal is increased in response to detecting a reduction in temperature of the memory device.
摘要翻译：集成电路存储器件包括刷新控制电路，该刷新控制电路产生具有相对于由存储器件接收的外部存储刷新命令信号的周期而改变的周期的内部存储器刷新命令信号。内部存储器刷新命令的周期中的这种变化可以响应于检测到存储器件的温度变化。特别地，刷新控制电路被配置为使得响应于检测到存储器件的温度降低而使内部存储器刷新命令信号的周期增加。

36. 发明授权

US07486576B2 Methods and devices for preventing data stored in memory from being read out 有权
标题翻译：用于防止存储在存储器中的数据被读出的方法和装置
公开(公告)号：US07486576B2
公开(公告)日：2009-02-03
申请号：US11826367
申请日：2007-07-13
申请人： Jong-Hyun Choi , Dong-Il Seo , Kyu-Chan Lee , Young-Hun Seo
发明人： Jong-Hyun Choi , Dong-Il Seo , Kyu-Chan Lee , Young-Hun Seo
IPC分类号： G11C7/00
CPC分类号： G11C11/4078 , G11C7/24
摘要： A dynamic random access memory (DRAM) device, including a DRAM core having memory cells for storing data information, and a read protection unit, prevents data stored in the memory cells before power-off, from being read out at power-on.
摘要翻译：包括具有用于存储数据信息的存储单元的DRAM内核的动态随机存取存储器（DRAM）装置以及在上电期间防止存储在存储单元中的数据在读取电源时被读出的读保护单元。

37. 发明申请

US20080111135A1 ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：有机发光二极管显示装置及其制造方法
公开(公告)号：US20080111135A1
公开(公告)日：2008-05-15
申请号：US11935670
申请日：2007-11-06
申请人： Jong-Hyun Choi , Kyung-Jin Yoo
发明人： Jong-Hyun Choi , Kyung-Jin Yoo
IPC分类号： H01L27/12 , H01L21/84
CPC分类号： H01L27/1277 , H01L27/1255 , H01L27/1296 , H01L27/3244 , H01L27/3265 , H01L27/3276 , H01L51/0021
摘要： An organic light emitting diode display device (OLED display device) having uniform electrical characteristics and a method of manufacturing the same. The OLED display device includes: a substrate; a semiconductor layer disposed on the substrate, and including source and drain regions and a channel region formed using metal induced lateral crystallization (MILC); a gate insulating layer for electrically insulating the semiconductor layer; a gate electrode disposed on the gate insulating layer; an interlayer insulating layer for electrically insulating the gate electrode; a thin film transistor (TFT) including source and drain electrodes that are electrically connected to the source and drain regions of the semiconductor layer; a first electrode for a capacitor disposed on a region of the substrate to be spaced apart from the TFT and formed using a metal induced crystallization (MIC); the gate insulating layer for electrically insulating the first capacitor electrode; a second electrode for the capacitor disposed on the gate insulating layer; a planarization layer disposed on the TFT and the capacitor; a first electrode disposed on the planarization layer; a pixel defining layer disposed on the first electrode; an organic layer disposed on the first electrode and the pixel defining layer, and including at least an emission layer; and a second electrode disposed on the organic layer.
摘要翻译：一种具有均匀电特性的有机发光二极管显示装置（OLED显示装置）及其制造方法。 OLED显示装置包括：基板; 设置在所述衬底上的半导体层，并且包括源区和漏区以及使用金属诱导横向结晶（MILC）形成的沟道区; 用于使所述半导体层电绝缘的栅极绝缘层; 设置在所述栅极绝缘层上的栅电极; 用于使所述栅电极电绝缘的层间绝缘层; 包括电连接到半导体层的源极和漏极区域的源极和漏极的薄膜晶体管（TFT）; 用于电容器的第一电极，设置在与TFT间隔开并且使用金属诱导结晶（MIC）形成的基板的区域上; 所述栅极绝缘层用于使所述第一电容器电极电绝缘; 用于设置在栅极绝缘层上的电容器的第二电极; 设置在TFT和电容器上的平坦化层; 设置在所述平坦化层上的第一电极; 设置在所述第一电极上的像素限定层; 设置在所述第一电极和所述像素限定层上的有机层，并且至少包括发光层; 以及设置在有机层上的第二电极。

38. 发明授权

US07298655B2 Isolation control circuit and method for a memory device 有权
标题翻译：用于存储器件的隔离控制电路和方法
公开(公告)号：US07298655B2
公开(公告)日：2007-11-20
申请号：US11073765
申请日：2005-03-08
申请人： Jong-Hyun Choi , Young-Sun Min
发明人： Jong-Hyun Choi , Young-Sun Min
IPC分类号： G11C16/04
CPC分类号： G11C11/4091 , G11C11/4094 , G11C2207/005
摘要： A semiconductor memory includes a memory cell array, a sense amplifier, an isolation device interposed between the sense amplifier and a bit line of the memory cell array, and circuitry for transferring a charge contained in a memory cell of memory cell array to the bit line while the isolation device electrically isolates the bit line from the sense amplifier, and, after the charge is transferred to the bit line, for causing the isolation device to electrically connect the bit line to the sense amplifier.
摘要翻译：半导体存储器包括存储单元阵列，读出放大器，插入在读出放大器和存储单元阵列的位线之间的隔离装置，以及用于将包含在存储单元阵列的存储单元中的电荷传送到位线而隔离装置将位线与读出放大器电隔离，并且在电荷被传送到位线之后，用于使隔离装置将位线电连接到读出放大器。

39. 发明授权

US07259978B2 Semiconductor memory devices and signal line arrangements and related methods 失效
标题翻译：半导体存储器件和信号线布置及相关方法
公开(公告)号：US07259978B2
公开(公告)日：2007-08-21
申请号：US11221684
申请日：2005-09-08
申请人： Chul-Woo Park , Jung-Bae Lee , Young-Sun Min , Jong-Hyun Choi , Jong-Eon Lee
发明人： Chul-Woo Park , Jung-Bae Lee , Young-Sun Min , Jong-Hyun Choi , Jong-Eon Lee
IPC分类号： G11C5/06
CPC分类号： G11C5/063 , G11C7/18 , G11C8/14
摘要： A semiconductor memory device may include a memory cell array, a bit line sense amplifier, a sub word line driver, and an electrode. The memory cell array may include a sub memory cell array connected between sub word lines and bit line pairs and having memory cells which are selected in response to a signal transmitted to the sub word lines and column selecting signal lines. The bit line sense amplifier may be configures to sense and amplify data of the bit line pairs. The sub word line driver may be configured to combine signals transmitted from word selecting signal lines and signals transmitted from main word lines to select the sub word lines. Moreover, the memory cell array may be configured to transmit data between the bit line pairs and local data line pairs and to transmit data between the local data line pairs and global data line pairs. The electrode may be configured to cover the whole memory cell array and to apply a voltage needed for the memory cells. The local data line pairs may be arranged on a first layer above the electrode in the same direction as the sub word line. The column selecting signal lines and the global data line pairs may be arranged on a second layer above the electrode in the same direction as the bit line. The word selecting signal lines and the main word lines may be arranged on a third layer above the electrode in the same direction as the sub word line. Related methods of signal line arrangement are also discussed.
摘要翻译：半导体存储器件可以包括存储单元阵列，位线读出放大器，子字线驱动器和电极。存储单元阵列可以包括连接在子字线和位线对之间并具有响应于发送到子字线和列选择信号线的信号而被选择的存储器单元的子存储单元阵列。位线读出放大器可以被配置为感测和放大位线对的数据。子字线驱动器可以被配置为组合从字选择信号线发送的信号和从主字线发送的信号，以选择子字线。此外，存储单元阵列可以被配置为在位线对和本地数据线对之间传输数据，并且在本地数据线对和全局数据线对之间传送数据。电极可以被配置为覆盖整个存储单元阵列并施加存储单元所需的电压。局部数据线对可以以与子字线相同的方向布置在电极上方的第一层上。列选择信号线和全局数据线对可以以与位线相同的方向布置在电极上方的第二层上。字选择信号线和主字线可以沿与子字线相同的方向布置在电极上方的第三层上。还讨论了信号线布置的相关方法。

40. 发明授权

US07242602B2 Semiconductor memory devices having conductive line in twisted areas of twisted bit line pairs 失效
标题翻译：半导体存储器件在绞合位线对的扭转区域具有导线
公开(公告)号：US07242602B2
公开(公告)日：2007-07-10
申请号：US11002034
申请日：2004-12-02
申请人： Chang-Ho Lee , Jong-Hyun Choi
发明人： Chang-Ho Lee , Jong-Hyun Choi
IPC分类号： G11C5/08 , G11C5/06 , G11C11/12
CPC分类号： G11C11/4097 , G11C5/14 , G11C7/02 , Y10S257/907
摘要： A semiconductor memory device includes spaced apart twisted bit line pairs, a respective one of which includes a spaced apart twisted area. A conductive line overlaps the respective twisted areas of the spaced apart twisted line pairs. The conductive line can extend parallel to the memory device word lines, and can provide a power supply ground and/or signal line.
摘要翻译：半导体存储器件包括间隔开的扭曲位线对，其相应的一个包括间隔开的扭曲区域。导线与间隔开的扭绞线对的相应扭曲区域重叠。导线可以平行于存储器件字线延伸，并且可以提供电源接地和/或信号线。

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