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31. 发明授权

US5804508A Method of making a low dielectric constant material for electronics 失效
标题翻译：制造电子材料用低介电常数材料的方法
公开(公告)号：US5804508A
公开(公告)日：1998-09-08
申请号：US735758
申请日：1996-10-23
申请人： Bruce E. Gnade , Chih-Chen Cho , Douglas M. Smith
发明人： Bruce E. Gnade , Chih-Chen Cho , Douglas M. Smith
IPC分类号： C04B38/00 , H01L21/312 , H01L21/314 , H01L21/316 , H01L21/768 , H01L23/522 , H01L21/31
CPC分类号： H01L21/02126 , H01L21/02203 , H01L21/02216 , H01L21/02282 , H01L21/02337 , H01L21/02343 , H01L21/02359 , H01L21/02362 , H01L21/3121 , H01L21/3122 , H01L21/31695 , H01L21/76801 , H01L21/7682 , H01L21/76834 , H01L2221/1047
摘要： This invention provides a process for making a semiconductor device with reduced capacitance between adjacent conductors. This process can include applying a solution between conductors 24, and then gelling, surface modifying, and drying the solution to form an extremely porous dielectric layer 28. A non-porous dielectric layer 30 may be formed over porous layer 28, which may complete an interlayer dielectric. A novel process for creating the porous dielectric layer is disclosed, which can be completed at vacuum or ambient pressures, yet results in porosity, pore size, and shrinkage of the dielectric during drying comparable to that previously attainable only by drying gels at supercritical pressure.
摘要翻译：本发明提供一种在相邻导体之间制造具有降低的电容的半导体器件的方法。该方法可以包括在导体24之间施加溶液，然后将溶液凝胶化，表面改性和干燥以形成极其多孔的介电层28.多孔介质层30可形成在多孔层28之上，多孔层28可以完成层间电介质。公开了一种用于产生多孔介电层的新方法，其可以在真空或环境压力下完成，但是在干燥期间导致电介质的孔隙率，孔径和收缩相当于仅通过在超临界压力下干燥凝胶可获得的电介质层。

32. 发明授权

US5782997A Aluminum metallization for SiGe devices 失效
标题翻译： SiGe器件的铝金属化
公开(公告)号：US5782997A
公开(公告)日：1998-07-21
申请号：US474290
申请日：1995-06-07
申请人： Chih-Chen Cho , Hung-Yu Liu
发明人： Chih-Chen Cho , Hung-Yu Liu
IPC分类号： C30B23/02 , H01L21/285 , C30B23/06
CPC分类号： H01L21/2855 , C30B23/02 , C30B29/02
摘要： Single crystal aluminum is deposited on SiGe structures to form metal interconnects. Generally, a method of forming single crystal aluminum on Si.sub.(1-X) Ge.sub.X is presented, including the steps of maintaining the substrate at certain temperature (e.g. between 300.degree. C. and 400.degree. C.) and pressure conditions (e.g. below 2.times.10.sup.-9 millibar) while aluminum atoms are deposited by a vacuum evaporation technique. This is apparently the first method of depositing single crystal aluminum on SiGe surfaces. Novel structures are made possible by the invention, including epitaxial layers 34 formed on single crystal aluminum 32 which has been deposited on SiGe 30. Among the advantages made possible by the methods presented are thermal stability and resistance to electromigration.
摘要翻译：单晶铝沉积在SiGe结构上以形成金属互连。通常，提出了在Si（1-X）GeX上形成单晶铝的方法，包括将衬底保持在一定温度（例如300℃至400℃）和压力条件（例如低于2×10 -9毫巴），而铝原子通过真空蒸发技术沉积。这显然是在SiGe表面上沉积单晶铝的第一种方法。通过本发明使得新颖的结构成为可能，包括形成在已经沉积在SiGe 30上的单晶铝32上的外延层34.通过所提出的方法可能的优点是热稳定性和抗电迁移。

33. 发明授权

US5536965A Porous thermal isolation mesas for hybrid uncooled infrared detectors 失效
标题翻译：用于混合非制冷红外探测器的多孔热隔离台面
公开(公告)号：US5536965A
公开(公告)日：1996-07-16
申请号：US479378
申请日：1995-06-07
申请人： Howard R. Beratan , Chih-Chen Cho , Scott R. Summerfelt
发明人： Howard R. Beratan , Chih-Chen Cho , Scott R. Summerfelt
IPC分类号： H01L27/146 , H01L37/02 , H01L31/00 , H01L31/058
CPC分类号： H01L27/1465 , H01L37/02 , Y10T29/49169
摘要： Thermal isolation mesas 36 comprising a porous material 64 are used to thermally insulate sensing integrated circuitry 44 from pixels 34 of an uncooled IR detector hybrid system 30. The porous material 64 is preferably a silicon-dioxide xerogel. The mesas 36 may also comprise a protective film 66.
摘要翻译：包括多孔材料64的隔热台面36用于将感测集成电路44与未经IR的IR检测器混合系统30的像素34热绝缘。多孔材料64优选为二氧化硅干凝胶。台面36还可以包括保护膜66。

34. 发明授权

US5494858A Method for forming porous composites as a low dielectric constant layer with varying porosity distribution electronics applications 失效
标题翻译：用于形成多孔复合材料作为具有不同孔隙分布电子应用的低介电常数层的方法
公开(公告)号：US5494858A
公开(公告)日：1996-02-27
申请号：US255157
申请日：1994-06-07
申请人： Bruce E. Gnade , Chih-Chen Cho , Douglas M. Smith
发明人： Bruce E. Gnade , Chih-Chen Cho , Douglas M. Smith
IPC分类号： C04B38/00 , H01L21/312 , H01L21/314 , H01L21/316 , H01L21/768 , H01L23/522 , H01L23/532 , H01L21/469
CPC分类号： H01L21/7682 , H01L21/02126 , H01L21/02203 , H01L21/02216 , H01L21/02282 , H01L21/02337 , H01L21/02343 , H01L21/02359 , H01L21/02362 , H01L21/31695 , H01L21/76835 , H01L23/5222 , H01L23/5329 , H01L21/3121 , H01L2221/1047 , H01L2924/0002
摘要： This invention provides a process for making a semiconductor device with reduced capacitance between adjacent conductors. This process can include applying and gelling one or more solutions between and over conductors 24 and drying the wet gel to create at least porous dielectric sublayers 28 and 29. By varying the composition of the solutions, gelling conditions, drying temperature, composition of the solvents in the wet gel, or a combination of these approaches, the porosity of the sublayers may be tailored individually. A non-porous dielectric layer 30 may be formed over porous layer 28, which may complete an interlayer dielectric. A novel process for creating the porous dielectric layer is disclosed, which can be completed at vacuum or ambient pressures, yet results in porosity, pore size, and shrinkage of the dielectric during drying comparable to that previously attainable only by drying gels at supercritical pressure.
摘要翻译：本发明提供一种在相邻导体之间制造具有降低的电容的半导体器件的方法。该方法可以包括在导体24之间和之上施加和凝胶化一种或多种溶液并干燥湿凝胶以产生至少多孔介电子层28和29.通过改变溶液的组成，胶凝条件，干燥温度，溶剂的组成在湿凝胶中，或这些方法的组合，子层的孔隙率可以单独定制。无孔介电层30可以形成在多孔层28之上，多孔层28可以完成层间电介质。公开了一种用于产生多孔介电层的新方法，其可以在真空或环境压力下完成，但是在干燥期间导致电介质的孔隙率，孔径和收缩相当于仅通过在超临界压力下干燥凝胶可获得的电介质层。

35. 发明授权

US5488015A Method of making an interconnect structure with an integrated low density dielectric 失效
标题翻译：制造具有集成低密度电介质的互连结构的方法
公开(公告)号：US5488015A
公开(公告)日：1996-01-30
申请号：US246432
申请日：1994-05-20
申请人： Robert H. Havemann , Shin-Puu Jeng , Bruce E. Gnade , Chih-Chen Cho
发明人： Robert H. Havemann , Shin-Puu Jeng , Bruce E. Gnade , Chih-Chen Cho
IPC分类号： H01L21/314 , H01L21/316 , H01L21/768 , H01L23/522 , H01L23/528 , H01L23/532 , H01L21/441 , H01L21/469
CPC分类号： H01L21/02362 , H01L21/02123 , H01L21/02126 , H01L21/02203 , H01L21/02216 , H01L21/02282 , H01L21/02359 , H01L21/31695 , H01L21/7682 , H01L21/76829 , H01L21/76834 , H01L23/5222 , H01L23/5226 , H01L23/5283 , H01L23/5329 , H01L2221/1047 , H01L2924/0002 , Y10S148/043 , Y10S148/118
摘要： This invention provides a semiconductor device and process for making the same with dramatically reduced capacitance between adjacent conductors and an interlayer dielectric construction which emphasizes mechanical strength, etch compatibility, and good heat transfer. This process can include applying a solution between conductors 24, and then gelling, surface modifying, and drying the solution to form an extremely porous dielectric layer 28. A non-porous dielectric layer 30 may be formed over porous layer 28, which may complete an interlayer dielectric and provide mechanical strength, heat transfer, and a solid layer for via etch. A novel process for creating the porous dielectric layer is disclosed, which can be completed at vacuum or ambient pressures, yet results in porosity, pore size, and shrinkage of the dielectric during drying comparable to that previously attainable only by drying gels at supercritical pressure.
摘要翻译：本发明提供了一种半导体器件及其制造方法，其显着降低了相邻导体之间的电容，以及强调机械强度，蚀刻兼容性和良好热传递的层间电介质结构。该方法可以包括在导体24之间施加溶液，然后将溶液凝胶化，表面改性和干燥以形成极其多孔的介电层28.多孔介质层30可形成在多孔层28之上，多孔层28可以完成层间电介质，并提供机械强度，热传递和用于通孔蚀刻的固体层。公开了一种用于产生多孔介电层的新方法，其可以在真空或环境压力下完成，但是在干燥期间导致电介质的孔隙率，孔径和收缩相当于仅通过在超临界压力下干燥凝胶可获得的电介质层。

36. 发明授权

US5470802A Method of making a semiconductor device using a low dielectric constant material 失效
标题翻译：使用低介电常数材料制造半导体器件的方法
公开(公告)号：US5470802A
公开(公告)日：1995-11-28
申请号：US247195
申请日：1994-05-20
申请人： Bruce E. Gnade , Chih-Chen Cho , Douglas M. Smith
发明人： Bruce E. Gnade , Chih-Chen Cho , Douglas M. Smith
IPC分类号： C04B38/00 , H01L21/312 , H01L21/314 , H01L21/316 , H01L21/768 , H01L23/522 , H01L21/02
CPC分类号： H01L21/02126 , H01L21/02203 , H01L21/02216 , H01L21/02282 , H01L21/02337 , H01L21/02343 , H01L21/02359 , H01L21/02362 , H01L21/3121 , H01L21/3122 , H01L21/31695 , H01L21/76801 , H01L21/7682 , H01L21/76834 , H01L2221/1047
摘要： This invention provides a process for making a semiconductor device with reduced capacitance between adjacent conductors. This process can include applying a solution between conductors 24, and then gelling, surface modifying, and drying the solution to form an extremely porous dielectric layer 28. A non-porous dielectric layer 30 may be formed over porous layer 28, which may complete an interlayer dielectric. A novel process for creating the porous dielectric layer is disclosed, which can be completed at vacuum or ambient pressures, yet results in porosity, pore size, and shrinkage of the dielectric during drying comparable to that previously attainable only by drying gels at supercritical pressure.
摘要翻译：本发明提供一种在相邻导体之间制造具有降低的电容的半导体器件的方法。该方法可以包括在导体24之间施加溶液，然后将溶液凝胶化，表面改性和干燥以形成极其多孔的介电层28.多孔介质层30可形成在多孔层28之上，多孔层28可以完成层间电介质。公开了一种用于产生多孔介电层的新方法，其可以在真空或环境压力下完成，但是在干燥期间导致电介质的孔隙率，孔径和收缩相当于仅通过在超临界压力下干燥凝胶可获得的电介质层。

37. 发明授权

US07354812B2 Multiple-depth STI trenches in integrated circuit fabrication 有权
标题翻译：集成电路制造中的多深STI沟槽
公开(公告)号：US07354812B2
公开(公告)日：2008-04-08
申请号：US10931946
申请日：2004-09-01
申请人： Shubneesh Batra , Howard C. Kirsch , Gurtej S. Sandhu , Xianfeng Zhou , Chih-Chen Cho
发明人： Shubneesh Batra , Howard C. Kirsch , Gurtej S. Sandhu , Xianfeng Zhou , Chih-Chen Cho
IPC分类号： H01L21/337 , H01L21/8238 , H01L21/8249 , H01L21/336 , H01L21/331 , H01L21/76 , H01L33/00 , H01L29/76 , H01L31/00 , H01L29/00
CPC分类号： H01L21/76229
摘要： Multiple trench depths within an integrated circuit device are formed by first forming trenches in a substrate to a first depth, but of varying widths. Formation of a dielectric layer can cause some of the trenches to fill or close off while leaving other, wider trenches open. Removal of a portion of the dielectric material can then be tailored to expose a bottom of the open trenches while leaving remaining trenches filled. Removal of exposed portions of the underlying substrate can then be used to selectively deepen the open trenches, which can subsequently be filled. Such methods can be used to form trenches of varying depths without the need for subsequent masking.
摘要翻译：集成电路器件内的多个沟槽深度通过首先将衬底中的沟槽形成第一深度但具有变化的宽度来形成。电介质层的形成可以使一些沟槽填充或封闭，同时留下其他更宽的沟槽打开。然后可以去除电介质材料的一部分以暴露开口沟槽的底部，同时留下剩余的沟槽填充。然后可以去除下面的衬底的暴露部分以选择性地加深可以随后填充的开放沟槽。这种方法可用于形成不同深度的沟槽，而不需要随后的掩蔽。

38. 发明授权

US07119369B2 FET having epitaxial silicon growth 有权
标题翻译：具有外延硅生长的FET
公开(公告)号：US07119369B2
公开(公告)日：2006-10-10
申请号：US10758059
申请日：2004-01-15
申请人： Zhongze Wang , Chih-Chen Cho , Er-Xuan Ping
发明人： Zhongze Wang , Chih-Chen Cho , Er-Xuan Ping
IPC分类号： H01L27/108
CPC分类号： H01L29/66651 , H01L21/76264 , H01L29/0653
摘要： A field-effect transistor has a channel region in a bulk semiconductor substrate, a first source/drain region on a first side of the channel region, a second source/drain region on a second side of the channel region, and an extension of epitaxial monocrystalline material formed on the bulk semiconductor substrate so as to extend away from each side of the channel region.
摘要翻译：场效应晶体管具有体半导体衬底中的沟道区，沟道区的第一侧上的第一源极/漏极区，沟道区的第二侧上的第二源极/漏极区和外延的延伸形成在体半导体衬底上以便从沟道区的每一侧延伸的单晶材料。

39. 发明申请

US20060091479A1 Applying epitaxial silicon in disposable spacer flow 有权
公开(公告)号：US20060091479A1
公开(公告)日：2006-05-04
申请号：US11305597
申请日：2005-12-16
申请人： Chih-Chen Cho , Er-Xuan Ping
发明人： Chih-Chen Cho , Er-Xuan Ping
IPC分类号： H01L29/76
CPC分类号： H01L27/10894 , H01L21/28525 , H01L21/823418 , H01L21/823468 , H01L21/823481 , H01L27/105 , H01L27/10873 , H01L27/11526 , H01L27/11546 , H01L29/66636
摘要： A process for forming active transistors for a semiconductor memory device by the steps of: forming transistor gates having generally vertical sidewalls in a memory array section and in periphery section; implanting a first type of conductive dopants into exposed silicon defined as active area regions of the transistor gates; forming temporary oxide spacers on the generally vertical sidewalls of the transistor gates; after the step of forming temporary spacers, implanting a second type of conductive dopants into the exposed silicon regions to form source/drain regions of the active transistors; after the step of implanting a second type of conductive dopants, growing an epitaxial silicon over exposed silicon regions; removing the temporary oxide spacers; and forming permanent nitride spacers on the generally vertical sidewalls of the transistor gates.

40. 发明授权

US06962841B2 Suppression of cross diffusion and gate depletion 有权
公开(公告)号：US06962841B2
公开(公告)日：2005-11-08
申请号：US10659081
申请日：2003-09-10
申请人： John D. Trivedi , Zhongze Wang , Chih-Chen Cho , Mike Violette , Todd R. Abbott
发明人： John D. Trivedi , Zhongze Wang , Chih-Chen Cho , Mike Violette , Todd R. Abbott
IPC分类号： G11C11/412 , H01L21/8238 , H01L21/8244 , H01L27/11
CPC分类号： G11C11/412 , H01L21/823842 , H01L21/823871 , H01L21/823878 , H01L27/11 , H01L27/1104
摘要： According to the present invention, an ultrathin buried diffusion barrier layer (UBDBL) is formed over all or part of the doped polysilicon layer of a polysilicide structure composed of the polycrystalline silicon film and an overlying film of a metal, metal silicide, or metal nitride. More specifically, according to one embodiment of the present invention, a memory cell is provided comprising a semiconductor substrate, a P well, an N well, an N type active region, a P type active region, an isolation region, a polysilicide gate electrode structure, and a diffusion barrier layer. The P well is formed in the semiconductor substrate. The N well is formed in the semiconductor substrate adjacent to the P well. The N type active region is defined in the P well and the P type active region is defined in the N well. The isolation region is arranged to isolate the N type active region from the P type active region. The polysilicide gate electrode structure is composed of a polycrystalline silicon film and an overlying metal, metal silicide, or metal nitride film. The polycrystalline silicon film comprises an N+ polysilicon layer formed with the N type active region and a P+ polysilicon layer formed with the P type active region. The diffusion barrier layer is formed in the polysilicide gate electrode structure over a substantial portion of the polycrystalline silicon film between the polycrystalline silicon film and the metal, metal silicide, or metal nitride film.

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