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31. 发明申请

US20080157266A1 STI LINER MODIFICATION METHOD 审中-公开
标题翻译： STI LINER修改方法
公开(公告)号：US20080157266A1
公开(公告)日：2008-07-03
申请号：US12049452
申请日：2008-03-17
申请人： Chien-Hao Chen , Vincent S. Chang , Chia-Lin Chen , Tze-Liang Lee , Shih-Chang Chen
发明人： Chien-Hao Chen , Vincent S. Chang , Chia-Lin Chen , Tze-Liang Lee , Shih-Chang Chen
IPC分类号： H01L21/762
CPC分类号： H01L21/76235
摘要： A new and improved liner modification method for a liner oxide layer in an STI trench is disclosed. According to the method, an STI trench is etched in a substrate and a liner oxide layer is formed on the trench surfaces by oxidation techniques. The method further includes pre-treatment of the trench surfaces using a nitrogen-containing gas prior to formation of the liner oxide layer, post-formation nitridation of the liner oxide layer, or both pre-treatment of the trench surfaces and post-formation nitridation of the liner oxide layer. The liner modification method of the present invention optimizes the inverse narrow width effect (INWE) and gate oxide integrity (GOI) of STI structures and prevents diffusion of dopant into the liner oxide layer during subsequent processing.
摘要翻译：公开了一种用于STI沟槽中的衬垫氧化物层的新的改进的衬垫修改方法。根据该方法，在衬底中蚀刻STI沟槽，并且通过氧化技术在沟槽表面上形成衬垫氧化物层。该方法还包括在形成衬垫氧化物层之前使用含氮气体预处理沟槽表面，衬里氧化物层的形成后氮化或沟槽表面的预处理和后形成氮化的衬里氧化物层。本发明的衬垫修改方法优化STI结构的反窄窄度效应（INWE）和栅极氧化物完整性（GOI），并防止掺杂剂在随后的处理期间扩散到衬里氧化物层中。

32. 发明申请

US20080128765A1 MOSFET Device With Localized Stressor 审中-公开
标题翻译：具有局部应力的MOSFET器件
公开(公告)号：US20080128765A1
公开(公告)日：2008-06-05
申请号：US12016499
申请日：2008-01-18
申请人： Chien-Hao Chen , Donald Y. Chao , Tze-Liang Lee , Shih-Chang Chen
发明人： Chien-Hao Chen , Donald Y. Chao , Tze-Liang Lee , Shih-Chang Chen
IPC分类号： H01L29/78
CPC分类号： H01L29/7833 , H01L29/6659 , H01L29/7843
摘要： A metal-oxide-semiconductor field-effect transistors (MOSFET) having localized stressors is provided. In accordance with embodiments of the present invention, a transistor comprises a high-stress film over the source/drain regions, but not over the gate electrode. The high-stress film may be a tensile-stress film for use with n-channel devices or a compressive-stress film for use with p-channel devices. A method of fabricating a MOSFET with localized stressors over the source/drain regions comprises forming a transistor having a gate electrode and source/drain regions, forming a high-stress film over the gate electrode and the source/drain regions, and thereafter removing the high-stress film located over the gate electrode, thereby leaving the high-stress film located over the source/drain regions. A contact-etch stop layer may be formed over the transistor.
摘要翻译：提供了具有局部应力源的金属氧化物半导体场效应晶体管（MOSFET）。根据本发明的实施例，晶体管包括源/漏区上的高应力膜，但不在栅电极上。高应力膜可以是用于n沟道器件的拉伸应力膜或用于p沟道器件的压应力膜。在源极/漏极区域上制造具有局部应力源的MOSFET的方法包括形成具有栅电极和源/漏区的晶体管，在栅电极和源/漏区上形成高应力膜，然后除去高应力膜位于栅电极之上，从而使高应力膜位于源极/漏极区之上。接触蚀刻停止层可以形成在晶体管上。

33. 发明申请

US20070298565A1 Junction leakage reduction in SiGe process by implantation 有权
标题翻译：通过植入SiGe工艺中的结漏电减少
公开(公告)号：US20070298565A1
公开(公告)日：2007-12-27
申请号：US11523274
申请日：2006-09-19
申请人： Chun-Feng Nieh , Chien-Hao Chen , Keh-Chiang Ku , Tze-Liang Lee , Shih-Chang Chen
发明人： Chun-Feng Nieh , Chien-Hao Chen , Keh-Chiang Ku , Tze-Liang Lee , Shih-Chang Chen
IPC分类号： H01L21/8238
CPC分类号： H01L29/7848 , H01L29/1083 , H01L29/165 , H01L29/6653 , H01L29/66636 , H01L29/7834
摘要： A method for forming a semiconductor device is provided. The method includes providing a semiconductor substrate, forming a gate dielectric over the semiconductor substrate, forming a gate electrode on the gate dielectric, forming a stressor in the semiconductor substrate adjacent an edge of the gate electrode, and implanting an impurity after the step of forming the stressor. The impurity is preferably selected from the group consisting essentially of group IV elements, inert elements, and combinations thereof.
摘要翻译：提供一种形成半导体器件的方法。该方法包括提供半导体衬底，在半导体衬底上形成栅极电介质，在栅极电介质上形成栅电极，在与栅电极的边缘相邻的半导体衬底中形成应力器，并在形成步骤之后注入杂质压力源。杂质优选选自基本上由IV族元素，惰性元素及其组合组成的组。

34. 发明申请

US20060183279A1 METHOD FOR SELECTIVELY STRESSING MOSFETS TO IMPROVE CHARGE CARRIER MOBILITY 审中-公开
标题翻译：选择性地压力MOSFET以提高电荷载流子迁移率的方法
公开(公告)号：US20060183279A1
公开(公告)日：2006-08-17
申请号：US11279016
申请日：2006-04-07
申请人： Chien-Hao Chen , Chia-Lin Chen , Ju-Wang Hsu , Tze-Liang Lee , Shih-Chang Chen
发明人： Chien-Hao Chen , Chia-Lin Chen , Ju-Wang Hsu , Tze-Liang Lee , Shih-Chang Chen
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L29/7843
摘要： A strained channel MOSFET device with improved charge mobility and method for forming the same, the method including providing a first gate with a first semiconductor conductive type and second gate with a semiconductor conductive type on a substrate; forming a first strained layer with a first type of stress on said first gate; and, forming a second strained layer with a second type of stress on said second gate.
摘要翻译：一种具有改善的电荷迁移率的应变通道MOSFET器件及其形成方法，所述方法包括在衬底上提供具有半导体导电类型的第一半导体导电类型的第一栅极和第二栅极; 在所述第一栅极上形成具有第一类型应力的第一应变层; 并且在所述第二浇口上形成具有第二类型应力的第二应变层。

35. 发明申请

US20060151808A1 MOSFET device with localized stressor 审中-公开
公开(公告)号：US20060151808A1
公开(公告)日：2006-07-13
申请号：US11034282
申请日：2005-01-12
申请人： Chien-Hao Chen , Pang-Yen Tsai , Chie-Chien Chang , Tze-Liang Lee , Shih-Chang Chen
发明人： Chien-Hao Chen , Pang-Yen Tsai , Chie-Chien Chang , Tze-Liang Lee , Shih-Chang Chen
IPC分类号： H01L31/109 , H01L21/8234 , H01L21/477
CPC分类号： H01L21/26506 , H01L21/28518 , H01L21/28525 , H01L21/823807 , H01L29/165 , H01L29/45 , H01L29/517 , H01L29/518 , H01L29/66628 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： MOSFETs having localized stressors are provided. The MOSFET has a stress-inducing layer formed in the source/drain regions, wherein the stress-inducing layer comprises a first semiconductor material and a second semiconductor material. A treatment is performed on the stress-inducing layer such that a reaction is caused with the first semiconductor material and the second semiconductor material is forced lower into the stress-inducing layer. The stress-inducing layer may be either a recessed region or non-recessed region. A first method involves forming a stress-inducing layer, such as SiGe, in the source/drain regions and performing a nitridation or oxidation process. A nitride or oxide film is formed in the top portion of the stress-inducing layer, forcing the Ge lower into the stress-inducing layer. Another method embodiment involves forming a reaction layer over the stress-inducing layer and performing a treatment process to cause the reaction layer to react with the stress-inducing layer.

36. 发明授权

US07052946B2 Method for selectively stressing MOSFETs to improve charge carrier mobility 有权
公开(公告)号：US07052946B2
公开(公告)日：2006-05-30
申请号：US10798960
申请日：2004-03-10
申请人： Chien-Hao Chen , Chia-Lin Chen , Ju-Wang Hsu , Tze-Liang Lee , Shih-Chang Chen
发明人： Chien-Hao Chen , Chia-Lin Chen , Ju-Wang Hsu , Tze-Liang Lee , Shih-Chang Chen
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L29/7843
摘要： A strained channel MOSFET device with improved charge mobility and method for forming the same, the method including providing a first gate with a first semiconductor conductive type and second gate with a semiconductor conductive type on a substrate; forming a first strained layer with a first type of stress on said first gate; and, forming a second strained layer with a second type of stress on said second gate.

37. 发明申请

US20060014396A1 Method for forming a resist protect layer 有权
标题翻译：形成抗蚀剂保护层的方法
公开(公告)号：US20060014396A1
公开(公告)日：2006-01-19
申请号：US10892014
申请日：2004-07-14
申请人： Chien-Hao Chen , Ju-Wang Hsu , Chia-Lin Chen , Tze-Liang Lee , Shih-Chang Chen
发明人： Chien-Hao Chen , Ju-Wang Hsu , Chia-Lin Chen , Tze-Liang Lee , Shih-Chang Chen
IPC分类号： H01L21/302 , H01L21/31
CPC分类号： H01L21/31111 , H01L21/823481 , H01L29/665 , H01L29/6656 , H01L29/78
摘要： A method for forming a resist protect layer on a semiconductor substrate includes the following steps. An isolation structure is formed on the semiconductor substrate. An original nitride layer having a substantial etch selectivity to the isolation structure is formed over the semiconductor substrate. A photoresist mask is formed for partially covering the original nitride layer. A wet etching is performed to remove the original nitride layer uncovered by the photoresist mask in such a way without causing substantial damage to the isolation structure. As such, the original nitride layer covered by the photoresist mask constitutes the resist protect layer.
摘要翻译：在半导体衬底上形成抗蚀剂保护层的方法包括以下步骤。在半导体衬底上形成隔离结构。在半导体衬底上形成对隔离结构具有实质蚀刻选择性的原始氮化物层。形成光致抗蚀剂掩模以部分覆盖原始氮化物层。执行湿蚀刻以以这样的方式去除由光致抗蚀剂掩模未覆盖的原始氮化物层，而不会对隔离结构造成实质损坏。因此，由光致抗蚀剂掩模覆盖的原始氮化物层构成抗蚀剂保护层。

38. 发明申请

US20050214998A1 Local stress control for CMOS performance enhancement 审中-公开
标题翻译： CMOS性能提升的局部应力控制
公开(公告)号：US20050214998A1
公开(公告)日：2005-09-29
申请号：US10810795
申请日：2004-03-26
申请人： Chien-Hao Chen , Chia-Lin Chen , Tze-Liang Lee , Shih-Chang Chen
发明人： Chien-Hao Chen , Chia-Lin Chen , Tze-Liang Lee , Shih-Chang Chen
IPC分类号： H01L21/44 , H01L21/768 , H01L21/8238
CPC分类号： H01L21/76829 , H01L21/823807 , H01L21/823828 , H01L29/7843
摘要： A semiconductor device and method for forming the same for improving charge mobility in NMOS and PMOS devices simultaneously, the method including forming a first dielectric layer including a stress type selected from the group consisting of tensile stress and compressive stress over the respective PMOS and NMOS device regions; removing a portion of the first dielectric layer overlying one of the PMOS and NMOS device regions; forming a second dielectric layer including a stress type opposite from the first dielectric layer stress type over the respective PMOS and NMOS device regions; and, removing a portion of the second dielectric layer overlying one of the PMOS and NMOS device regions having an underlying first dielectric layer to form a compressive stress dielectric layer over the PMOS device region and a tensile stress dielectric layer over the NMOS device region.
摘要翻译：一种半导体器件及其制造方法，用于同时改善NMOS和PMOS器件的电荷迁移率，该方法包括形成第一介电层，该第一介电层包括在相应的PMOS和NMOS器件上包括拉应力和压应力的应力类型区域; 去除覆盖所述PMOS和NMOS器件区域中的一个的所述第一电介质层的一部分; 在相应的PMOS和NMOS器件区域上形成包括与第一介电层应力型相反的应力类型的第二介质层; 以及去除覆盖具有下面的第一介电层的PMOS器件区域和NMOS器件区域之一的第二介电层的一部分，以在PMOS器件区域上形成压应力介电层，并在NMOS器件区域上形成拉伸应力介电层。

39. 发明申请

US20050199958A1 Method for selectively stressing MOSFETs to improve charge carrier mobility 有权
标题翻译：选择性地强迫MOSFET以改善载流子迁移率的方法
公开(公告)号：US20050199958A1
公开(公告)日：2005-09-15
申请号：US10798960
申请日：2004-03-10
申请人： Chien-Hao Chen , Chia-Lin Chen , Ju-Wang Hsu , Tze-Liang Lee , Shih-Chang Chen
发明人： Chien-Hao Chen , Chia-Lin Chen , Ju-Wang Hsu , Tze-Liang Lee , Shih-Chang Chen
IPC分类号： H01L21/8238 , H01L29/76
CPC分类号： H01L21/823807 , H01L29/7843
摘要： A strained channel MOSFET device with improved charge mobility and method for forming the same, the method including providing a first gate with a first semiconductor conductive type and second gate with a semiconductor conductive type on a substrate; forming a first strained layer with a first type of stress on said first gate; and, forming a second strained layer with a second type of stress on said second gate.
摘要翻译：一种具有改善的电荷迁移率的应变沟道MOSFET器件及其形成方法，所述方法包括在衬底上提供具有半导体导电类型的第一半导体导电类型的第一栅极和第二栅极; 在所述第一栅极上形成具有第一类型应力的第一应变层; 并且在所述第二浇口上形成具有第二类型应力的第二应变层。

40. 发明申请

US20070037326A1 Shallow source/drain regions for CMOS transistors 审中-公开
标题翻译： CMOS晶体管的浅源极/漏极区域
公开(公告)号：US20070037326A1
公开(公告)日：2007-02-15
申请号：US11200374
申请日：2005-08-09
申请人： Chien-Hao Chen , Chun-Feng Nieh , Tze-Liang Lee
发明人： Chien-Hao Chen , Chun-Feng Nieh , Tze-Liang Lee
IPC分类号： H01L21/84
CPC分类号： H01L21/26506 , H01L21/26513 , H01L21/2658 , H01L29/6659 , H01L29/66772 , H01L29/7833
摘要： A transistor having shallow, high-dopant concentration source/drain regions is provided. A gate electrode is formed on a substrate, and the source/drain regions of the substrate are transformed into an amorphous state by, for example, implanting Si, Ge, Xe, In, Ar, Kr, Rn, a combination thereof, or the like ions. A co-implantation process is performed to implant ions of C, N, F, a combination thereof, or the like in the source/drain regions. Thereafter, one or more implants may be performed to form the LDD and source/drain regions and the substrate is recrystallized. The amorphous regions and the co-implantation regions effectively confine or reduce the diffusion of the ions used to form the LDD and source/drain regions.
摘要翻译：提供具有浅掺杂浓度源/漏区的晶体管。在基板上形成栅电极，通过例如注入Si，Ge，Xe，In，Ar，Kr，Rn及其组合，将基板的源极/漏极区域变换为非晶态，或像离子。执行共注入工艺以在源极/漏极区域中注入C，N，F，它们的组合等的离子。此后，可以执行一个或多个植入物以形成LDD和源极/漏极区域，并且衬底被重结晶。非晶区域和共注入区域有效地限制或减少用于形成LDD和源极/漏极区域的离子的扩散。

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