专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明授权

US06197706B1 Low temperature method to form low k dielectric 有权
标题翻译：低温方法形成低k电介质
公开(公告)号：US06197706B1
公开(公告)日：2001-03-06
申请号：US09607042
申请日：2000-06-30
申请人： Lain-Jang Li , Cheng-Chung Lin , Syun-Ming Jang
发明人： Lain-Jang Li , Cheng-Chung Lin , Syun-Ming Jang
IPC分类号： H01L2131
CPC分类号： H01L21/3146
摘要： Black diamond films, deposited using PECVD at low substrate temperatures, have been effectively stabilized by immersing them in de-ionized water at a temperature of about 90° C. for about 20 minutes or in a hydrogen peroxide solution (typically at a concentration of 10%) for about 60 minutes. Since it has been observed that the dielectric constant of the stabilized film increases with both immersion time and/or peroxide concentration, this effect may be used as a means for adjusting the dielectric constant of a black diamond film. Standard analytical techniques confirm that these low temperature stabilized films have electrical properties that are at least as good as those of films stabilized using high temperature heat treatments.
摘要翻译：通过在约90℃的温度下将它们浸入去离子水中约20分钟或在过氧化氢溶液中（通常浓度为10），已经有效地稳定了在低基材温度下使用PECVD沉积的黑色金刚石膜％）约60分钟。由于已经观察到稳定的膜的介电常数随着浸渍时间和/或过氧化物浓度的增加而增加，所以该效果可以用作调整黑色金刚石膜的介电常数的手段。标准分析技术证实这些低温稳定膜的电性能至少与使用高温热处理稳定的膜的电性能一样好。

32. 发明授权

US08560997B1 Conditional cell placement 有权
标题翻译：条件细胞放置
公开(公告)号：US08560997B1
公开(公告)日：2013-10-15
申请号：US13557578
申请日：2012-07-25
申请人： Ping-Lin Yang , Ming-Zhang Kuo , Cheng-Chung Lin , Jimmy Hsiao , Jia-Rong Hsu
发明人： Ping-Lin Yang , Ming-Zhang Kuo , Cheng-Chung Lin , Jimmy Hsiao , Jia-Rong Hsu
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： Among other things, one or more techniques for conditional cell placement are provided herein. In an embodiment, a conditional boundary is created for a first cell. For example, the conditional boundary enables the first cell to be placed relative to a second cell based on a conditional placement rule. In an embodiment, the first cell is placed in a first manner relative to the second cell based in a first scenario. In a second scenario, different than the first scenario, the first cell is placed in a second manner relative to the second cell. In this manner, conditional cell placement is provided, thus providing flexibility and improved layout efficiency with regard to semiconductor fabrication, for example.
摘要翻译：其中还提供了一种或多种用于条件单元放置的技术。在一个实施例中，为第一小区创建条件边界。例如，条件边界使得能够基于条件放置规则相对于第二单元放置第一单元。在一个实施例中，基于第一情况，第一小区相对于第二小区以第一方式放置。在第二种情况下，与第一种情况不同，第一单元相对于第二单元以第二种方式放置。以这种方式，提供条件单元布置，从而提供例如关于半导体制造的灵活性和改进的布局效率。

33. 发明授权

US07271103B2 Surface treated low-k dielectric as diffusion barrier for copper metallization 有权
标题翻译：表面处理的低k电介质作为铜金属化的扩散阻挡层
公开(公告)号：US07271103B2
公开(公告)日：2007-09-18
申请号：US10687713
申请日：2003-10-17
申请人： Kuei-Wu Huang , Ai-Sen Liu , Baw-Ching Perng , Ming-Ta Lei , Wen-Kai Wan , Cheng-Chung Lin , Yih-Shung Lin , Chia-Hui Lin
发明人： Kuei-Wu Huang , Ai-Sen Liu , Baw-Ching Perng , Ming-Ta Lei , Wen-Kai Wan , Cheng-Chung Lin , Yih-Shung Lin , Chia-Hui Lin
IPC分类号： H01L21/302
CPC分类号： H01L21/02137 , H01L21/02332 , H01L21/0234 , H01L21/02351 , H01L21/02362 , H01L21/31058 , H01L21/3122 , H01L21/3124 , H01L21/3148 , H01L21/3185 , H01L21/76825 , H01L21/76826 , H01L21/76829
摘要： A Cu damascene structure is formed where Cu diffusion barrier is formed by treating the top surface of the surrounding low-k interlayer dielectric with nitrogen or carbon containing medium to form a silicon nitride or silicon carbide diffusion barrier rather than capping the top surface of the Cu with metal diffusion barrier as is conventionally done.
摘要翻译：形成Cu镶嵌结构，其中通过用含氮或碳的介质处理周围的低k层间电介质的顶表面形成Cu扩散阻挡层，以形成氮化硅或碳化硅扩散阻挡层，而不是封盖Cu的顶表面具有如以往所做的金属扩散阻挡层。

34. 发明申请

US20060001160A1 Surface treatment of metal interconnect lines 有权
标题翻译：金属互连线的表面处理
公开(公告)号：US20060001160A1
公开(公告)日：2006-01-05
申请号：US11213238
申请日：2005-08-26
申请人： Wen-Kai Wan , Yih-Hsiung Lin , Ming-Ta Lei , Baw-Ching Perng , Cheng-Chung Lin , Chia-Hui Lin , Ai-Sen Liu
发明人： Wen-Kai Wan , Yih-Hsiung Lin , Ming-Ta Lei , Baw-Ching Perng , Cheng-Chung Lin , Chia-Hui Lin , Ai-Sen Liu
IPC分类号： H01L29/40 , H01L23/52 , H01L23/48 , B32B15/00 , B32B17/06
CPC分类号： H01L21/76843 , H01L21/288 , H01L21/76849 , H01L21/76858 , H01L21/76886
摘要： Apparatus for forming a semiconductor structure comprising a first layer on top of a substrate wherein the first layer defines conductive regions such as copper interconnect lines and non-conductive regions such as dielectric materials. The conductive regions are covered by a second layer of a material different than the first layer such as for example nickel and then the structure is heat treated such that the interconnect lines and second metal, such as a copper interconnect line and a nickel second layer, interact with each other to form an alloy layer. The alloy layer has superior qualities for adhering to both the copper interconnect lines and a subsequently deposited dielectric material.
摘要翻译：用于形成半导体结构的装置，其包括在衬底的顶部上的第一层，其中第一层限定诸如铜互连线和非导电区域（例如介电材料）的导电区域。导电区域被不同于第一层的材料的第二层（例如镍）覆盖，然后对该结构进行热处理，使得互连线和第二金属（例如铜互连线和镍第二层）相互作用形成合金层。合金层具有优异的粘附于铜互连线和随后沉积的电介质材料的品质。

35. 发明授权

US06955984B2 Surface treatment of metal interconnect lines 有权
标题翻译：金属互连线的表面处理
公开(公告)号：US06955984B2
公开(公告)日：2005-10-18
申请号：US10439358
申请日：2003-05-16
申请人： Wen-Kai Wan , Yih-Hsiung Lin , Ming-Dai Lei , Baw-Ching Perng , Cheng-Chung Lin , Chia-Hui Lin , Ai-Sen Liu
发明人： Wen-Kai Wan , Yih-Hsiung Lin , Ming-Dai Lei , Baw-Ching Perng , Cheng-Chung Lin , Chia-Hui Lin , Ai-Sen Liu
IPC分类号： H01L21/288 , H01L21/44 , H01L21/445 , H01L21/768
CPC分类号： H01L21/76843 , H01L21/288 , H01L21/76849 , H01L21/76858 , H01L21/76886
摘要： Methods and apparatus for forming a semiconductor structure comprising a first layer on top of a substrate wherein the first layer defines conductive regions such as copper interconnect lines and non-conductive regions such as dielectric materials. The conductive regions are covered by a second layer of a material different than the first layer such as for example nickel and then the structure is heat treated such that the interconnect lines and second metal, such as a copper interconnect line and a nickel second layer, interact with each other to form an alloy layer. The alloy layer has superior qualities for adhering to both the copper interconnect lines and a subsequently deposited dielectric material.
摘要翻译：用于形成半导体结构的方法和装置包括在衬底的顶部上的第一层，其中第一层限定诸如铜互连线和非导电区域（例如介电材料）的导电区域。导电区域被不同于第一层的材料的第二层（例如镍）覆盖，然后对该结构进行热处理，使得互连线和第二金属（例如铜互连线和镍第二层）相互作用形成合金层。合金层具有优异的粘附于铜互连线和随后沉积的电介质材料的品质。

36. 发明申请

US20050085083A1 Surface treated low-k dielectric as diffusion barrier for copper metallization 有权
标题翻译：表面处理的低k电介质作为铜金属化的扩散阻挡层
公开(公告)号：US20050085083A1
公开(公告)日：2005-04-21
申请号：US10687713
申请日：2003-10-17
申请人： Kuei-Wu Huang , Ai-Sen Liu , Baw-Ching Perng , Ming-Ta Lei , Wen-Kai Wan , Cheng-Chung Lin , Yih-Shung Lin , Chia-Hui Lin
发明人： Kuei-Wu Huang , Ai-Sen Liu , Baw-Ching Perng , Ming-Ta Lei , Wen-Kai Wan , Cheng-Chung Lin , Yih-Shung Lin , Chia-Hui Lin
IPC分类号： H01L21/3105 , H01L21/312 , H01L21/314 , H01L21/318 , H01L21/768 , H01L21/302 , H01L21/461
CPC分类号： H01L21/02137 , H01L21/02332 , H01L21/0234 , H01L21/02351 , H01L21/02362 , H01L21/31058 , H01L21/3122 , H01L21/3124 , H01L21/3148 , H01L21/3185 , H01L21/76825 , H01L21/76826 , H01L21/76829
摘要： A Cu damascene structure is formed where Cu diffusion barrier is formed by treating the top surface of the surrounding low-k interlayer dielectric with nitrogen or carbon containing medium to form a silicon nitride or silicon carbide diffusion barrier rather than capping the top surface of the Cu with metal diffusion barrier as is conventionally done.
摘要翻译：形成Cu镶嵌结构，其中通过用含氮或碳的介质处理周围的低k层间电介质的顶表面形成Cu扩散阻挡层，以形成氮化硅或碳化硅扩散阻挡层，而不是封盖Cu的顶表面具有如以往所做的金属扩散阻挡层。

37. 外观设计

USD464501S1 Computer desk 失效
公开(公告)号：USD464501S1
公开(公告)日：2002-10-22
申请号：US29149299
申请日：2001-10-05
申请人： Cheng-Chung Lin
设计人： Cheng-Chung Lin

38. 发明授权

US08269549B2 Power supply circuit for PCI-E slot 有权
标题翻译： PCI-E插槽电源电路
公开(公告)号：US08269549B2
公开(公告)日：2012-09-18
申请号：US13048973
申请日：2011-03-16
申请人： Cheng-Chung Lin , Wu Jiang
发明人： Cheng-Chung Lin , Wu Jiang
IPC分类号： G11C5/14
CPC分类号： G06F1/26
摘要： A power supply circuit for a PCI-E slot includes a control chip, a first electronic switch, and a second electronic switch. The control chip determines a status of a motherboard, outputting a control signal. A first terminal of the first electronic switch is connected to the control chip to receive the control signal, and connected to a +3.3V dual power supply of the motherboard through a first resistor. A second terminal of the first electronic switch is grounded. A third terminal of the first electronic switch is connected to a first terminal of the second electronic switch, and connected to the +3.3V dual power supply through a second resistor. A second terminal of the second electronic switch is connected to the +3.3V dual power supply. A third terminal of the second electronic switch is connected to a PCI-E slot.
摘要翻译：用于PCI-E插槽的电源电路包括控制芯片，第一电子开关和第二电子开关。控制芯片确定主板的状态，输出控制信号。第一电子开关的第一端子连接到控制芯片以接收控制信号，并通过第一电阻器连接到主板的+ 3.3V双电源。第一个电子开关的第二个端子接地。第一电子开关的第三端子连接到第二电子开关的第一端子，并通过第二电阻器连接到+ 3.3V双电源。第二个电子开关的第二个端子连接到+ 3.3V双电源。第二电子开关的第三端子连接到PCI-E插槽。

39. 发明申请

US20100201490A1 DISPLAY DEVICE AND DISPLAY SYSTEM THEREOF 审中-公开
标题翻译：显示装置及其显示系统
公开(公告)号：US20100201490A1
公开(公告)日：2010-08-12
申请号：US12404850
申请日：2009-03-16
申请人： Chun-Hui Huang , Cheng-Chung Lin , Kuo-Yuan Tseng
发明人： Chun-Hui Huang , Cheng-Chung Lin , Kuo-Yuan Tseng
IPC分类号： H04B7/00
CPC分类号： G09G5/00 , G09G2330/02 , G09G2380/04
摘要： A display device includes a RFID tag unit, a display unit, a processing unit and a power supply unit. The RFID tag unit follows a wireless communication standard of a RFID system to receive a wireless signal and outputs identification information. The processing unit electrically connected with the RFID tag unit and the display unit receives the identification information and outputs to the display unit for displaying. The power supply unit supplies operation power required to the processing unit and the display unit. The required power while the above-mentioned display device refreshes the information is supplied by the power supply unit, so that the information can be refreshed with longer communication distance and power saving is achieved. A display system including the above-mentioned display device and a reader/writer device is also disclosed.
摘要翻译：显示装置包括RFID标签单元，显示单元，处理单元和电源单元。 RFID标签单元遵循RFID系统的无线通信标准，以接收无线信号并输出识别信息。与RFID标签单元和显示单元电连接的处理单元接收识别信息并输出到显示单元以进行显示。电源单元提供处理单元和显示单元所需的操作电源。当上述显示装置刷新信息时所需的功率由电源单元提供，使得可以以更长的通信距离刷新信息并实现功率节省。还公开了包括上述显示装置和读写器装置的显示系统。

40. 发明申请

US20060113616A1 Selective spacer layer deposition method for forming spacers with different widths 审中-公开
标题翻译：用于形成具有不同宽度的间隔物的选择性间隔层沉积方法
公开(公告)号：US20060113616A1
公开(公告)日：2006-06-01
申请号：US11206613
申请日：2005-08-18
申请人： Ai-Sen Liu , Baw-Ching Perng , Ming-Ta Lei , Yih-Shung Lin , Cheng-Chung Lin , Chia-Hui Lin
发明人： Ai-Sen Liu , Baw-Ching Perng , Ming-Ta Lei , Yih-Shung Lin , Cheng-Chung Lin , Chia-Hui Lin
IPC分类号： H01L29/94
CPC分类号： H01L21/823468 , H01L21/3105 , H01L21/3144 , H01L21/823456 , H01L29/6656
摘要： A method of forming spacers with different widths on a semiconductor substrate, includes the steps of disposing a first spacer layer over the substrate, defining the first spacer layer into a plurality of spacers of a first width, and disposing a second spacer layer selectively over the first spacer layer of a number of the spacers preselected for the second spacer layer, the predetermined number of the spacers with the second spacer layer each having a second width which is different from the first width.
摘要翻译：一种在半导体衬底上形成具有不同宽度的间隔物的方法，包括以下步骤：在衬底上设置第一间隔层，将第一间隔层限定为多个第一宽度的间隔物，并且在第为第二间隔层预选的多个间隔物的第一间隔层，具有第二间隔层的预定数量的间隔物各自具有与第一宽度不同的第二宽度。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式