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1. 发明授权

US06955984B2 Surface treatment of metal interconnect lines 有权
标题翻译：金属互连线的表面处理
公开(公告)号：US06955984B2
公开(公告)日：2005-10-18
申请号：US10439358
申请日：2003-05-16
申请人： Wen-Kai Wan , Yih-Hsiung Lin , Ming-Dai Lei , Baw-Ching Perng , Cheng-Chung Lin , Chia-Hui Lin , Ai-Sen Liu
发明人： Wen-Kai Wan , Yih-Hsiung Lin , Ming-Dai Lei , Baw-Ching Perng , Cheng-Chung Lin , Chia-Hui Lin , Ai-Sen Liu
IPC分类号： H01L21/288 , H01L21/44 , H01L21/445 , H01L21/768
CPC分类号： H01L21/76843 , H01L21/288 , H01L21/76849 , H01L21/76858 , H01L21/76886
摘要： Methods and apparatus for forming a semiconductor structure comprising a first layer on top of a substrate wherein the first layer defines conductive regions such as copper interconnect lines and non-conductive regions such as dielectric materials. The conductive regions are covered by a second layer of a material different than the first layer such as for example nickel and then the structure is heat treated such that the interconnect lines and second metal, such as a copper interconnect line and a nickel second layer, interact with each other to form an alloy layer. The alloy layer has superior qualities for adhering to both the copper interconnect lines and a subsequently deposited dielectric material.
摘要翻译：用于形成半导体结构的方法和装置包括在衬底的顶部上的第一层，其中第一层限定诸如铜互连线和非导电区域（例如介电材料）的导电区域。导电区域被不同于第一层的材料的第二层（例如镍）覆盖，然后对该结构进行热处理，使得互连线和第二金属（例如铜互连线和镍第二层）相互作用形成合金层。合金层具有优异的粘附于铜互连线和随后沉积的电介质材料的品质。

2. 发明授权

US08053894B2 Surface treatment of metal interconnect lines 有权
标题翻译：金属互连线的表面处理
公开(公告)号：US08053894B2
公开(公告)日：2011-11-08
申请号：US11213238
申请日：2005-08-26
申请人： Wen-Kai Wan , Yih-Hsiung Lin , Ming-Ta Lei , Baw-Ching Perng , Cheng-Chung Lin , Chia-Hui Lin , Ai-Sen Liu
发明人： Wen-Kai Wan , Yih-Hsiung Lin , Ming-Ta Lei , Baw-Ching Perng , Cheng-Chung Lin , Chia-Hui Lin , Ai-Sen Liu
IPC分类号： H01L23/48
CPC分类号： H01L21/76843 , H01L21/288 , H01L21/76849 , H01L21/76858 , H01L21/76886
摘要： Apparatus for forming a semiconductor structure comprising a first layer on top of a substrate wherein the first layer defines conductive regions such as copper interconnect lines and non-conductive regions such as dielectric materials. The conductive regions are covered by a second layer of a material different than the first layer such as for example nickel and then the structure is heat treated such that the interconnect lines and second metal, such as a copper interconnect line and a nickel second layer, interact with each other to form an alloy layer. The alloy layer has superior qualities for adhering to both the copper interconnect lines and a subsequently deposited dielectric material.
摘要翻译：用于形成半导体结构的装置，其包括在衬底的顶部上的第一层，其中第一层限定诸如铜互连线和非导电区域（例如介电材料）的导电区域。导电区域被不同于第一层的材料的第二层（例如镍）覆盖，然后对该结构进行热处理，使得互连线和第二金属（例如铜互连线和镍第二层）相互作用形成合金层。合金层具有优异的粘附于铜互连线和随后沉积的电介质材料的品质。

3. 发明申请

US20060001160A1 Surface treatment of metal interconnect lines 有权
标题翻译：金属互连线的表面处理
公开(公告)号：US20060001160A1
公开(公告)日：2006-01-05
申请号：US11213238
申请日：2005-08-26
申请人： Wen-Kai Wan , Yih-Hsiung Lin , Ming-Ta Lei , Baw-Ching Perng , Cheng-Chung Lin , Chia-Hui Lin , Ai-Sen Liu
发明人： Wen-Kai Wan , Yih-Hsiung Lin , Ming-Ta Lei , Baw-Ching Perng , Cheng-Chung Lin , Chia-Hui Lin , Ai-Sen Liu
IPC分类号： H01L29/40 , H01L23/52 , H01L23/48 , B32B15/00 , B32B17/06
CPC分类号： H01L21/76843 , H01L21/288 , H01L21/76849 , H01L21/76858 , H01L21/76886
摘要： Apparatus for forming a semiconductor structure comprising a first layer on top of a substrate wherein the first layer defines conductive regions such as copper interconnect lines and non-conductive regions such as dielectric materials. The conductive regions are covered by a second layer of a material different than the first layer such as for example nickel and then the structure is heat treated such that the interconnect lines and second metal, such as a copper interconnect line and a nickel second layer, interact with each other to form an alloy layer. The alloy layer has superior qualities for adhering to both the copper interconnect lines and a subsequently deposited dielectric material.
摘要翻译：用于形成半导体结构的装置，其包括在衬底的顶部上的第一层，其中第一层限定诸如铜互连线和非导电区域（例如介电材料）的导电区域。导电区域被不同于第一层的材料的第二层（例如镍）覆盖，然后对该结构进行热处理，使得互连线和第二金属（例如铜互连线和镍第二层）相互作用形成合金层。合金层具有优异的粘附于铜互连线和随后沉积的电介质材料的品质。

4. 发明申请

US20050098896A1 Integration film scheme for copper / low-k interconnect 有权
标题翻译：铜/低k互连的集成电路方案
公开(公告)号：US20050098896A1
公开(公告)日：2005-05-12
申请号：US10706156
申请日：2003-11-12
申请人： Tai-Chun Huang , Chih-Hsiang Yao , Yih-Hsiung Lin , Tien-I Bao , Bi-Trong Chen , Yung-Cheng Lu
发明人： Tai-Chun Huang , Chih-Hsiang Yao , Yih-Hsiung Lin , Tien-I Bao , Bi-Trong Chen , Yung-Cheng Lu
IPC分类号： H01L23/532 , H01L23/48
CPC分类号： H01L23/53295 , H01L23/53228 , H01L2924/0002 , H01L2924/00
摘要： A structure for a multi-level interconnect inter-level dielectric layer (ILD), a method of manufacturing thereof, and a semiconductor device including the ILD layer. The ILD layer includes a first low-dielectric constant material sub-layer, and a second low-dielectric constant material sub-layer disposed over the first low-dielectric constant material sub-layer. The second low-dielectric constant material sub-layer has at least one different material property than the first low-dielectric constant material sub-layer. A third low-dielectric constant material sub-layer is disposed over the second low-dielectric constant material sub-layer, the third low-dielectric constant material sub-layer having at least one different material property than the second low-dielectric constant material sub-layer. The first, second and third low-dielectric constant materials sub-layers are preferably comprised of the same material, deposited continuously in one or more deposition chambers while the deposition conditions such as the gas flow rate, power, or gas species are adjusted or changed.
摘要翻译：用于多层互连层间介电层（ILD）的结构，其制造方法以及包括ILD层的半导体器件。 ILD层包括第一低介电常数材料子层和设置在第一低介电常数材料子层上的第二低介电常数材料子层。第二低介电常数材料子层与第一低介电常数材料子层具有至少一种不同的材料特性。第三低介电常数材料子层设置在第二低介电常数材料副层上，第三低介电常数材料子层与第二低介电常数材料子层具有至少一种不同的材料特性 -层。第一，第二和第三低介电常数材料子层优选由相同的材料组成，其连续沉积在一个或多个沉积室中，同时调节或改变诸如气体流速，功率或气体种类的沉积条件。

5. 外观设计

USD362393S Clock 失效
公开(公告)号：USD362393S
公开(公告)日：1995-09-19
申请号：US17082
申请日：1994-01-04
申请人： Yih-Hsiung Lin
设计人： Yih-Hsiung Lin

6. 发明授权

US07244673B2 Integration film scheme for copper / low-k interconnect 有权
标题翻译：铜/低k互连的集成电路方案
公开(公告)号：US07244673B2
公开(公告)日：2007-07-17
申请号：US10706156
申请日：2003-11-12
申请人： Tai-Chun Huang , Chih-Hsiang Yao , Yih-Hsiung Lin , Tien-I Bao , Bi-Trong Chen , Yung-Cheng Lu
发明人： Tai-Chun Huang , Chih-Hsiang Yao , Yih-Hsiung Lin , Tien-I Bao , Bi-Trong Chen , Yung-Cheng Lu
IPC分类号： H01L21/469
CPC分类号： H01L23/53295 , H01L23/53228 , H01L2924/0002 , H01L2924/00
摘要： A structure for a multi-level interconnect inter-level dielectric layer (ILD), a method of manufacturing thereof, and a semiconductor device including the ILD layer. The ILD layer includes a first low-dielectric constant material sub-layer, and a second low-dielectric constant material sub-layer disposed over the first low-dielectric constant material sub-layer. The second low-dielectric constant material sub-layer has at least one different material property than the first low-dielectric constant material sub-layer. A third low-dielectric constant material sub-layer is disposed over the second low-dielectric constant material sub-layer, the third low-dielectric constant material sub-layer having at least one different material property than the second low-dielectric constant material sub-layer. The first, second and third low-dielectric constant materials sub-layers are preferably comprised of the same material, deposited continuously in one or more deposition chambers while the deposition conditions such as the gas flow rate, power, or gas species are adjusted or changed.
摘要翻译：用于多层互连层间介电层（ILD）的结构，其制造方法以及包括ILD层的半导体器件。 ILD层包括第一低介电常数材料子层和设置在第一低介电常数材料子层上的第二低介电常数材料子层。第二低介电常数材料子层与第一低介电常数材料子层具有至少一种不同的材料特性。第三低介电常数材料子层设置在第二低介电常数材料副层上，第三低介电常数材料子层与第二低介电常数材料子层具有至少一种不同的材料特性 -层。第一，第二和第三低介电常数材料子层优选由相同的材料组成，其连续沉积在一个或多个沉积室中，同时调节或改变诸如气体流速，功率或气体种类的沉积条件。

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