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31. 发明授权

US08907681B2 Timing skew characterization apparatus and method 有权
标题翻译：定时偏斜表征装置及方法
公开(公告)号：US08907681B2
公开(公告)日：2014-12-09
申请号：US13046148
申请日：2011-03-11
申请人： Chao Kai Chuang , Yen-Chien Lai , Hung-Jen Liao
发明人： Chao Kai Chuang , Yen-Chien Lai , Hung-Jen Liao
IPC分类号： G04F10/00 , G01R31/317 , G01R31/319
CPC分类号： G01R31/2837 , G01R31/31725 , G01R31/31726 , G01R31/31922 , H03K5/14
摘要： A timing skew characterization apparatus comprises a coarse timing skew characterization circuit, a fine timing skew characterization circuit and a coarse delay cell calibration circuit. The coarse timing skew characterization circuit comprises a plurality of coarse delay cells whose delays can be calibrated through the coarse delay cell calibration circuit. The calibration of fine delay cells can be implemented through a trail and error process. Both coarse delay step and fine delay step can be characterized through a single measurement setup. As a result, the timing skew characterization apparatus provides a high resolution setup and hold time measurement.
摘要翻译：定时偏差表征装置包括粗时序偏差表征电路，精确定时偏斜表征电路和粗延迟单元校准电路。粗定时偏斜表征电路包括多个粗延迟单元，其延迟可以通过粗延迟单元校准电路进行校准。精细延迟单元的校准可以通过跟踪和误差过程来实现。可以通过单个测量设置来表征粗延迟步长和精细延迟步长。结果，定时偏差表征装置提供高分辨率建立和保持时间测量。

32. 发明授权

US08455354B2 Layouts of POLY cut openings overlapping active regions 有权
标题翻译： POLY切割开口与活跃区域重叠的布局
公开(公告)号：US08455354B2
公开(公告)日：2013-06-04
申请号：US13081115
申请日：2011-04-06
申请人： Jung-Hsuan Chen , Yen-Huei Chen , Li-Chun Tien , Hung-Jen Liao
发明人： Jung-Hsuan Chen , Yen-Huei Chen , Li-Chun Tien , Hung-Jen Liao
IPC分类号： H01L21/28
CPC分类号： H01L21/32139 , H01L21/76816
摘要： A method of forming integrated circuits includes forming a mask layer over a gate electrode line, wherein the gate electrode line is over a well region of a semiconductor substrate; forming an opening in the mask layer, wherein a portion of the gate electrode line and a well pickup region of the well region are exposed through the opening; and removing the portion of the gate electrode line through the opening.
摘要翻译：形成集成电路的方法包括在栅电极线上形成掩模层，其中栅电极线在半导体衬底的阱区之上; 在所述掩模层中形成开口，其中所述栅电极线的一部分和所述阱区的阱拾取区域通过所述开口露出; 并且通过所述开口去除所述栅电极线的所述部分。

33. 发明授权

US08218354B2 SRAM word-line coupling noise restriction 有权
标题翻译： SRAM字线耦合噪声限制
公开(公告)号：US08218354B2
公开(公告)日：2012-07-10
申请号：US12649806
申请日：2009-12-30
申请人： Jhon Jhy Liaw , Hung-Jen Liao
发明人： Jhon Jhy Liaw , Hung-Jen Liao
IPC分类号： G11C11/00
CPC分类号： G11C5/063 , G11C11/412 , G11C11/413
摘要： A DC mode word-line coupling noise restriction circuit for multiple-port Random Access Memory cells. This circuit may comprise a Static Random Access Memory array. The SRAM array contains a plurality of columns and a plurality of rows with an SRAM cell formed at a cross-point of the columns and rows. Each SRAM cell has a first word-line conductor and a second word-line conductor. The first word-line conductor is connected to a first coupling noise restriction circuit. The first coupling noise restriction circuit comprises an inverter and a NMOSFET. The inverter has another NMOSFET and a PMOSFET.
摘要翻译：一种用于多端口随机存取存储单元的DC模式字线耦合噪声限制电路。该电路可以包括静态随机存取存储器阵列。 SRAM阵列包括多个列和多个行，其中SRAM单元形成在列和行的交叉点。每个SRAM单元具有第一字线和第二字线。第一字线导体连接到第一耦合噪声限制电路。第一耦合噪声限制电路包括反相器和NMOSFET。反相器具有另一个NMOSFET和PMOSFET。

34. 发明申请

US20100124099A1 8T LOW LEAKAGE SRAM CELL 有权
标题翻译： 8T低漏电SRAM单元
公开(公告)号：US20100124099A1
公开(公告)日：2010-05-20
申请号：US12273959
申请日：2008-11-19
申请人： Jui-Jen Wu , Yen-Huei Chen , Shao-Yu Chou , Hung-Jen Liao
发明人： Jui-Jen Wu , Yen-Huei Chen , Shao-Yu Chou , Hung-Jen Liao
IPC分类号： G11C11/412
CPC分类号： G11C11/412
摘要： This invention discloses a static random access memory (SRAM) cell comprising a pair of cross-coupled inverters having a storage node, and a NMOS transistor having a gate terminal, a first and a second source/drain terminal connected to the storage node, a read word-line (RWL) and a read bit-line (RBL), respectively, the RWL and RBL being activated during a read operation and not being activated during any write operation.
摘要翻译：本发明公开了一种静态随机存取存储器（SRAM）单元，其包括具有存储节点的一对交叉耦合的反相器，以及具有栅极端子，连接到存储节点的第一和第二源极/漏极端子的NMOS晶体管，分别读取字线（RWL）和读位线（RBL），RWL和RBL在读操作期间被激活，并且在任何写操作期间未被激活。

35. 发明授权

US07468903B2 Circuits for improving read and write margins in multi-port SRAMS 有权
公开(公告)号：US07468903B2
公开(公告)日：2008-12-23
申请号：US11598385
申请日：2006-11-13
申请人： Dao-Ping Wang , Hung-Jen Liao , Kun Lung Chen , Yung-Lung Lin , Jui-Jen Wu , Chen Yen-Huei
发明人： Dao-Ping Wang , Hung-Jen Liao , Kun Lung Chen , Yung-Lung Lin , Jui-Jen Wu , Chen Yen-Huei
IPC分类号： G11C11/00
CPC分类号： G11C11/412 , G11C8/08 , G11C11/413 , G11C11/418
摘要： A system and method for writing a SRAM cell coupled to complimentary first and second bit-lines (BLs) is disclosed, the method comprising asserting a word-line (WL) selecting the SRAM cell to a first positive voltage, providing a second positive voltage at the first BL, providing a first negative voltage at the second BL, and asserting a plurality of WLs not selecting the SRAM cell to a second negative voltage, wherein the writing margin of the SRAM cell is increased.

36. 发明申请

US20080137449A1 Dynamic power control for expanding SRAM write margin 有权
标题翻译：用于扩展SRAM写入余量的动态功耗控制
公开(公告)号：US20080137449A1
公开(公告)日：2008-06-12
申请号：US11636173
申请日：2006-12-08
申请人： Jui-Jen Wu , Kun-Lung Chen , Hung-Jen Liao , Yung-Lung Lin , Chen Yen-Huei , Dao-Ping Wang
发明人： Jui-Jen Wu , Kun-Lung Chen , Hung-Jen Liao , Yung-Lung Lin , Chen Yen-Huei , Dao-Ping Wang
IPC分类号： G11C7/00
CPC分类号： G11C11/413
摘要： A writing dynamic power control circuit is disclosed, which comprises a BL and its complementary BLB, at least one memory cell coupled to both the BL and BLB, a first NMOS transistor having a source, a drain and a gate coupled to the BL, the Vss and a first data signal, respectively, a second NMOS transistor having a source, a drain and a gate coupled to the BLB, the Vss and a second data signal, respectively, wherein the second data signal is complementary to the first data signal, a first PMOS transistor having a source, a drain and a gate coupled to a high voltage power supply (CVDD) node, the BLB and the BL, respectively, and a second PMOS transistor having a source, a drain and a gate coupled to the CVDD node, the BL and the BLB, respectively.
摘要翻译：公开了一种写入动态功率控制电路，其包括BL及其互补BLB，耦合到BL和BLB的至少一个存储单元，具有耦合到BL的源极，漏极和栅极的第一NMOS晶体管， Vss和第一数据信号，分别具有耦合到BLB的源极，漏极和栅极的第二NMOS晶体管，Vss和第二数据信号，其中第二数据信号与第一数据信号互补，第一PMOS晶体管，具有源极，漏极和栅极，分别耦合到高电压电源（CVDD）节点，BLB和BL，以及第二PMOS晶体管，其具有源极，漏极和栅极耦合到 CVDD节点，BL和BLB。

37. 发明申请

US20070008771A1 Tracking circuit for a memory device 有权
标题翻译：记忆装置的跟踪电路
公开(公告)号：US20070008771A1
公开(公告)日：2007-01-11
申请号：US11172873
申请日：2005-07-05
申请人： Cheng Lee , Simon Wang , Hung-Jen Liao
发明人： Cheng Lee , Simon Wang , Hung-Jen Liao
IPC分类号： G11C11/00 , G11C8/00 , G11C29/00 , G11C7/00
CPC分类号： G11C7/14 , G11C7/22 , G11C7/227 , G11C11/419
摘要： A memory device includes a memory array, an I/O circuit for accessing the memory array, and a tracking circuit. The tracking circuit includes a dummy bit line, a first tracking cell including a first NMOS transistor, the first tracking cell being coupled to receive a control signal and also coupled to the dummy bit line through the first NMOS transistor, and a second tracking cell including a second NMOS transistor, the second tracking cell being coupled to receive the control signal and also coupled to the dummy bit line through the second NMOS transistor, a gate of the second NMOS transistor being coupled to the dummy bit line. The memory device also includes a control circuit coupled to the dummy bit line for generating a clock signal for the I/O circuit.
摘要翻译：存储器件包括存储器阵列，用于访问存储器阵列的I / O电路和跟踪电路。跟踪电路包括虚拟位线，第一跟踪单元包括第一NMOS晶体管，第一跟踪单元被耦合以接收控制信号，并且还通过第一NMOS晶体管耦合到虚拟位线，第二跟踪单元包括第二NMOS晶体管，第二跟踪单元被耦合以接收控制信号，并且还通过第二NMOS晶体管耦合到虚拟位线，第二NMOS晶体管的栅极耦合到虚拟位线。存储器件还包括耦合到虚拟位线的控制电路，用于产生I / O电路的时钟信号。

38. 发明申请

US20050149891A1 Memory compiler with ultra low power feature and method of use 有权
标题翻译：内存编译器具有超低功耗特性和使用方法
公开(公告)号：US20050149891A1
公开(公告)日：2005-07-07
申请号：US10752116
申请日：2004-01-06
申请人： Ruei-Chin Luo , Hung-Jen Liao
发明人： Ruei-Chin Luo , Hung-Jen Liao
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： The present invention relates to a method of creating a design for a semiconductor memory. In an embodiment, a memory compiler for a semiconductor memory has access to a set of leaf cell designs for use by the memory compiler, the leaf cell designs comprising a power management circuit design as a leaf cell for a memory circuit. A user may elect to allow enablement of an ultra low power feature and the memory compiler creates a design which incorporates the power management circuit in a compiled semiconductor memory macro when the user-selectable option is enabled. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
摘要翻译：本发明涉及一种创建半导体存储器的设计的方法。在一个实施例中，用于半导体存储器的存储器编译器可以访问由存储器编译器使用的一组叶单元设计，叶单元设计包括作为存储器电路的叶单元的功率管理电路设计。用户可以选择允许启用超低功率特征，并且当用户可选择的选项被启用时，存储器编译器创建将编译半导体存储器宏中的电源管理电路合并的设计。要强调的是，该摘要被提供以符合要求摘要的规则，这将允许搜索者或其他读者快速确定技术公开的主题。提交它的理解是，它不会用于解释或限制权利要求的范围或含义。

39. 发明申请

US20050134342A1 Circuit and method for generating a signal pulse 审中-公开
标题翻译：用于产生信号脉冲的电路和方法
公开(公告)号：US20050134342A1
公开(公告)日：2005-06-23
申请号：US10741576
申请日：2003-12-18
申请人： Yung-Lung Lin , Hung-Jen Liao
发明人： Yung-Lung Lin , Hung-Jen Liao
IPC分类号： H03K3/017 , H03K5/04 , H03K5/06
CPC分类号： H03K5/06
摘要： A pulse generator is disclosed which comprises a clock buffer coupled to a data latch coupled to a delay unit; a logic device coupled to the delay unit and the data latch, the logic device adapted to logically combine signals generated from the delay unit and the data latch and to generate a signal pulse; and a signal reset unit coupled to the data latch. A method of generating a pulse is also disclosed, comprising generating a signal state by sensing a rising edge of an external clock; latching the signal state for generating a latched signal state; delaying the latched signal state for generating a delayed signal state; and logically combining the latched signal state and the delayed signal state for generating a signal pulse.
摘要翻译：公开了一种脉冲发生器，其包括耦合到耦合到延迟单元的数据锁存器的时钟缓冲器; 耦合到所述延迟单元和所述数据锁存器的逻辑器件，所述逻辑器件适于逻辑地组合由所述延迟单元产生的信号和所述数据锁存器并产生信号脉冲; 以及耦合到数据锁存器的信号复位单元。还公开了一种产生脉冲的方法，包括通过感测外部时钟的上升沿来产生信号状态; 锁存用于产生锁存信号状态的信号状态; 延迟锁存信号状态以产生延迟的信号状态; 并且逻辑地组合锁存信号状态和用于产生信号脉冲的延迟信号状态。

40. 发明授权

US09099199B2 Memory cell and memory array 有权
标题翻译：存储单元和存储器阵列
公开(公告)号：US09099199B2
公开(公告)日：2015-08-04
申请号：US13420931
申请日：2012-03-15
申请人： Tzu-Kuei Lin , Hung-Jen Liao , Jhon Jhy Liaw , Yen-Huei Chen
发明人： Tzu-Kuei Lin , Hung-Jen Liao , Jhon Jhy Liaw , Yen-Huei Chen
IPC分类号： G11C11/00 , G11C11/412
CPC分类号： G11C11/41 , G11C11/412
摘要： A memory cell includes a first, second, and third columns of devices. The first column of devices includes a first pull-down transistor, a second pull-down transistor, a first switch, and a second switch. The second column of devices includes a third pull-down transistor, a fourth pull-down transistor, a third switch, and a fourth switch. The third column of devices includes a first pull-up transistor, and a second pull-up transistor. The first pull-up transistor, the first pull-down transistor, and the third pull-down transistor are connected as a first inverter, and the second pull-up transistor, the second pull-down transistor, and the fourth pull-down transistor are connected as a second inverter. The first inverter and the second inverter are cross-coupled. The first switch, the second switch, the third switch, and the fourth switch are coupled with output terminals of the first and second inverters.
摘要翻译：存储器单元包括第一，第二和第三列器件。第一列器件包括第一下拉晶体管，第二下拉晶体管，第一开关和第二开关。第二列器件包括第三下拉晶体管，第四下拉晶体管，第三开关和第四开关。第三列器件包括第一上拉晶体管和第二上拉晶体管。第一上拉晶体管，第一下拉晶体管和第三下拉晶体管作为第一反相器连接，第二上拉晶体管，第二下拉晶体管和第四下拉晶体管作为第二反相器连接。第一个反相器和第二个反相器是交叉耦合的。第一开关，第二开关，第三开关和第四开关与第一和第二逆变器的输出端子耦合。

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