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31. 发明授权

US07152088B2 SQRT calculator capable of reducing error 失效
公开(公告)号：US07152088B2
公开(公告)日：2006-12-19
申请号：US10359539
申请日：2003-02-07
申请人： Bong-hwan Cho , Bong-soon Kang , Bong-guen Lee , Young-sun Kim
发明人： Bong-hwan Cho , Bong-soon Kang , Bong-guen Lee , Young-sun Kim
IPC分类号： G06F7/38
CPC分类号： G06F7/5525
摘要： A SQRT calculator capable of calculation with a minimal error is provided. The integer calculation unit selects a largest integer from a set of integers with a square of each of the integers smaller than an input datum. The transformation unit transforms the selected integer from the integer calculation unit by multiplying it by 2 and shifts a decimal point of the resulting number to the right by 1 place, thereby adding a certain number less than 10 to the decimal point shifted number to calculate a transformation value. The calculation unit shifts a decimal point of the number less than 10 to the left by 2 places and multiplies the transformation value by the resulting value, thereby subtracting the multiplied value from the input datum and choosing a largest number less than 10 with the subtracted value being in a desired range as a second decimal number of the square root. Thus, the SQRT calculator is capable of calculation with minimal error and, furthermore, has a minimum size of hardware.

32. 发明申请

US20060113578A1 Metal-insulator-metal capacitors with a chemical barrier layer in a lower electrode and methods of fabricating the same 有权
标题翻译：具有下电极中的化学阻挡层的金属 - 绝缘体 - 金属电容器及其制造方法
公开(公告)号：US20060113578A1
公开(公告)日：2006-06-01
申请号：US11216639
申请日：2005-09-01
申请人： Eun-ae Chung , Jae-hyoung Choi , Jung-hee Chung , Young-sun Kim , Cha-young Yoo
发明人： Eun-ae Chung , Jae-hyoung Choi , Jung-hee Chung , Young-sun Kim , Cha-young Yoo
IPC分类号： H01L27/108
CPC分类号： H01L21/7687 , H01L27/10852 , H01L28/65 , H01L28/75
摘要： A metal-insulator-metal (MIM) capacitor includes a lower electrode, a dielectric layer, and an upper electrode. The lower electrode includes a first conductive layer, a chemical barrier layer on the first conductive layer, and a second conductive layer on the chemical barrier layer. The chemical barrier layer is between the first and second conductive layers and is a different material than the first and second conductive layers. The dielectric layer is on the lower electrode. The upper electrode is on the dielectric layer opposite to the lower electrode. The first and second conductive layers can have the same thickness. The chemical barrier layer can be thinner than each of the first and second conductive layers. Related methods are discussed.
摘要翻译：金属绝缘体金属（MIM）电容器包括下电极，电介质层和上电极。下电极包括第一导电层，第一导电层上的化学阻挡层和化学阻挡层上的第二导电层。化学屏障层位于第一和第二导电层之间，并且是与第一和第二导电层不同的材料。介电层位于下电极上。上电极位于与下电极相对的电介质层上。第一和第二导电层可以具有相同的厚度。化学阻挡层可以比第一和第二导电层中的每一个薄。讨论相关方法。

33. 发明申请

US20050083252A1 Plasma display panel device using sub-field mode and method of driving the same 审中-公开
标题翻译：等离子显示面板装置采用子场模式及其驱动方法
公开(公告)号：US20050083252A1
公开(公告)日：2005-04-21
申请号：US10921956
申请日：2004-08-20
申请人： Chung-wook Roh , Young-sun Kim , Hye-jeong Kim
发明人： Chung-wook Roh , Young-sun Kim , Hye-jeong Kim
IPC分类号： H04N5/66 , G09F9/313 , G09G3/20 , G09G3/28 , G09G3/288 , G09G3/291 , G09G3/294 , G09G3/298 , H01J17/49
CPC分类号： G09G3/2803 , G09G3/294 , G09G3/2946 , G09G2320/0271 , G09G2320/066
摘要： Provided are a plasma display panel (PDP) device using a sub-field mode and a method of driving the PDP device. The method of driving the PDP includes allocating a first event pulse for generating an even number of light pulses or a second event pulse for generating an odd number of light pulses to each sub-field, and outputting sustain pulses, which generate light pulses, according to the allocated event pulse. Thus, linearity of the gray level can be improved and an image quality can be improved.
摘要翻译：提供了使用子场模式的等离子体显示面板（PDP）装置和驱动PDP装置的方法。驱动PDP的方法包括分配用于产生偶数个光脉冲的第一事件脉冲或用于产生每个子场的奇数个光脉冲的第二事件脉冲，并输出产生光脉冲的维持脉冲，根据到分配的事件脉冲。因此，可以提高灰度级的线性度并且可以提高图像质量。

34. 发明申请

US20050051828A1 Methods of forming metal thin films, lanthanum oxide films, and high dielectric films for semiconductor devices using atomic layer deposition 审中-公开
标题翻译：使用原子层沉积形成金属薄膜，氧化镧膜和用于半导体器件的高介电膜的方法
公开(公告)号：US20050051828A1
公开(公告)日：2005-03-10
申请号：US10828596
申请日：2004-04-21
申请人： Ki-yeon Park , Sung-tae Kim , Young-sun Kim , In-sung Park , Jae-hyun Yeo , Yun-jung Lee , Ki-vin Im
发明人： Ki-yeon Park , Sung-tae Kim , Young-sun Kim , In-sung Park , Jae-hyun Yeo , Yun-jung Lee , Ki-vin Im
IPC分类号： H01L21/20 , C23C16/40 , C23C16/44 , C23C16/455 , H01L21/314 , H01L21/316 , H01L21/8242 , H01B1/00 , H01L27/108 , H01L29/94 , H01L31/119 , H01L21/31
CPC分类号： H01L21/0228 , C23C16/40 , C23C16/45529 , C23C16/45553 , H01L21/02178 , H01L21/02192 , H01L21/022 , H01L21/02337 , H01L21/3141 , H01L21/31604 , H01L27/1085
摘要： The present invention provides methods of forming metal thin films, lanthanum oxide films and high dielectric films. Compositions of metal thin films, lanthanum oxide films and high dielectric films are also provided. Further provided are semiconductor devices comprising the metal thin films, lanthanum oxide films and high dielectric films provided herein.
摘要翻译：本发明提供形成金属薄膜，氧化镧膜和高介电膜的方法。还提供了金属薄膜，氧化镧薄膜和高介电薄膜的组成。还提供了包括金属薄膜，氧化镧膜和本文提供的高介电膜的半导体器件。

35. 发明授权

US06599807B2 Method for manufacturing capacitor of semiconductor device having improved leakage current characteristics 有权
公开(公告)号：US06599807B2
公开(公告)日：2003-07-29
申请号：US10034043
申请日：2001-12-20
申请人： Jae-soon Lim , Seung-hwan Lee , Han-mei Choi , Yun-jung Lee , Gab-jin Nam , Ki-yeon Park , Young-sun Kim , Sung-tae Kim
发明人： Jae-soon Lim , Seung-hwan Lee , Han-mei Choi , Yun-jung Lee , Gab-jin Nam , Ki-yeon Park , Young-sun Kim , Sung-tae Kim
IPC分类号： H01L2972
CPC分类号： H01L28/55
摘要： A method for manufacturing a capacitor of a semiconductor device is provided. The method includes the steps of: forming a first electrode on a semiconductor substrate; forming a dielectric layer on the first electrode; forming a second electrode on the dielectric layer; first annealing the capacitor having the first electrode, the dielectric layer, and the second electrode under oxygen atmosphere; and second annealing the capacitor having the first electrode, the dielectric layer, and the second electrode under vacuum.

36. 发明授权

US06398430B1 Semiconductor device fabrication system 失效
标题翻译：半导体器件制造系统
公开(公告)号：US06398430B1
公开(公告)日：2002-06-04
申请号：US09634999
申请日：2000-08-08
申请人： Gyu-chan Jeoung , Kwang-seok Choi , Jin-hang Jung , Young-sun Kim , Hong Lee , Hoe-sik Chung , Sung-ho Lee , Hun-hwan Ha
发明人： Gyu-chan Jeoung , Kwang-seok Choi , Jin-hang Jung , Young-sun Kim , Hong Lee , Hoe-sik Chung , Sung-ho Lee , Hun-hwan Ha
IPC分类号： G03D500
CPC分类号： G03F7/40 , G03F7/2024 , H01L21/308
摘要： A semiconductor device fabrication system for carrying out a UV-bake on a photoresist pattern in the semiconductor device pattern formation, includes a photoresist coating unit coating a wafer with a specific photoresist; a developing unit forming a photoresist pattern on the wafer coated with the photoresist; and a cross-linking and flow baking unit for cross-linking the photoresist pattern and subsequently flow baking the cross-linked photoresist pattern, wherein the cross-linking and flow baking unit thermally stabilizes the photoresist pattern prior to flow baking.
摘要翻译：一种用于在半导体器件图案形成中在光致抗蚀剂图案上进行UV烘烤的半导体器件制造系统包括用特定光致抗蚀剂涂覆晶片的光致抗蚀剂涂覆单元; 在涂有光致抗蚀剂的晶片上形成光刻胶图案的显影单元; 以及交联和流动烘烤单元，用于交联光致抗蚀剂图案，随后流动烘烤交联的光致抗蚀剂图案，其中交联和流动烘焙单元在流动烘烤之前热稳定光致抗蚀剂图案。

37. 发明授权

US06194263B1 Methods for forming capacitor structures including etching pits 失效
标题翻译：用于形成包括蚀刻坑的电容器结构的方法
公开(公告)号：US06194263B1
公开(公告)日：2001-02-27
申请号：US08729232
申请日：1996-10-09
申请人： Young-sun Kim , Young-wook Park
发明人： Young-sun Kim , Young-wook Park
IPC分类号： H01L218242
CPC分类号： H01L28/84 , H01L27/10852 , H01L28/90
摘要： A method for forming an electrode structure includes the steps of forming a conductive electrode on the microelectronic substrate, forming HSG-silicon seeds on the surface of the conductive electrode, and etching the conductive electrode using the HSG-silicon seeds as a mask so that pits are formed between the HSG-silicon seeds. In addition, the HSG-silicon seeds on the conductive electrode can be grown to form enlarged HSG-silicon bumps on the conductive electrode further increasing the surface area thereof. Related structures are also discussed.
摘要翻译：一种形成电极结构的方法包括以下步骤：在微电子衬底上形成导电电极，在导电电极的表面上形成HSG-硅晶种，并使用HSG-硅晶种作为掩模蚀刻导电电极，使得凹坑形成在HSG-硅种子之间。此外，导电电极上的HSG-硅晶种可以生长以在导电电极上形成扩大的HSG-硅凸块，进一步增加其表面积。还讨论了相关结构。

38. 发明授权

US6004858A Methods of forming hemispherical grained silicon (HSG-Si) capacitor structures including protective layers 失效
标题翻译：形成包括保护层的半球形硅（HSG-Si）电容器结构的方法
公开(公告)号：US6004858A
公开(公告)日：1999-12-21
申请号：US988858
申请日：1997-12-11
申请人： Se-jin Shim , Young-sun Kim , Cha-young Yoo , Young-wook Park
发明人： Se-jin Shim , Young-sun Kim , Cha-young Yoo , Young-wook Park
IPC分类号： H01L21/02 , H01L21/20
CPC分类号： H01L28/84
摘要： A method of forming a capacitor structure includes the steps of forming a conductive layer on a microelectronic substrate, and forming a first hemispherical grained silicon layer on the conductive layer opposite the substrate. A protective layer is formed on the hemispherical grained silicon layer. The protective layer, the first hemispherical grained silicon layer, and the conductive layer are then patterned so that portions of the microelectronic substrate are exposed adjacent the patterned conductive layer. A second hemispherical grained silicon layer is formed on the surface of the protective layer opposite the first hemispherical grained silicon layer, on sidewalls of the patterned conductive layer, and on the exposed portions of the microelectronic substrate. Portions of the second hemispherical grained silicon layer are removed from the exposed portions of the microelectronic substrate, and the patterned protective layer is then removed.
摘要翻译：一种形成电容器结构的方法包括以下步骤：在微电子衬底上形成导电层，并在与衬底相对的导电层上形成第一半球晶粒硅层。在半球状粒状硅层上形成保护层。然后对保护层，第一半球形晶粒硅层和导电层进行构图，使得微电子衬底的部分暴露在图案化导电层附近。在保护层的与第一半球状粒状硅层相对的表面上，在图案化的导电层的侧壁上，以及微电子衬底的露出部分上形成第二半球状粒状硅层。从微电子衬底的暴露部分去除第二半球形硅层的一部分，然后去除图案化的保护层。

39. 发明授权

US07973352B2 Capacitors having composite dielectric layers containing crystallization inhibiting regions 有权
标题翻译：具有包含结晶抑制区域的复合电介质层的电容器
公开(公告)号：US07973352B2
公开(公告)日：2011-07-05
申请号：US12754713
申请日：2010-04-06
申请人： Jae-hyoung Choi , Jung-hee Chung , Cha-young Yoo , Young-sun Kim , Se-hoon Oh
发明人： Jae-hyoung Choi , Jung-hee Chung , Cha-young Yoo , Young-sun Kim , Se-hoon Oh
IPC分类号： H01L29/94
CPC分类号： H01L29/92 , H01L27/10852 , H01L28/40
摘要： Integrated circuit capacitors have composite dielectric layers therein. These composite dielectric layers include crystallization inhibiting regions that operate to increase the overall crystallization temperature of the composite dielectric layer. An integrated circuit capacitor includes first and second capacitor electrodes and a capacitor dielectric layer extending between the first and second capacitor electrodes. The capacitor dielectric layer includes a composite of a first dielectric layer extending adjacent the first capacitor electrode, a second dielectric layer extending adjacent the second capacitor electrode and an electrically insulating crystallization inhibiting layer extending between the first and second dielectric layers. The electrically insulating crystallization inhibiting layer is formed of a material having a higher crystallization temperature characteristic relative to the first and second dielectric layers.
摘要翻译：集成电路电容器在其中具有复合电介质层。这些复合电介质层包括用于增加复合介电层的整体结晶温度的结晶抑制区。集成电路电容器包括第一和第二电容器电极和在第一和第二电容器电极之间延伸的电容器介电层。电容器介电层包括邻近第一电容器电极延伸的第一电介质层，邻近第二电容器电极延伸的第二电介质层和在第一和第二电介质层之间延伸的电绝缘的结晶抑制层的复合材料。电绝缘结晶抑制层由相对于第一和第二介电层具有较高结晶温度特性的材料形成。

40. 发明授权

US07824501B2 In-situ method of cleaning vaporizer during dielectric layer deposition process 有权
标题翻译：介电层沉积过程中清洗蒸发器的原位方法
公开(公告)号：US07824501B2
公开(公告)日：2010-11-02
申请号：US11781334
申请日：2007-07-23
申请人： Hoon-sang Choi , Jong-cheol Lee , Ki-vin Im , Eun-ae Chung , Sang-yeol Kang , Young-sun Kim , Kwang-hee Lee
发明人： Hoon-sang Choi , Jong-cheol Lee , Ki-vin Im , Eun-ae Chung , Sang-yeol Kang , Young-sun Kim , Kwang-hee Lee
IPC分类号： B08B9/08 , B08B3/08 , B08B3/10 , B08B5/00
CPC分类号： C23C16/45525 , C23C16/4401 , C23C16/45544
摘要： Provided is an in-situ method of cleaning a vaporizer of an atomic layer deposition apparatus during a dielectric layer deposition process, to prevent nozzle blocking in the vaporizer and an atomic layer deposition apparatus. During the dielectric layer deposition process, the following steps are repeated: supplying a first source gas for dielectric layer deposition into a chamber of an atomic layer deposition apparatus; purging the first source gas; supplying a second source gas into the chamber of the atomic layer deposition apparatus; purging the second source gas, the in-situ method of cleaning the vaporizer is performed after supplying the first source gas for dielectric layer deposition and before supplying the first source gas again.
摘要翻译：提供了一种在电介质层沉积工艺期间清洁原子层沉积设备的蒸发器的原位方法，以防止蒸发器和原子层沉积设备中的喷嘴堵塞。在电介质层沉积过程中，重复以下步骤：将用于电介质层沉积的第一源气体供应到原子层沉积设备的腔室中; 净化第一源气; 将第二源气体供应到原子层沉积设备的腔室中; 吹扫第二源气体时，在供给用于电介质层沉积的第一源气体并再次供应第一源气体之前执行清洗蒸发器的原位方法。

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