专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明授权

US08384425B2 Arrays of transistors with back control gates buried beneath the insulating film of a semiconductor-on-insulator substrate 有权
标题翻译：具有埋置在绝缘体上半导体衬底的绝缘膜下方的后控制栅极的晶体管阵列
公开(公告)号：US08384425B2
公开(公告)日：2013-02-26
申请号：US12961293
申请日：2010-12-06
申请人： Carlos Mazure , Richard Ferrant
发明人： Carlos Mazure , Richard Ferrant
IPC分类号： H03K19/173 , H03K3/01 , H01L27/12
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/11807
摘要： This invention provides a semiconductor device structure formed on a conventional semiconductor-on-insulator (SeOI) substrate and including an array of patterns, each pattern being formed by at least one field-effect transistor, each FET transistor having, in the thin film, a source region, a drain region, a channel region, and a front control gate region formed above the channel region. The provided device further includes at least one FET transistor having a pattern including a back control gate region formed in the base substrate beneath the channel region, the back gate region being capable of being biased in order to shift the threshold voltage of the transistor to simulate a modification in the channel width of the transistor or to force the transistor to remain off or on whatever the voltage applied on its front control gate. This invention also provides methods of operating such semiconductor device structures.
摘要翻译：本发明提供了一种半导体器件结构，其形成在传统的绝缘体上半导体（SeOI）衬底上并且包括一组图案，每个图案由至少一个场效应晶体管形成，每个FET晶体管在薄膜中，源极区域，漏极区域，沟道区域和形成在沟道区域上方的前部控制栅极区域。所提供的器件还包括至少一个FET晶体管，其具有包括形成在沟道区域下方的基底衬底中的反向控制栅极区域的图案，所述背栅极区域能够被偏置以便移位晶体管的阈值电压以模拟晶体管的沟道宽度的修改或迫使晶体管保持关断或者在其前控制栅上施加的任何电压。本发明还提供了操作这种半导体器件结构的方法。

32. 发明授权

US08304833B2 Memory cell with a channel buried beneath a dielectric layer 有权
标题翻译：具有埋在电介质层下方的通道的存储单元
公开(公告)号：US08304833B2
公开(公告)日：2012-11-06
申请号：US12974822
申请日：2010-12-21
申请人： Carlos Mazure , Richard Ferrant
发明人： Carlos Mazure , Richard Ferrant
IPC分类号： H04L27/12
CPC分类号： H01L29/7841 , H01L21/76264 , H01L21/84 , H01L27/0711 , H01L27/10802 , H01L27/1203 , H01L29/1037 , H01L29/1083 , H01L29/4236 , H01L29/66825 , H01L29/7302 , H01L29/7881
摘要： The invention provides various embodiments of a memory cell formed on a semiconductor-on-insulator (SeOI) substrate and comprising one or more FET transistors. Each FET transistor has a source region and a drain region at least portions of which are arranged in the thin layer of the SeOI substrate, a channel region in which a trench is made, and a gate region formed in the trench. Specifically, the source, drain and channel regions also have portions which are arranged also beneath the insulating layer of the SeOI substrate; the portion of channel region beneath the insulating layer extends between the portions of the source and drain regions also beneath the insulating layer; and the trench in the channel region extends into the depth of the base substrate beyond the insulating layer. Also, methods for fabricating such memory cells and memory arrays including a plurality of such memory cells.
摘要翻译：本发明提供了形成在绝缘体上半导体（SeOI）衬底上并且包括一个或多个FET晶体管的存储单元的各种实施例。每个FET晶体管具有源极区和漏极区，其至少部分布置在SeOI衬底的薄层中，其中形成沟槽的沟道区和形成在沟槽中的栅极区。具体地，源极，漏极和沟道区域还具有也被布置在SeOI衬底的绝缘层下方的部分; 绝缘层下方的沟道区域的部分在绝缘层下方的源极和漏极区的部分之间延伸; 并且沟道区域中的沟槽延伸到基底衬底的深度超过绝缘层。而且，制造这种存储单元的方法和包括多个这样的存储单元的存储器阵列。

33. 发明申请

US20110134698A1 FLASH MEMORY CELL ON SeOI HAVING A SECOND CONTROL GATE BURIED UNDER THE INSULATING LAYER 有权
标题翻译：在绝缘层下面有第二个控制栅的闪存存储器
公开(公告)号：US20110134698A1
公开(公告)日：2011-06-09
申请号：US12946135
申请日：2010-11-15
申请人： Carlos Mazure , Richard Ferrant
发明人： Carlos Mazure , Richard Ferrant
IPC分类号： G11C16/04 , H01L29/772 , H01L21/336
CPC分类号： H01L29/7881 , H01L21/28273 , H01L27/11521 , H01L29/42328 , H01L29/42336
摘要： The invention relates to a flash memory cell having a FET transistor with a floating gate on a semiconductor-on-insulator (SOI) substrate composed of a thin film of semiconductor material separated from a base substrate by an insulating buried oxide (BOX) layer, The transistor has in the thin film, a channel, with two control gates, a front control gate located above the floating gate and separated from it by an inter-gate dielectric, and a back control gate located within the base substrate directly under the insulating (BOX) layer and separated from the channel by only the insulating (BOX) layer. The two control gates are designed to be used in combination to perform a cell programming operation. The invention also relates to a memory array made up of a plurality of memory cells according to the first aspect of the invention, which can be in an array of rows and columns, and a method of fabricating such memory cells and memory arrays.
摘要翻译：本发明涉及一种闪存单元，其具有在绝缘体上绝缘体（SOI）衬底上具有浮置栅极的FET晶体管，该半导体材料由通过绝缘掩埋氧化物（BOX）层从基底衬底分离的半导体材料薄膜构成，晶体管在薄膜中具有通道，具有两个控制栅极，位于浮置栅极上方的前控制栅极，并通过栅极间电介质与栅极间绝缘体分离，以及位于绝缘子下方的基底衬底内的反控制栅极（BOX）层，并且仅通过绝缘（BOX）层与沟道分离。两个控制门被设计成组合使用以执行单元编程操作。本发明还涉及由根据本发明的第一方面的多个存储单元组成的存储器阵列，其可以是行和列的阵列，以及制造这种存储单元和存储器阵列的方法。

34. 发明申请

US20110134690A1 METHOD OF CONTROLLING A DRAM MEMORY CELL ON THE SeOI HAVING A SECOND CONTROL GATE BURIED UNDER THE INSULATING LAYER 审中-公开
标题翻译：控制在具有绝缘层的第二控制栅的SeOi上的DRAM存储单元的方法
公开(公告)号：US20110134690A1
公开(公告)日：2011-06-09
申请号：US12898230
申请日：2010-10-05
申请人： Carlos Mazure , Richard Ferrant
发明人： Carlos Mazure , Richard Ferrant
IPC分类号： G11C11/34 , H01L29/772 , H01L21/336
CPC分类号： G11C11/404 , G11C2211/4016 , H01L27/10802 , H01L27/1203 , H01L29/42356 , H01L29/7841
摘要： The invention relates to a method of controlling a DRAM memory cell of an FET transistor on a semiconductor-on-insulator substrate that includes a thin film of semiconductor material separated from a base substrate by an insulating layer or BOX layer, the transistor having a channel and two control gates, a front control gate being arranged on top of the channel and separated from the latter by a gate dielectric and a back control gate being arranged in the base substrate and separated from the channel by the insulating layer (BOX). In a cell programming operation, the front control gate and the back control gate are operated jointly by applying a first voltage to the front control gate and a second voltage to the back control gate, with the first voltage being lower in amplitude than the voltage needed to program the cell when no voltage is applied to the back control gate.
摘要翻译：本发明涉及一种控制绝缘体上半导体衬底上的FET晶体管的DRAM存储单元的方法，该方法包括通过绝缘层或BOX层从基底衬底分离的半导体材料的薄膜，晶体管具有通道和两个控制栅极，前控制栅极布置在通道的顶部并且由栅介质和背控制栅极分隔开，栅极电介质和背控制栅极被布置在基底衬底中并且通过绝缘层（BOX）与通道分离。在单元编程操作中，前控制栅极和后控制栅极通过向前控制栅极施加第一电压和向后控制栅极施加第二电压来共同操作，第一电压的幅度低于所需的电压当没有电压施加到后控制门时对单元进行编程。

35. 发明授权

US08310866B2 MRAM device structure employing thermally-assisted write operations and thermally-unassisted self-referencing operations 有权
标题翻译：采用热辅助写入操作和热辅助自参考操作的MRAM器件结构
公开(公告)号：US08310866B2
公开(公告)日：2012-11-13
申请号：US12168671
申请日：2008-07-07
申请人： Rainer Leuschner , Ulrich Klostermann , Richard Ferrant
发明人： Rainer Leuschner , Ulrich Klostermann , Richard Ferrant
IPC分类号： G11C11/02 , G11C7/00 , H01L21/00
CPC分类号： G11C7/04 , B82Y25/00 , B82Y40/00 , G11C11/16 , G11C11/1675 , H01F10/3254 , H01F10/3272 , H01F41/307 , H01L27/228 , H01L43/08 , H01L43/12
摘要： A thermally-assisted MRAM structure which is programmable at a writing mode operating temperature is presented and includes an anti-ferromagnet, an artificial anti-ferromagnet, a barrier layer, and a free magnetic layer. The anti-ferromagnet is composed of a material having a blocking temperature Tb which is lower than the writing mode operating temperature of the magnetic random access memory structure. The artificial anti-ferromagnet is magnetically coupled to the anti-ferromagnet, and includes first and second magnetic layers, and a coupling layer interposed therebetween, the first and second magnetic layers having different Curie point temperatures. The barrier layer is positioned to be between the second magnetic layer and the free magnetic layer.
摘要翻译：提出了一种在写入模式工作温度下可编程的热辅助MRAM结构，其包括反铁磁体，人造抗铁磁体，阻挡层和自由磁性层。抗铁磁体由具有比磁性随机存取存储器结构的写入模式工作温度低的阻挡温度Tb的材料构成。人造抗铁磁体磁耦合到抗铁磁体，并且包括第一和第二磁性层以及插入其间的耦合层，第一和第二磁性层具有不同的居里点温度。阻挡层被定位在第二磁性层和自由磁性层之间。

36. 发明授权

US07994560B2 Integrated circuit comprising a transistor and a capacitor, and fabrication method 有权
标题翻译：包括晶体管和电容器的集成电路及其制造方法
公开(公告)号：US07994560B2
公开(公告)日：2011-08-09
申请号：US12173702
申请日：2008-07-15
申请人： Christian Caillat , Richard Ferrant
发明人： Christian Caillat , Richard Ferrant
IPC分类号： H01L29/94
CPC分类号： H01L27/10823 , H01L27/0218 , H01L27/10829 , H01L27/10876 , H01L27/10885 , H01L27/1203
摘要： An integrated circuit includes a substrate and at least one active region. A transistor produced in the active region separated from the substrate. This transistor includes a source or drain first region and a drain or source second region which are connected by a channel. A gate structure is position on top of said channel and operates to control the channel. The gate structure is formed in a trench whose sidewalls have a shape which converges (narrows) in the width dimension towards the substrate. A capacitor is also formed having a first electrode, a second electrode and a dielectric layer between the electrodes. This capacitor is also formed in a trench. An electrode line is connected to the first electrode of the capacitor. The second electrode of the capacitor is formed in a layer shared in common with at least part of the drain or source second region of the transistor. A bit line is located beneath the gate structure. The integrated circuit may, for example, be a DRAM memory cell.
摘要翻译：集成电路包括衬底和至少一个有源区。在与基板分离的有源区中产生的晶体管。该晶体管包括源极或漏极第一区域以及通过沟道连接的漏极或源极第二区域。栅极结构位于所述通道的顶部并且用于控制通道。栅极结构形成在其侧壁具有朝向衬底的宽度尺寸收敛（窄））的形状的沟槽中。电容器也形成为具有在电极之间的第一电极，第二电极和电介质层。该电容器也形成在沟槽中。电极线连接到电容器的第一电极。电容器的第二电极形成在与晶体管的漏极或源极第二区域的至少一部分共同共享的层中。位线位于门结构下方。集成电路例如可以是DRAM存储单元。

37. 发明授权

US06995997B2 Cache cell with masking 有权
标题翻译：具有掩蔽的缓存单元
公开(公告)号：US06995997B2
公开(公告)日：2006-02-07
申请号：US10862057
申请日：2004-06-04
申请人： Richard Ferrant
发明人： Richard Ferrant
IPC分类号： G11C15/00
CPC分类号： G11C15/04
摘要： A CAM cell with masking made in the form of an integrated circuit, including a first storage cell including a first transistor, first and second inverters in anti-parallel, and a second transistor; a comparison cell, including third and fourth transistors controlling a fifth transistor, connected in series with a sixth inhibiting transistor to a result line; and a second storage cell, including a seventh transistor in series with two inverters in anti-parallel and an eighth transistor, the second storage cell controlling the inhibiting transistor. The first, second, seventh, and eighth transistors may be N-channel transistors, and the third, fourth, fifth, and sixth transistors may be P-channel transistors.
摘要翻译：具有以集成电路形式形成的掩蔽的CAM单元，包括：第一存储单元，包括第一晶体管，反并联的第一和第二反相器以及第二晶体管; 比较单元，包括控制第五晶体管的第三和第四晶体管，与第六抑制晶体管串联连接到结果行; 以及第二存储单元，其包括与反并联的两个反相器串联的第七晶体管和第八晶体管，所述第二存储单元控制所述抑制晶体管。第一，第二，第七和第八晶体管可以是N沟道晶体管，并且第三，第四，第五和第六晶体管可以是P沟道晶体管。

38. 发明申请

US20050174873A1 Semiconductor memory device and method of operating same 有权
公开(公告)号：US20050174873A1
公开(公告)日：2005-08-11
申请号：US11096970
申请日：2005-04-01
申请人： Richard Ferrant , Serguei Okhonin , Eric Carman , Michel Bron
发明人： Richard Ferrant , Serguei Okhonin , Eric Carman , Michel Bron
IPC分类号： G11C20060101 , G11C8/00 , G11C11/00 , G11C11/404 , G11C11/406 , G11C11/4097
CPC分类号： G11C11/404 , G11C7/18 , G11C8/08 , G11C11/406 , G11C11/40618 , G11C11/4097 , G11C2211/4016 , G11C2211/4065 , H01L21/84 , H01L27/10802 , H01L27/10844 , H01L27/1203 , H01L29/7841
摘要： There are many inventions described and illustrated herein. In a first aspect, the present invention is directed to a memory device and technique of reading data from and writing data into memory cells of the memory device. In this regard, in one embodiment of this aspect of the invention, the memory device and technique for operating that device that minimizes, reduces and/or eliminates the debilitating affects of the charge pumping phenomenon. This embodiment of the present invention employs control signals that minimize, reduce and/or eliminate transitions of the amplitudes and/or polarities. In another embodiment, the present invention is a semiconductor memory device including a memory array comprising a plurality of semiconductor dynamic random access memory cells arranged in a matrix of rows and columns. Each semiconductor dynamic random access memory cell includes a transistor having a source region, a drain region, a electrically floating body region disposed between and adjacent to the source region and the drain region, and a gate spaced apart from, and capacitively coupled to, the body region. Each transistor includes a first state representative of a first charge in the body region, and a second data state representative of a second charge in the body region. Further, each row of semiconductor dynamic random access memory cells includes an associated source line which is connected to only the semiconductor dynamic random access memory cells of the associated row.

39. 发明申请

US20050157534A1 DRAM refreshment 有权
标题翻译： DRAM刷新
公开(公告)号：US20050157534A1
公开(公告)日：2005-07-21
申请号：US10627955
申请日：2003-07-25
申请人： Richard Ferrant , Francois Jacquet
发明人： Richard Ferrant , Francois Jacquet
IPC分类号： G11C11/406 , G11C11/24
CPC分类号： G11C11/406
摘要： A DRAM including an array of storage elements arranged in lines and columns, and for each column: write means adapted to biasing at least a selected one of the elements to a charge level chosen from among a first predetermined high level and a second predetermined low level, combined with read circuitry adapted to determining whether the stored charge level is greater or smaller than a predetermined charge level; and isolation circuitry adapted to isolating the array from the read and/or write means, each column further including refreshment means, distinct from the read and write circuit, for increasing, beyond the first and second predetermined levels, the charge stored in a storage element.
摘要翻译：一种DRAM，包括排列成行和列的存储元件的阵列，并且用于每列：写入装置，其适于将至少一个所选元素偏置到从第一预定高电平和第二预定低电平中选择的电荷电平与读取电路组合，适于确定所存储的电荷电平是否大于或小于预定电荷电平; 以及隔离电路，其适于将阵列与读取和/或写入装置隔离，每列还包括与读取和写入电路不同的刷新装置，用于在第一和第二预定级别之外增加存储在存储元件中的电荷。

40. 发明授权

US06920075B2 Amplifier for reading storage cells with exclusive-OR type function 有权
标题翻译：用于读取具有异或类型功能的存储单元的放大器
公开(公告)号：US06920075B2
公开(公告)日：2005-07-19
申请号：US10450803
申请日：2001-12-14
申请人： Richard Ferrant
发明人： Richard Ferrant
IPC分类号： G11C7/06 , G11C7/10 , G11C11/4091 , G11C7/00
CPC分类号： G11C11/4091 , G11C7/062 , G11C7/1006
摘要： The invention concerns an amplifier (1), capable of being controlled by an activation signal, for reading storage cells of a crossbar network comprising, for each column, a direct bit line (BLdi) and a reference bit line (BLri), the amplifier being common to two columns and producing an OR-Exclusive type combination of the states of the cells read in said two columns.
摘要翻译：本发明涉及一种能够被激活信号控制的放大器（1），用于读取交叉开关网络的存储单元，其包括针对每列的直接位线（BLdi）和参考位线（BLri），放大器对于两列是共同的，并且产生在所述两列中读取的单元的状态的OR-Exclusive类型组合。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式