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31. 发明授权

US07056782B2 CMOS silicide metal gate integration 失效
公开(公告)号：US07056782B2
公开(公告)日：2006-06-06
申请号：US10786901
申请日：2004-02-25
申请人： Ricky S. Amos , Diane C. Boyd , Cyril Cabral, Jr. , Richard D. Kaplan , Jakub T. Kedzierski , Victor Ku , Woo-Hyeong Lee , Ying Li , Anda C. Mocuta , Vijay Narayanan , An L. Steegen , Maheswaran Surendra
发明人： Ricky S. Amos , Diane C. Boyd , Cyril Cabral, Jr. , Richard D. Kaplan , Jakub T. Kedzierski , Victor Ku , Woo-Hyeong Lee , Ying Li , Anda C. Mocuta , Vijay Narayanan , An L. Steegen , Maheswaran Surendra
IPC分类号： H01L21/8238
CPC分类号： H01L21/76897 , H01L21/28052 , H01L21/28097 , H01L21/823835 , H01L29/66545 , H01L29/6656
摘要： The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present invention has the same silicide metal phase and substantially the same height, regardless of the dimension of the silicide metal gate. The present invention also provides various methods of forming a CMOS structure having silicided contacts in which the polySi gate heights are substantially the same across the entire surface of a semiconductor structure.

32. 发明授权

US06846734B2 Method and process to make multiple-threshold metal gates CMOS technology 有权
标题翻译：制造多阈值金属门CMOS技术的方法与工艺
公开(公告)号：US06846734B2
公开(公告)日：2005-01-25
申请号：US10300165
申请日：2002-11-20
申请人： Ricky Amos , Katayun Barmak , Diane C. Boyd , Cyril Cabral, Jr. , Meikei Leong , Thomas S. Kanarsky , Jakub Tadeusz Kedzierski
发明人： Ricky Amos , Katayun Barmak , Diane C. Boyd , Cyril Cabral, Jr. , Meikei Leong , Thomas S. Kanarsky , Jakub Tadeusz Kedzierski
IPC分类号： H01L27/092 , H01L21/28 , H01L21/336 , H01L21/8238 , H01L21/84 , H01L21/3205 , H01L21/44 , H01L21/4763
CPC分类号： H01L21/823835 , H01L21/28097 , H01L21/823842 , H01L21/84 , H01L29/66545
摘要： Methods of forming complementary metal oxide semiconductor (CMOS) devices having multiple-threshold voltages which are easily tunable are provided. Total salicidation with a metal bilayer (representative of the first method of the present invention) or metal alloy (representative of the second method of the present invention) is provided. CMOS devices having multiple-threshold voltages provided by the present methods are also described.
摘要翻译：提供了形成具有易于调节的多阈值电压的互补金属氧化物半导体（CMOS）器件的方法。提供了用金属双层（代表本发明的第一种方法）或金属合金（代表本发明的第二种方法）的总的水杨酸化。还描述了通过本方法提供的具有多阈值电压的CMOS器件。

33. 发明授权

US06593617B1 Field effect transistors with vertical gate side walls and method for making such transistors 失效
标题翻译：具有垂直栅极侧壁的场效应晶体管和用于制造这种晶体管的方法
公开(公告)号：US06593617B1
公开(公告)日：2003-07-15
申请号：US09026093
申请日：1998-02-19
申请人： Diane C. Boyd , Stuart M. Burns , Hussein I. Hanafi , Yuan Taur , William C. Wille
发明人： Diane C. Boyd , Stuart M. Burns , Hussein I. Hanafi , Yuan Taur , William C. Wille
IPC分类号： H01L2976
CPC分类号： H01L29/66583
摘要： Metal oxide semiconductor field effect transistor (MOSFET) comprising a drain region and source region which enclose a channel region. A thin gate oxide is situated on the channel region and a gate conductor with vertical side walls is located on this gate oxide. The interfaces between the source region and channel region and the drain region and channel region are abrupt. Such an FET can be made using the following method: forming a dielectric stack on a semiconductor structure which at least comprises a pad oxide layer; defining an etch window having the lateral size and shape of a gate pillar to be formed; defining a gate hole in the dielectric stack by transferring the etch window into the dielectric stack using a reactive ion etching (RIE) process; depositing a gate conductor such that it fills the gate hole; removing the gate conductor covering the portions of the dielectric stack surrounding the gate hole; removing at least part of the dielectric stack such that a gate pillar with vertical side walls is set free.
摘要翻译：金属氧化物半导体场效应晶体管（MOSFET）包括漏极区域和封装沟道区域的源极区域。栅极氧化物位于通道区域上，并且具有垂直侧壁的栅极导体位于该栅极氧化物上。源极区域和沟道区域以及漏极区域和沟道区域之间的界面是突然的。可以使用以下方法制造FET：在至少包括衬垫氧化物层的半导体结构上形成电介质堆叠;限定蚀刻窗口，其具有要形成的门柱的横向尺寸和形状;通过使用反应离子蚀刻（RIE）工艺将蚀刻窗口转移到电介质堆叠中来在电介质堆叠中限定栅极孔;沉积栅极导体，使得其填充栅极孔;去除覆盖围绕栅极孔的电介质堆叠的部分的栅极导体;去除至少部分介电堆叠，使得具有垂直侧壁的门柱被释放。

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