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1. 发明授权

US06846734B2 Method and process to make multiple-threshold metal gates CMOS technology 有权
标题翻译：制造多阈值金属门CMOS技术的方法与工艺
公开(公告)号：US06846734B2
公开(公告)日：2005-01-25
申请号：US10300165
申请日：2002-11-20
申请人： Ricky Amos , Katayun Barmak , Diane C. Boyd , Cyril Cabral, Jr. , Meikei Leong , Thomas S. Kanarsky , Jakub Tadeusz Kedzierski
发明人： Ricky Amos , Katayun Barmak , Diane C. Boyd , Cyril Cabral, Jr. , Meikei Leong , Thomas S. Kanarsky , Jakub Tadeusz Kedzierski
IPC分类号： H01L27/092 , H01L21/28 , H01L21/336 , H01L21/8238 , H01L21/84 , H01L21/3205 , H01L21/44 , H01L21/4763
CPC分类号： H01L21/823835 , H01L21/28097 , H01L21/823842 , H01L21/84 , H01L29/66545
摘要： Methods of forming complementary metal oxide semiconductor (CMOS) devices having multiple-threshold voltages which are easily tunable are provided. Total salicidation with a metal bilayer (representative of the first method of the present invention) or metal alloy (representative of the second method of the present invention) is provided. CMOS devices having multiple-threshold voltages provided by the present methods are also described.
摘要翻译：提供了形成具有易于调节的多阈值电压的互补金属氧化物半导体（CMOS）器件的方法。提供了用金属双层（代表本发明的第一种方法）或金属合金（代表本发明的第二种方法）的总的水杨酸化。还描述了通过本方法提供的具有多阈值电压的CMOS器件。

2. 发明授权

US07250658B2 Hybrid planar and FinFET CMOS devices 有权
标题翻译：混合平面和FinFET CMOS器件
公开(公告)号：US07250658B2
公开(公告)日：2007-07-31
申请号：US11122193
申请日：2005-05-04
申请人： Bruce B. Doris , Diane C. Boyd , Meikei Leong , Thomas S. Kanarsky , Jakub T. Kedzierski , Min Yang
发明人： Bruce B. Doris , Diane C. Boyd , Meikei Leong , Thomas S. Kanarsky , Jakub T. Kedzierski , Min Yang
IPC分类号： H01L29/772
CPC分类号： H01L27/1211 , H01L21/845 , H01L29/66795 , H01L29/785
摘要： The present invention provides an integrated semiconductor circuit containing a planar single gated FET and a FinFET located on the same SOI substrate. Specifically, the integrated semiconductor circuit includes a FinFET and a planar single gated FET located atop a buried insulating layer of an silicon-on-insulator substrate, the planar single gated FET is located on a surface of a patterned top semiconductor layer of the silicon-on-insulator substrate and the FinFET has a vertical channel that is perpendicular to the planar single gated FET. A method of forming a method such an integrated circuit is also provided. In the method, resist imaging and a patterned hard mask are used in trimming the width of the FinFET active device region and subsequent resist imaging and etching are used in thinning the thickness of the FET device area. The trimmed active FinFET device region is formed such that it lies perpendicular to the thinned planar single gated FET device region.
摘要翻译：本发明提供一种集成半导体电路，其包含位于同一SOI衬底上的平面单栅极FET和FinFET。具体地，集成半导体电路包括FinFET和位于绝缘体上硅衬底的掩埋绝缘层顶上的平面单栅极FET，平面单门控FET位于硅 - 硅绝缘体的图案化顶部半导体层的表面上，绝缘体上的衬底和FinFET具有垂直于平面单门控FET的垂直沟道。还提供了一种形成集成电路的方法。在该方法中，抗蚀剂成像和图案化的硬掩模用于修整FinFET有源器件区域的宽度，并且随后的抗蚀剂成像和蚀刻用于减薄FET器件区域的厚度。经修整的有源FinFET器件区域形成为垂直于薄化的平面单栅极FET器件区域。

3. 发明授权

US07314789B2 Structure and method to generate local mechanical gate stress for MOSFET channel mobility modification 有权
标题翻译：用于产生MOSFET通道迁移率修正的局部机械栅极应力的结构和方法
公开(公告)号：US07314789B2
公开(公告)日：2008-01-01
申请号：US11618751
申请日：2006-12-30
申请人： Cyril Cabral, Jr. , Bruce B. Doris , Thomas S. Kanarsky , Xiao H. Liu , Huilong Zhu
发明人： Cyril Cabral, Jr. , Bruce B. Doris , Thomas S. Kanarsky , Xiao H. Liu , Huilong Zhu
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/84 , H01L21/04
CPC分类号： H01L29/7845 , H01L21/3215 , H01L21/823807 , H01L21/823835 , H01L21/823842 , H01L29/4966 , H01L29/517 , H01L29/665
摘要： A semiconductor structure and method that is capable of generating a local mechanical gate stress for channel mobility modification are provided. The semiconductor structure includes at least one NFET and at least one PFET on a surface of a semiconductor substrate. The at least one NFET has a gate stack structure comprising a gate dielectric, a first gate electrode layer, a barrier layer, a Si-containing second gate electrode layer and a compressive metal, and the at least one PFET has a gate stack structure comprising a gate dielectric, a first gate electrode layer, a barrier layer and a tensile metal or a silicide.
摘要翻译：提供了能够产生用于信道迁移率修改的局部机械栅极应力的半导体结构和方法。半导体结构在半导体衬底的表面上包括至少一个NFET和至少一个PFET。所述至少一个NFET具有包括栅极电介质，第一栅极电极层，阻挡层，含Si的第二栅极电极层和压缩金属的栅极堆叠结构，并且所述至少一个PFET具有包括栅极电介质，第一栅电极层，阻挡层和拉伸金属或硅化物。

4. 发明授权

US07173312B2 Structure and method to generate local mechanical gate stress for MOSFET channel mobility modification 失效
标题翻译：用于产生MOSFET通道迁移率修正的局部机械栅极应力的结构和方法
公开(公告)号：US07173312B2
公开(公告)日：2007-02-06
申请号：US10905101
申请日：2004-12-15
申请人： Cyril Cabral, Jr. , Bruce B. Doris , Thomas S. Kanarsky , Xiao H. Liu , Huilong Zhu
发明人： Cyril Cabral, Jr. , Bruce B. Doris , Thomas S. Kanarsky , Xiao H. Liu , Huilong Zhu
IPC分类号： H01L29/76
CPC分类号： H01L29/7845 , H01L21/3215 , H01L21/823807 , H01L21/823835 , H01L21/823842 , H01L29/4966 , H01L29/517 , H01L29/665
摘要： A semiconductor structure and method that is capable of generating a local mechanical gate stress for channel mobility modification are provided. The semiconductor structure includes at least one NFET and at least one PFET on a surface of a semiconductor substrate. The at least one NFET has a gate stack structure comprising a gate dielectric, a first gate electrode layer, a barrier layer, a Si-containing second gate electrode layer and a compressive metal, and the at least one PFET has a gate stack structure comprising a gate dielectric, a first gate electrode layer, a barrier layer and a tensile metal or a silicide.
摘要翻译：提供了能够产生用于信道迁移率修改的局部机械栅极应力的半导体结构和方法。半导体结构在半导体衬底的表面上包括至少一个NFET和至少一个PFET。所述至少一个NFET具有包括栅极电介质，第一栅极电极层，阻挡层，含Si的第二栅极电极层和压缩金属的栅极堆叠结构，并且所述至少一个PFET具有包括栅极电介质，第一栅电极层，阻挡层和拉伸金属或硅化物。

5. 发明授权

US06911383B2 Hybrid planar and finFET CMOS devices 失效
标题翻译：混合平面和finFET CMOS器件
公开(公告)号：US06911383B2
公开(公告)日：2005-06-28
申请号：US10604097
申请日：2003-06-26
申请人： Bruce B. Doris , Diane C. Boyd , Meikei Ieong , Thomas S. Kanarsky , Jakub T. Kedzierski , Min Yang
发明人： Bruce B. Doris , Diane C. Boyd , Meikei Ieong , Thomas S. Kanarsky , Jakub T. Kedzierski , Min Yang
IPC分类号： H01L29/423 , H01L21/336 , H01L21/8234 , H01L21/84 , H01L27/08 , H01L27/088 , H01L27/12 , H01L29/49 , H01L29/786 , H01L21/3205
CPC分类号： H01L27/1211 , H01L21/845 , H01L29/66795 , H01L29/785
摘要： The present invention provides an integrated semiconductor circuit containing a planar single gated FET and a FinFET located on the same SOI substrate. Specifically, the integrated semiconductor circuit includes a FinFET and a planar single gated FET located atop a buried insulating layer of an silicon-on-insulator substrate, the planar single gated FET is located on a surface of a patterned top semiconductor layer of the silicon-on-insulator substrate and the FinFET has a vertical channel that is perpendicular to the planar single gated FET. A method of forming a method such an integrated circuit is also provided. In the method, resist imaging and a patterned hard mask are used in trimming the width of the FinFET active device region and subsequent resist imaging and etching are used in thinning the thickness of the FET device area. The trimmed active FinFET device region is formed such that it lies perpendicular to the thinned planar single gated FET device region.
摘要翻译：本发明提供一种集成半导体电路，其包含位于同一SOI衬底上的平面单栅极FET和FinFET。具体地，集成半导体电路包括FinFET和位于绝缘体上硅衬底的掩埋绝缘层顶上的平面单栅极FET，平面单门控FET位于硅 - 硅绝缘体的图案化顶部半导体层的表面上，绝缘体上的衬底和FinFET具有垂直于平面单门控FET的垂直沟道。还提供了一种形成集成电路的方法。在该方法中，抗蚀剂成像和图案化的硬掩模用于修整FinFET有源器件区域的宽度，并且随后的抗蚀剂成像和蚀刻用于减薄FET器件区域的厚度。经修整的有源FinFET器件区域形成为垂直于薄化的平面单栅极FET器件区域。

6. 发明授权

US07968915B2 Dual stress memorization technique for CMOS application 有权
标题翻译： CMOS应用的双重应力记忆技术
公开(公告)号：US07968915B2
公开(公告)日：2011-06-28
申请号：US12538110
申请日：2009-08-08
申请人： Thomas S. Kanarsky , Qiqing Ouyang , Haizhou Yin
发明人： Thomas S. Kanarsky , Qiqing Ouyang , Haizhou Yin
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823412 , H01L21/823468 , H01L21/823864 , H01L29/7843 , H01L29/7847
摘要： A stress-transmitting dielectric layer is formed on the at least one PFET and the at least one NFET. A tensile stress generating film, such as a silicon nitride, is formed on the at least one NFET by blanket deposition and patterning. A compressive stress generating film, which may be a refractive metal nitride film, is formed on the at least one PFET by a blanket deposition and patterning. An encapsulating dielectric film is deposited over the compress stress generating film. The stress is transferred from both the tensile stress generating film and the compressive stress generating film into the underlying semiconductor structures. The magnitude of the transferred compressive stress from the refractory metal nitride film may be from about 5 GPa to about 20 GPa. The stress is memorized during an anneal and remains in the semiconductor devices after the stress generating films are removed.
摘要翻译：在至少一个PFET和至少一个NFET上形成应力传导电介质层。通过毯式沉积和图案化在至少一个NFET上形成拉伸应力产生膜，例如氮化硅。可以通过覆盖沉积和图案化在至少一个PFET上形成可以是折射金属氮化物膜的压应力产生膜。在压缩应力产生膜上沉积密封电介质膜。应力从拉伸应力产生膜和压缩应力产生膜转移到下面的半导体结构中。来自难熔金属氮化物膜的转移的压缩应力的大小可以为约5GPa至约20GPa。应力在退火期间被记忆，并且在除去应力产生膜之后保留在半导体器件中。

7. 发明申请

US20080303101A1 DUAL STRESS MEMORIZATION TECHNIQUE FOR CMOS APPLICATION 有权
标题翻译： CMOS应用的双应力记忆技术
公开(公告)号：US20080303101A1
公开(公告)日：2008-12-11
申请号：US11758291
申请日：2007-06-05
申请人： Thomas S. Kanarsky , Qiqing Ouyang , Haizhou Yin
发明人： Thomas S. Kanarsky , Qiqing Ouyang , Haizhou Yin
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823412 , H01L21/823468 , H01L21/823864 , H01L29/7843 , H01L29/7847
摘要： A stress-transmitting dielectric layer is formed on the at least one PFET and the at least one NFET. A tensile stress generating film, such as a silicon nitride, is formed on the at least one NFET by blanket deposition and patterning. A compressive stress generating film, which may be a refractive metal nitride film, is formed on the at least one PFET by a blanket deposition and patterning. An encapsulating dielectric film is deposited over the compress stress generating film. The stress is transferred from both the tensile stress generating film and the compressive stress generating film into the underlying semiconductor structures. The magnitude of the transferred compressive stress from the refractory metal nitride film may be from about 5 GPa to about 20 GPa. The stress is memorized during an anneal and remains in the semiconductor devices after the stress generating films are removed,
摘要翻译：在至少一个PFET和至少一个NFET上形成应力传导电介质层。通过毯式沉积和图案化在至少一个NFET上形成拉伸应力产生膜，例如氮化硅。可以通过覆盖沉积和图案化在至少一个PFET上形成可以是折射金属氮化物膜的压应力产生膜。在压缩应力产生膜上沉积密封电介质膜。应力从拉伸应力产生膜和压缩应力产生膜转移到下面的半导体结构中。来自难熔金属氮化物膜的转移的压缩应力的大小可以为约5GPa至约20GPa。应力在退火期间被记忆，并且在除去应力产生膜之后保留在半导体器件中，

8. 发明授权

US06905941B2 Structure and method to fabricate ultra-thin Si channel devices 失效
标题翻译：制造超薄Si通道器件的结构和方法
公开(公告)号：US06905941B2
公开(公告)日：2005-06-14
申请号：US10250069
申请日：2003-06-02
申请人： Bruce B. Doris , Thomas S. Kanarsky , Meikei Ieong , Wesley C. Natzle
发明人： Bruce B. Doris , Thomas S. Kanarsky , Meikei Ieong , Wesley C. Natzle
IPC分类号： H01L21/762 , H01L21/84 , H01L21/76
CPC分类号： H01L21/84 , H01L21/76283
摘要： A method for preventing polysilicon stringer formation under the active device area of an isolated ultra-thin Si channel device is provided. The method utilizes a chemical oxide removal (COR) processing step to prevent stinger formation, instead of a conventional wet etch process wherein a chemical etchant such as HF is employed. A silicon-on-insulator (SOI) structure is also provided. The structure includes at least a top Si-containing layer located on a buried insulating layer; and an oxide filled trench isolation region located in the top Si-containing layer and a portion of the buried insulating layer. No undercut regions are located beneath the top Si-containing layer.
摘要翻译：提供了一种用于防止在隔离的超薄Si沟道器件的有源器件区域下形成多晶硅的方法。该方法使用化学氧化物去除（COR）处理步骤来防止托管架形成，而不是采用诸如HF的化学蚀刻剂的常规湿法蚀刻工艺。还提供了绝缘体上硅（SOI）结构。该结构包括至少位于掩埋绝缘层上的顶部含Si层; 以及位于顶部含Si层和掩埋绝缘层的一部分中的氧化物填充沟槽隔离区。顶部含Si层下方没有底切区域。

9. 发明授权

US06677646B2 Method and structure of a disposable reversed spacer process for high performance recessed channel CMOS 有权
标题翻译：用于高性能凹槽通道CMOS的一次性反向间隔器工艺的方法和结构
公开(公告)号：US06677646B2
公开(公告)日：2004-01-13
申请号：US10117959
申请日：2002-04-05
申请人： Meikei Ieong , Omer H. Dokumaci , Thomas S. Kanarsky , Victor Ku
发明人： Meikei Ieong , Omer H. Dokumaci , Thomas S. Kanarsky , Victor Ku
IPC分类号： H01L2701
CPC分类号： H01L29/78696 , H01L29/456 , H01L29/4908 , H01L29/66545 , H01L29/66772 , H01L29/78618 , H01L29/78621
摘要： A high-performance recessed channel CMOS device including an SOI layer having a recessed channel region and adjoining extension implant regions and optional halo implant regions; and at least one gate region present atop the SOI layer and a method for fabricating the same are provided. The adjoining extension and optional halo implant regions have an abrupt lateral profile and are located beneath said gate region.
摘要翻译：一种高性能凹陷沟道CMOS器件，包括具有凹陷沟道区域和相邻的延伸注入区域和可选的晕轮植入区域的SOI层; 并且提供存在于SOI层顶上的至少一个栅极区域及其制造方法。邻接的延伸部分和可选的晕轮植入区域具有突然的侧向轮廓并且位于所述栅极区域下方。

10. 发明授权

US07834399B2 Dual stress memorization technique for CMOS application 有权
标题翻译： CMOS应用的双重应力记忆技术
公开(公告)号：US07834399B2
公开(公告)日：2010-11-16
申请号：US11758291
申请日：2007-06-05
申请人： Thomas S. Kanarsky , Qiqing Ouyang , Haizhou Yin
发明人： Thomas S. Kanarsky , Qiqing Ouyang , Haizhou Yin
IPC分类号： H01L29/76
CPC分类号： H01L21/823807 , H01L21/823412 , H01L21/823468 , H01L21/823864 , H01L29/7843 , H01L29/7847
摘要： A stress-transmitting dielectric layer is formed on the at least one PFET and the at least one NFET. A tensile stress generating film, such as a silicon nitride, is formed on the at least one NFET by blanket deposition and patterning. A compressive stress generating film, which may be a refractive metal nitride film, is formed on the at least one PFET by a blanket deposition and patterning. An encapsulating dielectric film is deposited over the compress stress generating film. The stress is transferred from both the tensile stress generating film and the compressive stress generating film into the underlying semiconductor structures. The magnitude of the transferred compressive stress from the refractory metal nitride film may be from about 5 GPa to about 20 GPa. The stress is memorized during an anneal and remains in the semiconductor devices after the stress generating films are removed.
摘要翻译：在至少一个PFET和至少一个NFET上形成应力传导电介质层。通过毯式沉积和图案化在至少一个NFET上形成拉伸应力产生膜，例如氮化硅。可以通过覆盖沉积和图案化在至少一个PFET上形成可以是折射金属氮化物膜的压应力产生膜。在压缩应力产生膜上沉积密封电介质膜。应力从拉伸应力产生膜和压缩应力产生膜转移到下面的半导体结构中。来自难熔金属氮化物膜的转移的压缩应力的大小可以为约5GPa至约20GPa。应力在退火期间被记忆，并且在除去应力产生膜之后保留在半导体器件中。

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