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31. 发明授权

US07318127B2 Method, apparatus, and computer program product for sharing data in a cache among threads in an SMT processor 有权
标题翻译：用于在SMT处理器的线程之间共享缓存中的数据的方法，装置和计算机程序产品
公开(公告)号：US07318127B2
公开(公告)日：2008-01-08
申请号：US11055820
申请日：2005-02-11
申请人： David Allen Hrusecky , Sheldon B. Levenstein , Bruce Joseph Ronchetti , Anthony Saporito
发明人： David Allen Hrusecky , Sheldon B. Levenstein , Bruce Joseph Ronchetti , Anthony Saporito
IPC分类号： G06F12/14
CPC分类号： G06F12/0842 , G06F12/084 , G06F12/0862
摘要： A method, apparatus, and computer program product are disclosed in a data processing system for sharing data in a cache among multiple threads in a simultaneous multi-threaded (SMT) processor. The SMT processor executes multiple threads concurrently during each clock cycle. The cache is dynamically allocated for use among the multiple threads. Portions of the cache are capable of being designated to store private data that is used exclusively by only a first one of the threads. The portions of the cache are capable of being designated to store shared data that can be used by any one of the multiple threads. The size of the portions can be changed dynamically during execution of the threads.
摘要翻译：在用于在同时多线程（SMT）处理器中的多个线程之间的高速缓存中共享数据的数据处理系统中公开了一种方法，装置和计算机程序产品。 SMT处理器在每个时钟周期内同时执行多个线程。动态分配缓存以在多个线程之间使用。高速缓存的一部分能够被指定为仅存储第一个线程专用的专用数据。高速缓存的部分能够被指定为存储可由多个线程中的任何一个使用的共享数据。在执行线程期间，可以动态地更改部分的大小。

32. 发明申请

US20060184822A1 Auxiliary mechanism to manage instruction restart and restart coming in a lookahead processor 有权
标题翻译：辅助机制，用于管理指令重新启动和重新启动进入前瞻处理器
公开(公告)号：US20060184822A1
公开(公告)日：2006-08-17
申请号：US11055844
申请日：2005-02-11
申请人： Miles Dooley , Joaquin Hinojosa , Bruce Ronchetti , Anthony Saporito
发明人： Miles Dooley , Joaquin Hinojosa , Bruce Ronchetti , Anthony Saporito
IPC分类号： G06F11/00
CPC分类号： G06F9/3861 , G06F9/3842 , G06F11/141
摘要： A management system that controls a restart interface in a data processing system. The management system switches control of the interface from a distributed network managed by the caches to the management system. The management system is capable of detecting errors and seizing control of the interface in order to remedy any errors that occur within the interface.
摘要翻译：控制数据处理系统中的重启界面的管理系统。管理系统将接口控制从高速缓存管理的分布式网络切换到管理系统。管理系统能够检测错误并占用接口的控制，以补救接口内发生的任何错误。

33. 发明申请

US20060184741A1 Method, apparatus, and computer program product for sharing data in a cache among threads in an SMT processor 有权
标题翻译：用于在SMT处理器的线程之间共享缓存中的数据的方法，装置和计算机程序产品
公开(公告)号：US20060184741A1
公开(公告)日：2006-08-17
申请号：US11055820
申请日：2005-02-11
申请人： David Hrusecky , Sheldon Levenstein , Bruce Ronchetti , Anthony Saporito
发明人： David Hrusecky , Sheldon Levenstein , Bruce Ronchetti , Anthony Saporito
IPC分类号： G06F12/00
CPC分类号： G06F12/0842 , G06F12/084 , G06F12/0862
摘要： A method, apparatus, and computer program product are disclosed in a data processing system for sharing data in a cache among multiple threads in a simultaneous multi-threaded (SMT) processor. The SMT processor executes multiple threads concurrently during each clock cycle. The cache is dynamically allocated for use among the multiple threads. Portions of the cache are capable of being designated to store private data that is used exclusively by only a first one of the threads. The portions of the cache are capable of being designated to store shared data that can be used by any one of the multiple threads. The size of the portions can be changed dynamically during execution of the threads.
摘要翻译：在用于在同时多线程（SMT）处理器中的多个线程之间的高速缓存中共享数据的数据处理系统中公开了一种方法，装置和计算机程序产品。 SMT处理器在每个时钟周期内同时执行多个线程。动态分配缓存以在多个线程之间使用。高速缓存的一部分能够被指定为仅存储第一个线程专用的专用数据。高速缓存的部分能够被指定为存储可由多个线程中的任何一个使用的共享数据。在执行线程期间，可以动态地更改部分的大小。

34. 发明申请

US20060184739A1 Mechanism in a multi-threaded microprocessor to maintain best case demand instruction redispatch 有权
公开(公告)号：US20060184739A1
公开(公告)日：2006-08-17
申请号：US11055818
申请日：2005-02-11
申请人： Scott Frommer , Sheldon Levenstein , Bruce Ronchetti , Anthony Saporito
发明人： Scott Frommer , Sheldon Levenstein , Bruce Ronchetti , Anthony Saporito
IPC分类号： G06F12/00
CPC分类号： G06F9/383 , G06F9/3836 , G06F9/384 , G06F9/3842 , G06F9/3851 , G06F9/3857 , G06F9/3861 , G06F12/0897
摘要： A method and system for maintaining a best-case demand redispatch of an instruction to allow for maximizing the time a rejected thread may execute in lookahead execution mode, while maintaining the smallest L1 cache miss penalty supported by the memory subsystem. In response to a demand miss, a load/store unit sends a fetch request to the next level cache. The cache line of the demand miss is examined to identify the critical sector. Once the critical sector is identified, a best-case data return time is determined based on the fastest time the next level cache is able to return the critical sector of the cache line. The load/store unit then sends a speculative warning to the dispatch unit to coincide with the best-case data return, wherein the speculative warning prepares the dispatch unit to resend the instruction for execution as soon as data is available to the processor core.

35. 发明申请

US20060179227A1 Mechanism and apparatus allowing an N-way set associative cache, implementing a hybrid pseudo-LRU replacement algorithm, to have N L1 miss fetch requests simultaneously inflight regardless of their congruence class 有权
标题翻译：允许N路组关联高速缓存的机制和装置，实现混合伪LRU替换算法，以使N L1未命中提取请求同时运行，而不管其一致等级
公开(公告)号：US20060179227A1
公开(公告)日：2006-08-10
申请号：US11054293
申请日：2005-02-09
申请人： David Hrusecky , Sheldon Levenstein , Bruce Ronchetti , Anthony Saporito
发明人： David Hrusecky , Sheldon Levenstein , Bruce Ronchetti , Anthony Saporito
IPC分类号： G06F12/00
CPC分类号： G06F12/0859 , G06F12/124 , G06F12/125 , G06F12/127
摘要： A method, system, and computer program product for supporting multiple fetch requests to the same congruence class in an n-way set associative cache. Responsive to receiving an incoming fetch instruction at a load/store unit, outstanding valid fetch entries in the n-way set associative cache that have the same cache congruence class as the incoming fetch instruction are identified. SetIDs in used by these identified outstanding valid fetch entries are determined. A resulting setID is assigned to the incoming fetch instruction based on the identified setIDs, wherein the resulting setID assigned is a setID not currently in use by the outstanding valid fetch entries. The resulting setID for the incoming fetch instruction is written in a corresponding entry in the n-way set associative cache.
摘要翻译：一种方法，系统和计算机程序产品，用于在n路组关联高速缓存中支持对同一个同余类的多个提取请求。响应于在加载/存储单元处接收到传入的取指令，识别n路组关联高速缓冲存储器中具有与传入获取指令相同的高速缓存一致类的未完成的有效提取条目。确定这些识别的未完成的有效提取条目使用的SetID。所得到的setID被分配给基于所识别的setID的传入获取指令，其中分配的所得到的setID是未被提交的有效提取条目当前未使用的setID。用于传入提取指令的结果setID写入n路组关联高速缓存中的相应条目。

36. 发明申请

US20060179221A1 System and method for tracking changes in L1 data cache directory 有权
标题翻译：用于跟踪L1数据缓存目录中的更改的系统和方法
公开(公告)号：US20060179221A1
公开(公告)日：2006-08-10
申请号：US11054273
申请日：2005-02-09
申请人： Sheldon Levenstein , Anthony Saporito
发明人： Sheldon Levenstein , Anthony Saporito
IPC分类号： G06F12/00
CPC分类号： G06F12/0855
摘要： Method, system and computer program product for tracking changes in an L1 data cache directory. A method for tracking changes in an L1 data cache directory determines if data to be written to the L1 data cache is to be written to an address to be changed from an old address to a new address. If it is determined that the data to be written is to be written to an address to be changed, a determination is made if the data to be written is associated with the old address or the new address. If it is determined that the data is to be written to the new address, the data is allowed to be written to the new address following a prescribed delay after the address to be changed is changed. The method is preferably implemented in a system that provides a Store Queue (STQU) design that includes a Content Addressable Memory (CAM)-based store address tracking mechanism that includes early and late write CAM ports. The method eliminates time windows and the need for an extra copy of the L1 data cache directory.
摘要翻译：方法，系统和计算机程序产品，用于跟踪L1数据缓存目录中的更改。用于跟踪L1数据高速缓存目录中的变化的方法确定要写入L1数据高速缓存的数据是否被写入要从旧地址改变到新地址的地址。如果确定要写入的数据要写入要改变的地址，则确定要写入的数据是否与旧地址或新地址相关联。如果确定要将数据写入新地址，则在要更改的地址改变之后，允许将数据写入到遵循规定延迟的新地址。该方法优选地在提供包括基于内容寻址存储器（CAM）的存储地址跟踪机制的存储队列（STQU）设计的系统中实现，该机制包括早期和晚期写入CAM端口。该方法消除了时间窗口，并需要额外的L1数据高速缓存目录副本。

37. 发明申请

US20130339684A1 RESTRICTING PROCESSING WITHIN A PROCESSOR TO FACILITATE TRANSACTION COMPLETION 有权
公开(公告)号：US20130339684A1
公开(公告)日：2013-12-19
申请号：US13524833
申请日：2012-06-15
申请人： Khary J. Alexander , Brenton F. Belmar , Christian Jacobi , Randall W. Philley , Anthony Saporito , Timothy J. Slegel
发明人： Khary J. Alexander , Brenton F. Belmar , Christian Jacobi , Randall W. Philley , Anthony Saporito , Timothy J. Slegel
IPC分类号： G06F9/30
CPC分类号： G06F9/3861 , G06F9/3004 , G06F9/30087 , G06F9/38 , G06F9/3857 , G06F9/466 , G06F9/467 , G06F9/52 , G06F9/524
摘要： Processing of transactions within a computing environment is facilitated by taking actions to increase the chances of successfully executing a transaction. A counter is maintained that provides a count of how often a transaction has aborted. The counter increments the count each time the transaction is aborted, and it is reset to zero upon successful completion of the transaction or an interruption leading to no more re-executions of the transaction. If the count reaches a threshold value, then an interrupt is presented and transaction execution is unsuccessful. However, before the count reaches the threshold, a number of actions may be taken to increase the chances of successfully executing the transaction. These actions include actions to be performed within the processor executing the transaction, and/or actions to be performed against conflicting processors.

38. 发明授权

US07814374B2 System and method for the capture and preservation of intermediate error state data 有权
标题翻译：捕获和保存中间错误状态数据的系统和方法
公开(公告)号：US07814374B2
公开(公告)日：2010-10-12
申请号：US11625006
申请日：2007-01-19
申请人： Douglas Balazich , Michael Billeci , Anthony Saporito , Timothy J. Slegel
发明人： Douglas Balazich , Michael Billeci , Anthony Saporito , Timothy J. Slegel
IPC分类号： G06F11/00
CPC分类号： G06F11/0772 , G06F11/0724 , G06F11/0778
摘要： A multiprocessor chip system having the capability to capture and preserve intermediate machine error state data, wherein the system comprises a second level cache, wherein the second level cache is commonly interfaced with a primary and secondary processing core, and at least two primary error event registers, wherein each primary error event register is logically associated to a respective processing core. Further, at least two secondary error event registers, wherein each secondary error event register is logically associated to a respective processing core, and at least two sub-primary error accumulation registers, wherein each sub-primary error accumulation register is logically associated to a respective primary error event register and a secondary error event register.
摘要翻译：一种具有捕获和保存中间机器错误状态数据的能力的多处理器芯片系统，其中所述系统包括第二级高速缓存，其中所述第二级高速缓存通常与初级和次级处理核心以及至少两个主要错误事件寄存器，其中每个主要错误事件寄存器在逻辑上与相应的处理核心相关联。此外，至少两个次级错误事件寄存器，其中每个次级错误事件寄存器在逻辑上与相应的处理核心相关联，以及至少两个子主要错误累积寄存器，其中每个子主要错误累积寄存器在逻辑上与相应的主要错误事件寄存器和辅助错误事件寄存器。

39. 发明授权

US07571283B2 Mechanism in a multi-threaded microprocessor to maintain best case demand instruction redispatch 有权
标题翻译：机制在多线程微处理器中维护最佳情况需求指令重新分配
公开(公告)号：US07571283B2
公开(公告)日：2009-08-04
申请号：US12113561
申请日：2008-05-01
申请人： Scott B. Frommer , Sheldon B. Levenstein , Bruce J. Ronchetti , Anthony Saporito
发明人： Scott B. Frommer , Sheldon B. Levenstein , Bruce J. Ronchetti , Anthony Saporito
IPC分类号： G06F12/08
CPC分类号： G06F9/383 , G06F9/3836 , G06F9/384 , G06F9/3842 , G06F9/3851 , G06F9/3857 , G06F9/3861 , G06F12/0897
摘要： A method and system for maintaining a best-case demand redispatch of an instruction to allow for maximizing the time a rejected thread may execute in lookahead execution mode, while maintaining the smallest L1 cache miss penalty supported by the memory subsystem. In response to a demand miss, a load/store unit sends a fetch request to the next level cache. The cache line of the demand miss is examined to identify the critical sector. Once the critical sector is identified, a best-case data return time is determined based on the fastest time the next level cache is able to return the critical sector of the cache line. The load/store unit then sends a speculative warning to the dispatch unit to coincide with the best-case data return, wherein the speculative warning prepares the dispatch unit to resend the instruction for execution as soon as data is available to the processor core.
摘要翻译：一种方法和系统，用于维持指令的最佳情况需求重新分配，以允许最大化被拒绝的线程可以在前瞻执行模式中执行的时间，同时保持由存储器子系统支持的最小的L1高速缓存未命中。响应于需求未命中，加载/存储单元向下一级高速缓存发送提取请求。检查需求缺失的高速缓存行以确定关键部门。一旦确定了关键扇区，则最佳情况下的数据返回时间是基于下一级高速缓存能够返回高速缓存线的关键扇区的最快时间来确定的。加载/存储单元然后向调度单元发送与最佳情况数据返回一致的推测警告，其中，一旦数据可用于处理器核心，推测警告就准备调度单元重新发送执行指令。

40. 发明申请

US20080263283A1 System and Method for Tracking Changes in L1 Data Cache Directory 有权
标题翻译：跟踪L1数据缓存目录更改的系统和方法
公开(公告)号：US20080263283A1
公开(公告)日：2008-10-23
申请号：US12131432
申请日：2008-06-02
申请人： Sheldon B. Levenstein , Anthony Saporito
发明人： Sheldon B. Levenstein , Anthony Saporito
IPC分类号： G06F12/00
CPC分类号： G06F12/0855
摘要： Method, system and computer program product for tracking changes in an L1 data cache directory. A method for tracking changes in an L1 data cache directory determines if data to be written to the L1 data cache is to be written to an address to be changed from an old address to a new address. If it is determined that the data to be written is to be written to an address to be changed, a determination is made if the data to be written is associated with the old address or the new address. If it is determined that the data is to be written to the new address, the data is allowed to be written to the new address following a prescribed delay after the address to be changed is changed. The method is preferably implemented in a system that provides a Store Queue (STQU) design that includes a Content Addressable Memory (CAM)-based store address tracking mechanism that includes early and late write CAM ports. The method eliminates time windows and the need for an extra copy of the L1 data cache directory.
摘要翻译：方法，系统和计算机程序产品，用于跟踪L1数据缓存目录中的更改。用于跟踪L1数据高速缓存目录中的变化的方法确定要写入L1数据高速缓存的数据是否被写入要从旧地址改变到新地址的地址。如果确定要写入的数据要写入要改变的地址，则确定要写入的数据是否与旧地址或新地址相关联。如果确定要将数据写入新地址，则在要更改的地址改变之后，允许将数据写入到遵循规定延迟的新地址。该方法优选地在提供包括基于内容寻址存储器（CAM）的存储地址跟踪机制的存储队列（STQU）设计的系统中实现，该机制包括早期和晚期写入CAM端口。该方法消除了时间窗口，并需要额外的L1数据高速缓存目录副本。

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