专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明授权

US07342460B2 Expanded pull range for a voltage controlled clock synthesizer 有权
标题翻译：电压控制时钟合成器的扩展拉范围
公开(公告)号：US07342460B2
公开(公告)日：2008-03-11
申请号：US11278326
申请日：2006-03-31
申请人： Jeffrey S. Batchelor , Axel Thomsen
发明人： Jeffrey S. Batchelor , Axel Thomsen
IPC分类号： H03L7/18
CPC分类号： H03L7/1976 , H03L1/026 , H03L1/027 , H03L7/0992 , H03L7/10 , H03L7/197 , H03L7/23
摘要： A technique provides a clock source that meets accuracy requirements, allows the use of a low cost resonator, provides a wide range of output frequencies, and provides suitable phase noise performance. The technique generates a clock signal having a target output frequency using a controllable oscillator having at least one continuous frequency range of operation. The technique dynamically adjusts a reference control value based on a voltage for adjusting a frequency of the clock signal around a frequency determined by the reference control value. The reference control value is adjusted to be approximately within the center of an actual pull range corresponding to the controllable oscillator and a voltage control input of the controllable oscillator. The effective pull range of the controllable oscillator is continuous across the at least one continuous frequency range of operation.
摘要翻译：一种技术提供了满足精度要求的时钟源，允许使用低成本谐振器，提供宽范围的输出频率，并提供合适的相位噪声性能。该技术使用具有至少一个连续的操作频率范围的可控振荡器来产生具有目标输出频率的时钟信号。该技术基于用于调整围绕由参考控制值确定的频率的时钟信号的频率的电压来动态地调整参考控制值。参考控制值被调整为大约在对应于可控振荡器的实际牵引范围的中心和可控振荡器的电压控制输入的中心。可控振荡器的有效牵引范围在至少一个连续的操作频率范围内是连续的。

32. 发明授权

US07288998B2 Voltage controlled clock synthesizer 有权
标题翻译：电压时钟合成器
公开(公告)号：US07288998B2
公开(公告)日：2007-10-30
申请号：US11270957
申请日：2005-11-10
申请人： Axel Thomsen , Yunteng Huang , Jerrell P. Hein , Derrick C. Wei
发明人： Axel Thomsen , Yunteng Huang , Jerrell P. Hein , Derrick C. Wei
IPC分类号： H03L7/00
CPC分类号： H03L7/0898 , H03L1/022 , H03L1/026 , H03L7/095 , H03L7/0992 , H03L7/197 , H03L7/1976 , H03L7/23 , H03L7/235 , H03L2207/50 , H04J3/0688
摘要： A voltage controlled clock synthesizer includes a phase-locked loop (PLL) circuit that receives a timing reference signal, a controllable oscillator circuit, such as a VCO, providing an oscillator output signal, and a feedback divider circuit coupled to the oscillator output signal. The frequency of the oscillator output signal is determined in part according to a stored value used to generate a first digital control signal that determines a divide ratio of the feedback divider circuit. A control voltage present on a voltage control input adjusts the frequency of the oscillator output signal around a frequency determined by the stored value. The control voltage is converted to second digital signal and is utilized in determining the first digital control signal in combination with the stored value.
摘要翻译：电压控制时钟合成器包括接收定时参考信号的锁相环（PLL）电路，提供振荡器输出信号的可控振荡器电路，例如VCO，以及耦合到振荡器输出信号的反馈分频器电路。振荡器输出信号的频率部分地根据用于产生确定反馈分频器电路的分频比的第一数字控制信号的存储值来确定。存在于电压控制输入端的控制电压根据由存储的值确定的频率调整振荡器输出信号的频率。控制电压被转换为第二数字信号，并用于与所存储的值组合确定第一数字控制信号。

33. 发明申请

US20070146083A1 CALIBRATION OF OSCILLATOR DEVICES 审中-公开
标题翻译：振荡器器件校准
公开(公告)号：US20070146083A1
公开(公告)日：2007-06-28
申请号：US11681941
申请日：2007-03-05
申请人： Jerrell Hein , Axel Thomsen
发明人： Jerrell Hein , Axel Thomsen
IPC分类号： H03L7/00
CPC分类号： H03L1/022 , H03L1/026 , H03L7/095 , H03L7/0992 , H03L7/1976 , H03L7/235 , H03L2207/50
摘要： A clock device having a resonating device such as a crystal of SAW supplying a controllable oscillator such as a digitally controlled oscillator is calibrated by supplying a calibration clock. A phase-locked loop is utilized to generate one or more correction factors causing the PLL to lock to the calibration clock. The one or more correction factors are then stored in non-volatile memory.
摘要翻译：通过提供校准时钟来校准具有诸如数字控制振荡器等可控振荡器的SAW的晶体谐振装置的时钟装置。利用锁相环产生一个或多个校正因子，使PLL锁定到校准时钟。然后将一个或多个校正因子存储在非易失性存储器中。

34. 发明授权

US07187216B2 Phase selectable divider circuit 有权
标题翻译：相位可选分频电路
公开(公告)号：US07187216B2
公开(公告)日：2007-03-06
申请号：US10878198
申请日：2004-06-28
申请人： Lizhong Sun , Douglas F. Pastorello , Richard J. Juhn , Axel Thomsen
发明人： Lizhong Sun , Douglas F. Pastorello , Richard J. Juhn , Axel Thomsen
IPC分类号： H03K21/00
CPC分类号： H03K23/66 , H03L7/193 , H03L7/1976
摘要： A phase selectable divider circuit includes a select circuit receiving a plurality of signals having a common frequency and a different phase. One of the plurality of signals, having a first phase, is selected as a selector circuit output signal. A first value corresponding to the first phase is summed with a second value corresponding to a phase offset from the first phase to generate a sum indicative thereof. That sum is used to select a second one of the signals having a second phase as the next selector circuit output signal. As successive sums are generated, a pulse train is supplied by selector circuit having a desired frequency.
摘要翻译：相位选择分频电路包括接收具有共同频率和不同相位的多个信号的选择电路。选择具有第一相位的多个信号中的一个作为选择器电路输出信号。对应于第一相位的第一值与对应于从第一相位的相位偏移的第二值相加，以产生指示其的和。该和用于选择具有第二相位的第二信号作为下一个选择器电路输出信号。当产生连续的和时，由选择器电路提供具有期望频率的脉冲串。

35. 发明授权

US07113009B2 Programmable frequency divider 有权
标题翻译：可编程分频器
公开(公告)号：US07113009B2
公开(公告)日：2006-09-26
申请号：US10807852
申请日：2004-03-24
申请人： Lizhong Sun , Bruce Del Signore , Axel Thomsen , Douglas F. Pastorello
发明人： Lizhong Sun , Bruce Del Signore , Axel Thomsen , Douglas F. Pastorello
IPC分类号： H03K25/00
CPC分类号： H03K21/40 , H03K21/08 , H03K23/667
摘要： A divider is disclosed herein. The divider includes a sequence of divide stages programmably coupled to provide a variety of divide ratios. The divider also includes one or more multiplexers to feedback the output of a divide stage to the input of a divide stage earlier in the sequence of divide stages. The divider may also include duty cycle correction circuitry and self correction logic to correct abnormal logic states. The divide stages can operate in synchronism with each other. Multiplexer functionality, self correction circuitry functionality, and divide stage functionality may be implemented in a combination latch circuit.
摘要翻译：本文公开了一种分频器。分频器包括可编程地耦合以提供各种分频比的分频级序列。分频器还包括一个或多个多路复用器，用于将分频级的输出反馈到除法级序列之前的分频级的输入端。分频器还可以包括占空比校正电路和用于校正异常逻辑状态的自校正逻辑。分级阶段可以相互同步运行。多路复用器功能，自校正电路功能和分频功能可以在组合锁存电路中实现。

36. 发明授权

US08952751B2 Amplifier circuits and methods of amplifying an input signal 有权
标题翻译：放大器电路和放大输入信号的方法
公开(公告)号：US08952751B2
公开(公告)日：2015-02-10
申请号：US13732135
申请日：2012-12-31
申请人： Axel Thomsen , Gang Yuan
发明人： Axel Thomsen , Gang Yuan
IPC分类号： H03F1/02 , H03F3/00 , H03F3/45
CPC分类号： H03F3/005 , H03F3/45197 , H03F3/45645 , H03F2203/45404 , H03F2203/45418 , H03F2203/45421 , H03F2203/45424 , H03F2203/45444 , H03F2203/45446 , H03F2203/45528 , H03F2203/45648
摘要： A method of operating an amplifier circuit having a pre-charge phase and a sample/conversion phase includes, during a pre-charge phase, charging first and second capacitors to first and second bias voltages. The first capacitor is coupled to a first input of an amplifier circuit, which has a second input and an output. The second capacitor is coupled to the second input. During a sample/conversion phase, the first input of the amplifier circuit is coupled to an input signal through the first capacitor to level-shift the input signal according to the first bias voltage and the output of the amplifier is coupled to the second input through the second capacitor to level shift a feedback signal according to the second bias voltage.
摘要翻译：操作具有预充电阶段和采样/转换阶段的放大器电路的方法包括在预充电阶段期间将第一和第二电容器充电到第一和第二偏置电压。第一电容器耦合到具有第二输入和输出的放大器电路的第一输入端。第二电容器耦合到第二输入端。在采样/转换阶段期间，放大器电路的第一输入通过第一电容耦合到输入信号，以根据第一偏置电压对输入信号进行电平移位，并且放大器的输出端通过所述第二电容器根据所述第二偏置电压对反馈信号进行电平移位。

37. 发明申请

US20140176250A1 Relaxation Oscillator 有权
标题翻译：放松振荡器
公开(公告)号：US20140176250A1
公开(公告)日：2014-06-26
申请号：US13721885
申请日：2012-12-20
申请人： Axel Thomsen , Pavel Konecny , Xiaodong Wang
发明人： Axel Thomsen , Pavel Konecny , Xiaodong Wang
IPC分类号： H03K3/011
CPC分类号： H03K3/0231
摘要： In an embodiment, a method includes: during a first portion of a cycle of a clock signal generated by an oscillator, pre-charging a first capacitor of a first switched capacitor stage until a first comparator determines that a first node voltage of the first switched capacitor stage is greater than a first reference voltage at a first reference voltage node; applying a second reference voltage to the first reference voltage node; and responsive to a first edge of the clock signal, charging the first capacitor until the first comparator determines that the first node voltage is greater than the second reference voltage at the first reference voltage node.
摘要翻译：在一个实施例中，一种方法包括：在由振荡器产生的时钟信号的周期的第一部分期间，对第一开关电容器级的第一电容器进行预充电，直到第一比较器确定第一开关的第一节点电压电容器级大于第一参考电压节点处的第一参考电压; 将第二参考电压施加到所述第一参考电压节点; 并且响应于所述时钟信号的第一边沿，对所述第一电容器充电直到所述第一比较器确定所述第一节点电压大于所述第一参考电压节点处的所述第二参考电压。

38. 发明授权

US08203370B2 Schmitt trigger with gated transition level control 有权
标题翻译：施密特触发器具有门控过渡电平控制
公开(公告)号：US08203370B2
公开(公告)日：2012-06-19
申请号：US12494621
申请日：2009-06-30
申请人： Shouli Yan , Zhiwei Dong , Axel Thomsen
发明人： Shouli Yan , Zhiwei Dong , Axel Thomsen
IPC分类号： H03K3/00
CPC分类号： H03K3/3565 , H03K5/088
摘要： A Schmitt trigger comprises first and second circuitry. The first circuitry receives an input voltage and provides an output voltage at either a logical “low” or a logical “high” voltage level responsive to the input voltage and a first bias voltage. The second circuitry connects to the first circuitry to generate a second bias current for generating the output voltage. The second bias current is larger than the first bias current. The Schmitt trigger operates in a low power mode of operation using only the first bias voltage to maintain the logical “low” voltage level or the logical “high” voltage level at a substantially constant level. In a high power mode of operation the Schmitt trigger uses the second bias voltage during transition periods between the logical “low” voltage level and the logical “high” voltage level.
摘要翻译：施密特触发器包括第一和第二电路。第一电路接收输入电压并且响应于输入电压和第一偏置电压在逻辑“低”或逻辑“高”电压电平提供输出电压。第二电路连接到第一电路以产生用于产生输出电压的第二偏置电流。第二偏置电流大于第一偏置电流。施密特触发器仅在第一偏置电压下工作在低功耗工作模式，以将逻辑“低”电压电平或逻辑“高”电压电平维持在基本恒定的水平。在高功率工作模式下，施密特触发器在逻辑“低”电压电平和逻辑“高”电压电平之间的过渡期间使用第二偏置电压。

39. 发明授权

US07834706B2 Phase error cancellation 有权
标题翻译：相位误差消除
公开(公告)号：US07834706B2
公开(公告)日：2010-11-16
申请号：US11571077
申请日：2005-06-28
申请人： Doug Frey , Axel Thomsen , Ligang Zhang
发明人： Doug Frey , Axel Thomsen , Ligang Zhang
IPC分类号： H03L7/00
CPC分类号： H03L7/0891 , H03L7/1976
摘要： A noise cancellation signal is generated for a fractional-N phase-locked loop (200). A divide value is provided to a first delta sigma modulator circuit (203), which generates a divide control signal to control a divide value of a feedback divider (208) in the phase-locked loop. An error term (e) is generated that is indicative of a difference between the generated divide control signal and the divide value supplied to the first delta sigma modulator circuit. The error term is integrated in an integrator (320) to generate an integrated error term (x), where xk+1=xk+ek; and a phase error correction circuit (209) utilizes the error term ek and the integrated error term xk to generate the phase error cancellation signal.
摘要翻译：对于分数N锁相环（200）产生噪声消除信号。分频值被提供给第一ΔΣ调制器电路（203），其产生除法控制信号以控制锁相环中的反馈分频器（208）的除法值。生成指示所生成的除法控制信号和提供给第一ΔΣ调制器电路的除法值之间的差异的误差项（e）。误差项集成在积分器（320）中以产生积分误差项（x），其中xk + 1 = xk + ek; 并且相位误差校正电路（209）利用误差项ek和积分误差项xk来产生相位误差消除信号。

40. 发明授权

US07295077B2 Multi-frequency clock synthesizer 有权
标题翻译：多频时钟合成器
公开(公告)号：US07295077B2
公开(公告)日：2007-11-13
申请号：US11270954
申请日：2005-11-10
申请人： Axel Thomsen , Yunteng Huang , Jerrell P. Hein , Michael Petrowski, III
发明人： Axel Thomsen , Yunteng Huang , Jerrell P. Hein , Michael Petrowski, III
IPC分类号： H03B21/00
CPC分类号： H03L7/23 , H03L7/0898 , H03L7/197 , H03L7/1976
摘要： A phase-locked loop (PLL) circuit includes an input for receiving a timing reference signal, a phase detector circuit coupled to receive the timing reference signal, a controllable oscillator circuit controlled according to an output of the phase detector circuit, and a feedback divider circuit having an output coupled to the phase detector and an input coupled to the controllable oscillator circuit. The phase-locked loop circuit is coupled to output one of a plurality of output signals having an arbitrary frequency relationship to each other according to a frequency selection mechanism, the frequency selection mechanism including one or more input terminals coupled to control a divide ratio of the feedback divider circuit. The frequency selection mechanism selects one of a plurality of stored values. The selected stored value controls, at least in part, a divide ratio of the feedback divider circuit, thereby providing a pin programmable device capable of selecting among output frequencies having an arbitrary relationship to each other.
摘要翻译：锁相环（PLL）电路包括用于接收定时参考信号的输入端，耦合以接收定时参考信号的相位检测器电路，根据相位检测器电路的输出控制的可控振荡器电路，以及反馈分配器电路具有耦合到相位检测器的输出端和耦合到可控振荡器电路的输入端。锁相环电路根据频率选择机构耦合到输出具有任意频率关系的多个输出信号中的一个，所述频率选择机构包括一个或多个输入端，用于控制所述频率选择机构的分频比反馈分频电路。频率选择机构选择多个存储值中的一个。选择的存储值至少部分地控制反馈分频器电路的分频比，从而提供能够在彼此具有任意关系的输出频率之间进行选择的引脚可编程器件。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式