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31. 发明申请

US20080061357A1 Semiconductor device with double barrier film 审中-公开
标题翻译：具有双阻挡膜的半导体器件
公开(公告)号：US20080061357A1
公开(公告)日：2008-03-13
申请号：US11980561
申请日：2007-10-31
申请人： Makoto Sakuma , Yasuhiko Matsunaga , Fumitaka Arai , Kikuko Sugimae
发明人： Makoto Sakuma , Yasuhiko Matsunaga , Fumitaka Arai , Kikuko Sugimae
IPC分类号： H01L29/788
CPC分类号： H01L27/115 , H01L27/105 , H01L27/11526 , H01L27/11529
摘要： A semiconductor device comprising a first insulation layer, a second insulation layer, a first barrier film, a second barrier film, a diffusion layer. The device further comprises an upper contact hole, a lower contact hole, and a contact plug. The upper contact hole penetrates the second insulation layer and has a bottom in the second barrier film. The bottom has a width greater than a trench made in the first insulation layer, as measured in a direction crossing the widthwise direction of the trench. The lower contact hole penetrates the first insulation layer and first barrier film, communicates with the first contact hole via the trench and is provided on the diffusion layer. The upper portion of the lower contact hole has the same width as the trench. The contact plug is provided in the upper contact hole and lower contact hole.
摘要翻译：一种半导体器件，包括第一绝缘层，第二绝缘层，第一阻挡膜，第二阻挡膜，扩散层。该装置还包括上接触孔，下接触孔和接触塞。上接触孔穿透第二绝缘层，并且在第二阻挡膜中具有底部。底部的宽度大于在与沟槽宽度方向交叉的方向上测量的在第一绝缘层中形成的沟槽。下接触孔穿过第一绝缘层和第一阻挡膜，经由沟槽与第一接触孔连通并设置在扩散层上。下接触孔的上部具有与沟槽相同的宽度。接触塞设置在上接触孔和下接触孔中。

32. 发明申请

US20070196986A1 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US20070196986A1
公开(公告)日：2007-08-23
申请号：US11676814
申请日：2007-02-20
申请人： Masayuki Ichige , Makoto Sakuma , Fumitaka Arai
发明人： Masayuki Ichige , Makoto Sakuma , Fumitaka Arai
IPC分类号： H01L21/336
CPC分类号： H01L27/105 , H01L27/11526 , H01L27/11529 , H01L29/0638
摘要： A method for manufacturing a semiconductor device including a substrate, a memory cell region including first pattern, first guard ring around the memory cell, second guard ring around the first guard ring, an isolation region between the first and second guard ring, and a peripheral circuit region around the second guard ring and including second pattern, the method including exposing the resist film by multiple exposure including first and second exposures for forming latent images corresponding to the first and second patterns, a boundary area of the multiple exposure being set on the isolation region, on the first or second guard ring, or on an area between the first guard ring and the memory cell region, forming a resist pattern by developing the resist film, and etching the substrate with the resist pattern as a mask.
摘要翻译：一种半导体器件的制造方法，包括：衬底，包括第一图案的存储单元区域，存储单元周围的第一保护环，第一保护环周围的第二保护环，第一和第二保护环之间的隔离区域，电路区域，并且包括第二图案，所述方法包括通过多次曝光曝光所述抗蚀剂膜，所述多次曝光包括用于形成对应于所述第一和第二图案的潜像的第一和第二曝光，所述多次曝光的边界区域设置在在第一或第二保护环上或第一保护环和存储单元区域之间的区域上，通过显影抗蚀剂膜形成抗蚀剂图案，并用抗蚀剂图案作为掩模蚀刻基板。

33. 发明授权

US07122858B2 Nonvolatile semiconductor memory device including improved gate electrode 有权
公开(公告)号：US07122858B2
公开(公告)日：2006-10-17
申请号：US11118478
申请日：2005-05-02
申请人： Fumitaka Arai , Yasuhiko Matsunaga , Makoto Sakuma , Riichiro Shirota , Akira Shimizu
发明人： Fumitaka Arai , Yasuhiko Matsunaga , Makoto Sakuma , Riichiro Shirota , Akira Shimizu
IPC分类号： H01L29/788
CPC分类号： H01L27/115 , G11C16/0483 , G11C16/10 , H01L21/28273 , H01L27/11521 , H01L29/42324 , H01L29/42336 , H01L29/7883
摘要： A floating gate is formed on a semiconductor substrate via a gate insulating film. Diffused layers are formed as sources or drain regions on opposite sides of the floating gate in the semiconductor substrate. First and second control gates are formed opposite to both of the diffused layers on the opposite sides of the floating gate via an inter-gate insulating film to drive the floating gate.

34. 发明授权

US07027329B2 Nonvolatile semiconductor memory and programming method for the same 失效
公开(公告)号：US07027329B2
公开(公告)日：2006-04-11
申请号：US10865937
申请日：2004-06-14
申请人： Makoto Sakuma , Fumitaka Arai , Riichiro Shirota , Yasuhiko Matsunaga
发明人： Makoto Sakuma , Fumitaka Arai , Riichiro Shirota , Yasuhiko Matsunaga
IPC分类号： G11C16/04
CPC分类号： G11C16/10
摘要： A semiconductor memory has a memory cell matrix including a plurality of first and second cell columns alternately arranged along a row-direction, each of cell columns is implemented by a plurality of memory cell transistors, and peripheral circuits configured to drive the memory cell matrix and to read information from the memory cell matrix. The peripheral circuit encompasses (a) a leading program circuit configured to write first data into memory cell transistors in the first cell columns, (b) a lagging program circuit configured to write second data into memory cell transistors in the second cell columns after the first data are written, and (c) a voltage controller configured to control variation of threshold voltages for the memory cell transistors of the first cell columns.

35. 发明申请

US20050190600A1 Nonvolatile semiconductor memory device including improved gate electrode 有权
标题翻译：包括改进的栅电极的非易失性半导体存储器件
公开(公告)号：US20050190600A1
公开(公告)日：2005-09-01
申请号：US11118478
申请日：2005-05-02
申请人： Fumitaka Arai , Yasuhiko Matsunaga , Makoto Sakuma , Riichiro Shirota , Akira Shimizu
发明人： Fumitaka Arai , Yasuhiko Matsunaga , Makoto Sakuma , Riichiro Shirota , Akira Shimizu
IPC分类号： H01L27/115 , H01L21/8247 , H01L29/788 , G11C11/34
CPC分类号： H01L27/115 , G11C16/0483 , G11C16/10 , H01L21/28273 , H01L27/11521 , H01L29/42324 , H01L29/42336 , H01L29/7883
摘要： A floating gate is formed on a semiconductor substrate via a gate insulating film. Diffused layers are formed as sources or drain regions on opposite sides of the floating gate in the semiconductor substrate. First and second control gates are formed opposite to both of the diffused layers on the opposite sides of the floating gate via an inter-gate insulating film to drive the floating gate.
摘要翻译：通过栅极绝缘膜在半导体衬底上形成浮栅。扩散层在半导体衬底中的浮置栅极的相对侧上形成为源区或漏极区。第一和第二控制栅极通过栅极间绝缘膜与浮动栅极的相对侧上的两个扩散层相对形成，以驱动浮置栅极。

36. 发明授权

US07541654B2 Semiconductor memory device and semiconductor device including multilayer gate electrode 失效
标题翻译：半导体存储器件和包括多层栅电极的半导体器件
公开(公告)号：US07541654B2
公开(公告)日：2009-06-02
申请号：US11565843
申请日：2006-12-01
申请人： Fumitaka Arai , Makoto Sakuma
发明人： Fumitaka Arai , Makoto Sakuma
IPC分类号： H01L27/115
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524
摘要： In a memory cell array are arranged a plurality of cell units having memory cells and selection gate transistors to select the memory cell. A first selection gate line includes a control gate of the selection gate transistors. A second selection gate line is formed above the first selection gate line. The first selection gate line has a first gate electrode, a first inter-gate insulating film and a second gate electrode superimposed in this order. The first inter-gate insulating film has a first opening portion through which the first gate electrode and the second gate electrode come into contact with each other. A contact material is formed on the first selection gate line, and electrically connects the first selection gate line and the second selection gate line with each other. The contact material is arranged on the first selection gate line on which the first opening portion is not arranged.
摘要翻译：在存储单元阵列中布置有具有存储单元的多个单元单元和选择栅晶体管以选择存储单元。第一选择栅极线包括选择栅极晶体管的控制栅极。在第一选择栅极线之上形成第二选择栅极线。第一选择栅极线具有依次叠加的第一栅电极，第一栅间绝缘膜和第二栅电极。第一栅极间绝缘膜具有第一开口部，第一栅极电极和第二栅极电极相互接触。接触材料形成在第一选择栅极线上，并且使第一选择栅极线和第二选择栅极线彼此电连接。接触材料配置在不配置第一开口部的第一选择栅极线上。

37. 发明授权

US07416935B2 Method of manufacturing nonvolatile semiconductor memory device having adjacent selection transistors connected together 有权
标题翻译：具有连接在一起的相邻选择晶体管的非易失性半导体存储器件的制造方法
公开(公告)号：US07416935B2
公开(公告)日：2008-08-26
申请号：US11407242
申请日：2006-04-20
申请人： Makoto Sakuma , Fumitaka Arai
发明人： Makoto Sakuma , Fumitaka Arai
IPC分类号： H01L21/8238
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11524 , H01L29/42324
摘要： A method of manufacturing a nonvolatile semiconductor memory device, including forming a gate insulating film, a first conductive layer providing floating gates and a mask, in that order, on a semiconductor substrate, forming a plurality of element-isolating regions in the mask layer, first conductive layer, gate insulating film and semiconductor substrate; forming first trenches in parts of the first conductive layer separated by the element-isolating region; forming inter-gate insulating films on sides of each floating gate; forming control gates in the first trenches; making second trenches in parts of the mask layer and first conductive layer and in adjacent parts of the element-isolating regions; forming conductive members in the second trenches, wherein a top of the conductive members is at the same level as an upper surface of the mask layer; and removing parts of the first conductive layer and the gate insulating film exclusive of the conductive members.
摘要翻译：一种制造非易失性半导体存储器件的方法，包括在半导体衬底上形成栅绝缘膜，提供浮栅和掩模的第一导电层，在掩模层中形成多个元件隔离区，第一导电层，栅极绝缘膜和半导体衬底; 在由元件隔离区隔开的第一导电层的部分中形成第一沟槽; 在每个浮动栅极的侧面形成栅极间绝缘膜; 在第一沟槽中形成控制栅极; 在掩模层和第一导电层的部分以及元件隔离区的相邻部分中形成第二沟槽; 在所述第二沟槽中形成导电构件，其中所述导电构件的顶部处于与所述掩模层的上表面相同的水平; 以及去除不包括导电构件的第一导电层和栅极绝缘膜的部分。

38. 发明申请

US20080006885A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING 审中-公开
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US20080006885A1
公开(公告)日：2008-01-10
申请号：US11853544
申请日：2007-09-11
申请人： Fumitaka ARAI , Makoto Sakuma
发明人： Fumitaka ARAI , Makoto Sakuma
IPC分类号： H01L29/76 , H01L21/82
CPC分类号： H01L27/11524 , H01L21/76895 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11529
摘要： A semiconductor integrated circuit device comprises an insulated-gate field-effect transistor, the insulated-gate field-effect transistor comprising a device isolation insulating film that is provided to extend from an inside of a semiconductor substrate and to project from an upper surface of the semiconductor substrate, and defines a device region on the semiconductor substrate, a gate insulation film that is provided on the device region, a gate electrode that is provided on the gate insulation film, source/drain regions that are provided in the semiconductor substrate on both sides of the gate electrode, an insulation layer that is provided on the gate electrode, and a contact line that penetrates the insulation layer and is put in contact with the gate electrode.
摘要翻译：一种半导体集成电路器件，包括绝缘栅场效应晶体管，所述绝缘栅场效应晶体管包括器件隔离绝缘膜，所述器件隔离绝缘膜设置成从半导体衬底的内部延伸并且从所述半导体衬底的上表面突出半导体衬底，并且限定半导体衬底上的器件区域，设置在器件区域上的栅极绝缘膜，设置在栅极绝缘膜上的栅电极，设置在半导体衬底中的源极/漏极区域栅电极的侧面，设置在栅电极上的绝缘层和穿过绝缘层并与栅电极接触的接触线。

39. 发明授权

US07291875B2 Semiconductor device with double barrier film 失效
标题翻译：具有双阻挡膜的半导体器件
公开(公告)号：US07291875B2
公开(公告)日：2007-11-06
申请号：US11447947
申请日：2006-06-07
申请人： Makoto Sakuma , Yasuhiko Matsunaga , Fumitaka Arai , Kikuko Sugimae
发明人： Makoto Sakuma , Yasuhiko Matsunaga , Fumitaka Arai , Kikuko Sugimae
IPC分类号： H01L23/485
CPC分类号： H01L27/115 , H01L27/105 , H01L27/11526 , H01L27/11529
摘要： A semiconductor device comprising a first insulation layer, a second insulation layer, a first barrier film, a second barrier film, a diffusion layer. The device further comprises an upper contact hole, a lower contact hole, and a contact plug. The upper contact hole penetrates the second insulation layer and has a bottom in the second barrier film. The bottom has a width greater than a trench made in the first insulation layer, as measured in a direction crossing the widthwise direction of the trench. The lower contact hole penetrates the first insulation layer and first barrier film, communicates with the first contact hole via the trench and is provided on the diffusion layer. The upper portion of the lower contact hole has the same width as the trench. The contact plug is provided in the upper contact hole and lower contact hole.
摘要翻译：一种半导体器件，包括第一绝缘层，第二绝缘层，第一阻挡膜，第二阻挡膜，扩散层。该装置还包括上接触孔，下接触孔和接触塞。上接触孔穿透第二绝缘层，并且在第二阻挡膜中具有底部。底部的宽度大于在与沟槽宽度方向交叉的方向上测量的在第一绝缘层中形成的沟槽。下接触孔穿过第一绝缘层和第一阻挡膜，经由沟槽与第一接触孔连通并设置在扩散层上。下接触孔的上部具有与沟槽相同的宽度。接触塞设置在上接触孔和下接触孔中。

40. 发明申请

US20070034934A1 Semiconductor memory device with a stacked gate including a floating gate and a control gate and method of manufacturing the same 有权
标题翻译：具有包括浮动栅极和控制栅极的堆叠栅极的半导体存储器件及其制造方法
公开(公告)号：US20070034934A1
公开(公告)日：2007-02-15
申请号：US11582015
申请日：2006-10-16
申请人： Fumitaka Arai , Yasuhiko Matsunaga , Makoto Sakuma
发明人： Fumitaka Arai , Yasuhiko Matsunaga , Makoto Sakuma
IPC分类号： H01L29/76 , H01L21/8238
CPC分类号： G11C16/0433 , G11C16/0483 , H01L21/28273 , H01L27/115 , H01L27/11526 , H01L27/11546
摘要： A semiconductor memory device includes first and second MOS transistors. The first MOS transistor is formed on a region enclosed by a first element isolating region and includes a first gate insulating film and a first gate electrode. The second MOS transistor is formed on a region enclosed by a second element isolating region and includes a second gate insulating film and a second gate electrode. The upper part of the first and second element isolating regions project from a semiconductor substrate and their corners are curved. The width from the position where the first element isolating region contacts the first gate insulating film to the top surface end of the first element isolating region is equal to the width from the position where the second element isolating region contacts the second gate insulating film to the top surface end of the second element isolating region.
摘要翻译：半导体存储器件包括第一和第二MOS晶体管。第一MOS晶体管形成在由第一元件隔离区域包围的区域中，并且包括第一栅极绝缘膜和第一栅极电极。第二MOS晶体管形成在由第二元件隔离区域包围的区域中，并且包括第二栅极绝缘膜和第二栅极电极。第一元件隔离区域和第二元件隔离区域的上部从半导体基板突出并且它们的拐角是弯曲的。从第一元件隔离区域接触第一栅极绝缘膜的位置到第一元件隔离区域的顶面端部的宽度等于从第二元件隔离区域接触第二栅极绝缘膜到第二栅极绝缘膜的位置的宽度第二元件隔离区域的顶表面端。

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