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31. 发明授权

US06411618B1 Central office line card with code recognition for increasing data rates over PSTN 失效
标题翻译：中央办公室线卡，具有通过PSTN增加数据速率的代码识别
公开(公告)号：US06411618B1
公开(公告)日：2002-06-25
申请号：US09103496
申请日：1998-06-24
申请人： Keith L. Quiring , Alan Gatherer
发明人： Keith L. Quiring , Alan Gatherer
IPC分类号： H04L1228
CPC分类号： H04L12/2896 , H04L12/2856 , H04M3/005 , H04M3/007
摘要： A linecard (175) permits an increased rate connection between a subscriber (15) and a service provider (40) over the PSTN (50) includes an analog interface (152) a digital interface (165) coupled to the digital backplane (170) to the service provider's host server (34), a conversion circuit (258) interspersed between the analog interface (152) and the digital interface (165), and a linecard microcontroller (300) configured to request bandwidth on the backplane (170) A linecard (175) incorporates a codec (250) with a code recognition mechanism (200) to monitor the Pulse Code Modulated (PCM) input from the provider. The code recognition mechanism (200) provides a way to dynamically allocate and deallocate timeslots on the backplane (170).
摘要翻译：线路卡（175）允许通过PSTN（50）的用户（15）和服务提供商（40）之间的增加的速率连接包括模拟接口（152）耦合到数字背板（170）的数字接口（165）分布在模拟接口（152）和数字接口（165）之间的转换电路（258）以及被配置为在背板（170）A上请求带宽的线卡微控制器（300）向服务提供商的主机服务器（34）线卡（175）包含具有代码识别机构（200）的编解码器（250），以监视来自提供商的脉冲编码调制（PCM）输入。代码识别机制（200）提供了一种在背板（170）上动态地分配和释放时隙的方法。

32. 发明授权

US06370191B1 Efficient implementation of error approximation in blind equalization of data communications 有权
标题翻译：数据通信盲均衡中误差近似的有效实现
公开(公告)号：US06370191B1
公开(公告)日：2002-04-09
申请号：US09431687
申请日：1999-11-01
申请人： Shivaling S. Mahant-Shetti , Srinath Hosur , Alan Gatherer
发明人： Shivaling S. Mahant-Shetti , Srinath Hosur , Alan Gatherer
IPC分类号： H04L2710
CPC分类号： G06F7/552 , G06F2207/5525 , H04L25/0307 , H04L2025/03401 , H04L2025/03477 , H04L2025/0349 , H04L2025/03573 , H04L2025/0363
摘要： A cable modem (20) having a blind equalizer (40) in its equalization function (28) is disclosed. The blind equalizer (40) includes an adaptive equalizer (44) and an approximating update function (42) that provides updated equalization coefficients to the adaptive equalizer (44) using the Constant Modulus Algorithm, wherein the error in the adaptive equalizer output is estimated. The estimates are based upon a determination of the maximum and minimum of the real and i components of symbols output by the adaptive equalizer (44). Efficiency in the computations required for updating the equalizer coefficients is obtained, without sacrificing convergence.
摘要翻译：公开了一种在其均衡功能（28）中具有盲均衡器（40）的电缆调制解调器（20）。盲均衡器（40）包括使用恒模算法向自适应均衡器（44）提供更新的均衡系数的自适应均衡器（44）和近似更新功能（42），其中估计自适应均衡器输出中的误差。估计基于由自适应均衡器（44）输出的符号的真实和i分量的最大值和最小值的确定。获得更新均衡器系数所需的计算的效率，而不会牺牲收敛。

33. 发明授权

US06298366B1 Reconfigurable multiply-accumulate hardware co-processor unit 有权
标题翻译：可重构的乘法累加硬件协处理器单元
公开(公告)号：US06298366B1
公开(公告)日：2001-10-02
申请号：US09244973
申请日：1999-02-04
申请人： Alan Gatherer , Carl E. Lemonds, Jr. , Dale E. Hocevar , Ching-Yu Hung
发明人： Alan Gatherer , Carl E. Lemonds, Jr. , Dale E. Hocevar , Ching-Yu Hung
IPC分类号： G06F748
CPC分类号： G06F7/5443
摘要： A reconfigurable co-processor adapted for multiple multiply-accumulate operations includes plural pairs of multipliers, plural first adders receiving respective product outputs from a pairs of multipliers, and at least one second adder receiving sum outputs from a corresponding pair of first adders. The co-processor includes sign extend circuits at the output of each multiplier. One multiplier of each pair has a fixed left shift circuit that left shifts the product output a predetermined number of bits. The other multiplier in each pair includes a right shift circuit that right shifts the product output the number of bits. Multiplexers at the output of the first multiplier in each pair select the sign extended or the left shifted products. Multiplexers at the output of the second multiplier in each pair select the product, the right shifted product or pass through the inputs. The sign extend circuit for the second multiplier follows the multiplexer. Third adders receive the sum outputs of the second adders and produce a third sum output. These third adders include plural selectable output accumulators and variable right shifter at their outputs. The third adders may separately sum the product sums from four multipliers each. Alternatively, the third adders may accumulate the products of eight multipliers.
摘要翻译：适用于多重乘法运算的可重配置协处理器包括多对乘法器，多个第一加法器，从一对乘法器接收相应的乘积输出，以及至少一个第二加法器，从相应的第一加法器对接收和输出。协处理器在每个乘法器的输出端包括符号扩展电路。每对的一个乘法器具有固定的左移位电路，其使乘积输出偏移预定数量的位。每对中的另一个乘法器包括一个右移位电路，用于将乘积输出向右移位位数。每对中第一乘法器输出端的多路复用器选择扩展符号或左移符号。每对中第二乘法器输出端的多路复用器选择产品，右移产品或通过输入。第二乘法器的符号扩展电路跟随多路复用器。第三加法器接收第二加法器的和输出并产生第三和输出。这些第三加法器在其输出端包括多个可选输出累加器和可变右移位器。第三加法器可以分别将乘积和乘以四个乘法器。或者，第三加法器可以累积八个乘法器的乘积。

34. 发明授权

US06252911B1 Trellis shaping for PCM modems 失效
标题翻译：用于PCM调制解调器的网格整形
公开(公告)号：US06252911B1
公开(公告)日：2001-06-26
申请号：US09096062
申请日：1998-06-11
申请人： Alan Gatherer , Murtaza Ali
发明人： Alan Gatherer , Murtaza Ali
IPC分类号： H04L512
CPC分类号： H04L25/4927
摘要： A trellis shaping method is described that may be used for suppressing DC components and/or Nyquist frequency components from the outputs of a PCM (56K) modem. The technique is based on convolutional codes. The code is generated through the use of a Viterbi decoder. Data bits are mapped for transmission into a set of n magnitudes and (n−k) sign bits s. The sign bits s are passed through (HT)−1 to get preliminary sing bits t=s (HT)−1 of size n. (HT)−1 is a matrix of size (n−k) by n which represents the left inverse of the syndrome-former matrix HT of convolutional code c=b G, defined so that G HT=0. The convolutional code is then added to sign bits t through an XOR operation to give final sign bits s (HT)−1+b G. After transmission, the final sign bits are passed through HT to give an output of (s (HT)−1+b G) (HT))=s, for recovery of the data bits.
摘要翻译：描述了可用于从PCM（56K）调制解调器的输出抑制DC分量和/或奈奎斯特频率分量的网格整形方法。该技术基于卷积码。该代码通过使用维特比解码器生成。映射数据位以传输到一组n个幅度和（n-k）个符号位。符号位通过（HT）-1，以获得大小为n的初步字位t = s（HT）-1。（HT）-1是大小（n-k）乘以n的矩阵，其表示卷积码c = b G的综合征 - 形成矩阵HT的左倒数，使得G HT = 0。然后通过XOR操作将卷积码添加到符号位t，以得到最终符号位s（HT）-1 + b G。传输后，最终符号位通过HT，输出（s（HT） -1 + b G）（HT））= s，用于恢复数据位。

35. 发明授权

US5889691A Apparatus and method for a multiplier unit with high component utilization 失效
标题翻译：具有高组件利用率的乘法器单元的装置和方法
公开(公告)号：US5889691A
公开(公告)日：1999-03-30
申请号：US782001
申请日：1997-01-06
申请人： Alan Gatherer , Carl E. Lemonds
发明人： Alan Gatherer , Carl E. Lemonds
IPC分类号： G06F7/52
CPC分类号： G06F7/5272
摘要： In a multiplier unit having a preprocessor stage, a multiplier stage, and a summation stage, the multiplier stage includes a shift register, a gate component for controllably transmitting the multiplicand A in a manner determined by a bit signal of multiplier B applied to the gate component control terminal. Partial products are grouped by multiplicand digits and each digit is applied, through delay components determined by the order of the digit, to first terminals of an associated adder components. Output signals from each adder component is transmitted through a plurality of delay components and applied to second input terminals of the same adder component. In this manner, partial products A.sub.p *B.sub.q are assembled and the partial products (A.sub.0 + . . . A.sub.M)*B.sub.q =A*B.sub.q can be applied to the summation unit in a single period. When the multiplier is an integer multiple of the multiplicand, the implementation is particularly convenient.
摘要翻译：在具有预处理器级，乘法器级和求和级的乘法器单元中，乘法器级包括移位寄存器，用于以由施加到门的乘法器B的位信号确定的方式可控地发送被乘数A的门分量组件控制终端。部分产品按被乘数分组，每个数字通过由数字顺序确定的延迟分量应用于相关加法器分量的第一个终端。来自每个加法器分量的输出信号通过多个延迟分量传输并被施加到相同加法器分量的第二输入端。以这种方式，部分乘积Ap * Bq被组装，并且部分乘积（A0 +。。AM）* Bq = A * Bq可以在单个周期内应用于求和单元。当乘数是被乘数的整数倍时，实现特别方便。

36. 发明授权

US5461640A Method and system for optimizing an equalizer in a data transmission system 失效
标题翻译：用于优化数据传输系统中的均衡器的方法和系统
公开(公告)号：US5461640A
公开(公告)日：1995-10-24
申请号：US253471
申请日：1994-06-03
申请人： Alan Gatherer
发明人： Alan Gatherer
IPC分类号： H04L25/03 , H03H7/30
CPC分类号： H04L25/03133
摘要： The present invention includes an optimized equalizer (22) used to equalize a signal (at 20) received from a distorting channel (18). First, auto and cross correlations of a predetermined training sequence and the received signal are generated (at 21c). The correlations are then used to generate a solution matrix (21d). An eigenvector associated with a maximum eigenvalue of a function of the correlations is formed (21e) using the solution matrix (21d) and then used to generate equalizer control signals (21f) or parameters defining taps of a filter implementing the equalizer (22).
摘要翻译：本发明包括用于均衡从失真信道（18）接收的信号（在20）的优化均衡器（22）。首先，生成预定训练序列与接收信号的自相关和交叉相关（21c）。然后使用相关性来生成解矩阵（21d）。使用解矩阵（21d）形成与相关函数的最大特征值相关联的特征向量（21e），然后用于产生均衡器控制信号（21f）或定义实现均衡器（22）的滤波器的抽头的参数。

37. 发明授权

US08396058B2 Media packet networking appliance sending diversity packets to second proxy 有权
标题翻译：媒体分组网络设备向第二代理发送分集数据包
公开(公告)号：US08396058B2
公开(公告)日：2013-03-12
申请号：US13101692
申请日：2011-05-05
申请人： Stephen J. Perkins , Alan Gatherer , Krishnasamy Anandakumar , Alan V. McCree , Vishu Viswanathan
发明人： Stephen J. Perkins , Alan Gatherer , Krishnasamy Anandakumar , Alan V. McCree , Vishu Viswanathan
IPC分类号： H04L12/66
CPC分类号： H04L41/08 , H04L29/06027 , H04L41/0206 , H04L41/024 , H04L41/12 , H04L45/00 , H04L45/24 , H04L45/56 , H04L47/2416 , H04L65/105 , H04L65/4076 , H04L65/602 , H04L65/605 , H04L65/80 , H04L67/14 , H04L69/40 , H04W28/04 , H04W40/02 , H04W40/20 , H04W40/246 , H04W84/042 , H04W88/08 , H04W88/14 , H04W88/16
摘要： In one form of the invention, a process of sending real-time information from a sender computer (103) to a receiver computer (105) coupled to the sender computer (103) by a packet network (100) wherein packets (111,113) sometimes become lost, includes steps of directing (441) packets (111) containing the real-time information from the sender computer (103) by at least one path (119) in the packet network (100) to the receiver computer (105), and directing packets (113) containing information dependent on the real-time information from the sender computer (103) by at least one path diversity path (117) in the packet network (100) to the same receiver computer (105). Other forms of the invention encompass other processes, improved packets and packet ensembles (111,113), integrated circuits (610), chipsets (DSP 1721, MCU), computer cards (1651), information storage articles (1511,1611), systems, computers (103,105), gateways (191,193), routers (131,133), cellular telephone handsets (181,189), wireless base stations (183,187), appliances (1721,1731,1741), and packet networks (100), and other forms as disclosed and claimed.
摘要翻译：在本发明的一种形式中，发送计算机（103）将实时信息发送到分组网络（100）耦合到发送方计算机（103）的接收机（105）的过程，其中分组（111,113）有时包括将包含来自发送者计算机（103）的实时信息的分组（441）通过分组网络（100）中的至少一个路径（119）引导到接收机计算机（105）的步骤，以及将分组网络（100）中的至少一个路径分集路径（117）包含取决于来自发送者计算机（103）的实时信息的信息的分组（113）导向到同一接收机计算机（105）。本发明的其他形式包括其他过程，改进的分组和分组集合（111,113），集成电路（610），芯片组（DSP1721，MCU），计算机卡（1651），信息存储产品（1511,1611），系统，计算机（103,105），网关（191,193），路由器（131,133），蜂窝电话手机（181,189），无线基站（183,187），设备（1721,1731,1741）和分组网络（100）声称。

38. 发明申请

US20110211573A1 INTEGRATED CIRCUITS, SYSTEMS, APPARATUS, PACKETS AND PROCESSES UTILIZING PATH DIVERSITY FOR MEDIA OVER PACKET APPLICATIONS 有权
标题翻译：集成电路，系统，设备，分组和处理使用分组应用程序中的媒体路径多样性
公开(公告)号：US20110211573A1
公开(公告)日：2011-09-01
申请号：US13101692
申请日：2011-05-05
申请人： Stephen J. Perkins , Alan Gatherer , Krishanasamy Anandakumar , Alan V. McCree , Vishu Viswanathan
发明人： Stephen J. Perkins , Alan Gatherer , Krishanasamy Anandakumar , Alan V. McCree , Vishu Viswanathan
IPC分类号： H04L12/66
CPC分类号： H04L41/08 , H04L29/06027 , H04L41/0206 , H04L41/024 , H04L41/12 , H04L45/00 , H04L45/24 , H04L45/56 , H04L47/2416 , H04L65/105 , H04L65/4076 , H04L65/602 , H04L65/605 , H04L65/80 , H04L67/14 , H04L69/40 , H04W28/04 , H04W40/02 , H04W40/20 , H04W40/246 , H04W84/042 , H04W88/08 , H04W88/14 , H04W88/16
摘要： In one form of the invention, a process of sending real-time information from a sender computer (103) to a receiver computer (105) coupled to the sender computer (103) by a packet network (100) wherein packets (111,113) sometimes become lost, includes steps of directing (441) packets (111) containing the real-time information from the sender computer (103) by at least one path (119) in the packet network (100) to the receiver computer (105), and directing packets (113) containing information dependent on the real-time information from the sender computer (103) by at least one path diversity path (117) in the packet network (100) to the same receiver computer (105). Other forms of the invention encompass other processes, improved packets and packet ensembles (111,113), integrated circuits (610), chipsets (DSP 1721, MCU), computer cards (1651), information storage articles (1511,1611), systems, computers (103,105), gateways (191,193), routers (131,133), cellular telephone handsets (181,189), wireless base stations (183,187), appliances (1721,1731,1741), and packet networks (100), and other forms as disclosed and claimed.
摘要翻译：在本发明的一种形式中，发送计算机（103）将实时信息发送到分组网络（100）耦合到发送方计算机（103）的接收机（105）的过程，其中分组（111,113）有时包括将包含来自发送者计算机（103）的实时信息的分组（441）通过分组网络（100）中的至少一个路径（119）引导到接收机计算机（105）的步骤，以及将分组网络（100）中的至少一个路径分集路径（117）包含取决于来自发送者计算机（103）的实时信息的信息的分组（113）导向到同一接收机计算机（105）。本发明的其他形式包括其他过程，改进的分组和分组集合（111,113），集成电路（610），芯片组（DSP1721，MCU），计算机卡（1651），信息存储产品（1511,1611），系统，计算机（103,105），网关（191,193），路由器（131,133），蜂窝电话手机（181,189），无线基站（183,187），设备（1721,1731,1741）和分组网络（100）声称。

39. 发明授权

US07693062B2 Sending real-time and dependent information over separate network paths 有权
标题翻译：通过单独的网络路径发送实时和相关信息
公开(公告)号：US07693062B2
公开(公告)日：2010-04-06
申请号：US11175411
申请日：2005-07-06
申请人： Stephen J. Perkins , Alan Gatherer , Krishanasamy Anandakumar , Alan V. McCree , Vishu Viswanathan
发明人： Stephen J. Perkins , Alan Gatherer , Krishanasamy Anandakumar , Alan V. McCree , Vishu Viswanathan
IPC分类号： G01R31/08 , G06F11/00 , G08C15/00 , H04J1/16 , H04J3/14 , H04L1/00 , H04L12/26
CPC分类号： H04L41/08 , H04L29/06027 , H04L41/0206 , H04L41/024 , H04L41/12 , H04L45/00 , H04L45/24 , H04L45/56 , H04L47/2416 , H04L65/105 , H04L65/4076 , H04L65/602 , H04L65/605 , H04L65/80 , H04L67/14 , H04L69/40 , H04W28/04 , H04W40/02 , H04W40/20 , H04W40/246 , H04W84/042 , H04W88/08 , H04W88/14 , H04W88/16
摘要： In one form of the invention, a process of sending real-time information from a sender computer (103) to a receiver computer (105) coupled to the sender computer (103) by a packet network (100) wherein packets (111,113) sometimes become lost, includes steps of directing (441) packets (111) containing the real-time information from the sender computer (103) by at least one path (119) in the packet network (100) to the receiver computer (105), and directing packets (113) containing information dependent on the real-time information from the sender computer (103) by at least one path diversity path (117) in the packet network (100) to the same receiver computer (105). Other forms of the invention encompass other processes, improved packets and packet ensembles (111,113), integrated circuits (610), chipsets (DSP 1721, MCU), computer cards (1651), information storage articles (1511,1611), systems, computers (103,105), gateways (191,193), routers (131,133), cellular telephone handsets (181,189), wireless base stations (183,187), appliances (1721,1731,1741), and packet networks (100), and other forms as disclosed and claimed.
摘要翻译：在本发明的一种形式中，发送计算机（103）将实时信息发送到分组网络（100）耦合到发送方计算机（103）的接收机（105）的过程，其中分组（111,113）有时包括将包含来自发送者计算机（103）的实时信息的分组（441）通过分组网络（100）中的至少一个路径（119）引导到接收机计算机（105）的步骤，以及将分组网络（100）中的至少一个路径分集路径（117）包含取决于来自发送者计算机（103）的实时信息的信息的分组（113）导向到同一接收机计算机（105）。本发明的其他形式包括其他过程，改进的分组和分组集合（111,113），集成电路（610），芯片组（DSP1721，MCU），计算机卡（1651），信息存储产品（1511,1611），系统，计算机（103,105），网关（191,193），路由器（131,133），蜂窝电话手机（181,189），无线基站（183,187），设备（1721,1731,1741）和分组网络（100）声称。

40. 发明授权

US07400608B2 Method and apparatus for spread spectrum interference cancellation 有权
标题翻译：扩频干扰消除的方法和装置
公开(公告)号：US07400608B2
公开(公告)日：2008-07-15
申请号：US11032985
申请日：2005-01-11
申请人： Aris Papasakellariou , Alan Gatherer
发明人： Aris Papasakellariou , Alan Gatherer
IPC分类号： H04B1/00
CPC分类号： H04B1/7107
摘要： The interference cancellation (IC) system (500) includes a plurality of IC units, for which IC is applied. Each IC unit has its spread spectrum code generator, delay devices, correlators or matched filters (MF), spreading circuits and subtracting and adding devices. The IC process in accordance with the invention includes using a bank of MF to despread the received signal at every time instant corresponding to every identified multipath of every user's transmitted signal. Based on the despread signals, an initial decision for the present information symbol of every user can be made using a single-user receiver such as, for example, the conventional Rake receiver or an equalizer. Based on the initial decisions, IC regenerates the multipath signals for each user using timed versions of the spread spectrum code, the delays of the multipaths, and the corresponding channel medium estimates. By adding the regenerated signal estimates for the multipaths of all users, an estimate of the received signal at the input of the receiver prior to despreading can be reconstructed. Each IC unit despreads the regenerated received signal using timed versions of the corresponding spread spectrum code for each multipath delay. The result is subsequently subtracted from the initial despread signal and, to avoid removing the desired user path component, the reconstructed, interference-free, desired despread signal path is also added. The above IC process may be repeated several times (e.g., using several IC stages). Performing interference cancellation after despreading the regenerated estimate of the received signal leads to substantially smaller complexity than the prior art approach where the interference cancellation occurs prior to dispreading.
摘要翻译：干扰消除（IC）系统（500）包括应用IC的多个IC单元。每个IC单元具有其扩频码发生器，延迟器件，相关器或匹配滤波器（MF），扩展电路以及减法和加法器件。根据本发明的IC过程包括使用一组MF来在对应于每个用户发送的信号的每个所识别的多路径的每个时刻解扩展所接收的信号。基于解扩信号，可以使用例如常规Rake接收机或均衡器的单用户接收机来对每个用户的当前信息符号进行初始判定。基于初始决定，IC使用扩展频谱码的定时版本，多路径的延迟以及相应的信道介质估计来为每个用户再生多径信号。通过添加所有用户的多路径的再生信号估计，可以重构在解扩之前在接收机的输入处的接收信号的估计。每个IC单元使用用于每个多径延迟的相应扩频码的定时版本对再生的接收信号进行解扩。随后从初始解扩展信号中减去结果，为了避免去除所需的用户路径分量，也添加了重建的，无干扰的期望解扩信号路径。上述IC过程可以重复几次（例如，使用几个IC级）。在解扩接收信号的再生估计之后执行干扰消除导致比在分散之前发生干扰消除的现有技术方法显着更小的复杂度。

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