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31. 发明申请

US20060006888A1 Electrochemically fabricated microprobes 审中-公开
标题翻译：电化学制造的微型纺织品
公开(公告)号：US20060006888A1
公开(公告)日：2006-01-12
申请号：US10949738
申请日：2004-09-24
申请人： Ezekiel Kruglick , Christopher Bang , Vacit Arat , Adam Cohen , Dennis Smalley , Kieun Kim , Richard Chen , Gang Zhang
发明人： Ezekiel Kruglick , Christopher Bang , Vacit Arat , Adam Cohen , Dennis Smalley , Kieun Kim , Richard Chen , Gang Zhang
IPC分类号： G01R31/02
CPC分类号： G01R1/06716 , G01R1/0483 , G01R1/06733 , G01R1/06744 , G01R1/07357 , G01R31/2886
摘要： Multilayer probe structures for testing semiconductor die are electrochemically fabricated via depositions of one or more materials in a plurality of overlaying and adhered layers. In some embodiments the structures may include generally helical shaped configurations, helical shape configurations with narrowing radius as the probe extends outward from a substrate, bellows-like configurations, and the like. In some embodiments arrays of multiple probes are provided.
摘要翻译：用于测试半导体管芯的多层探针结构通过多个覆盖层和粘附层中的一种或多种材料的沉积进行电化学制造。在一些实施例中，结构可以包括大致螺旋形构造，当探针从衬底向外延伸，波纹管状构造等时具有窄半径的螺旋形构造。在一些实施例中，提供了多个探针的阵列。

32. 发明申请

US20050202180A1 Electrochemical fabrication methods for producing multilayer structures including the use of diamond machining in the planarization of deposits of material 审中-公开
标题翻译：用于生产多层结构的电化学制造方法，包括在平坦化材料沉积中使用金刚石加工
公开(公告)号：US20050202180A1
公开(公告)日：2005-09-15
申请号：US11029165
申请日：2005-01-03
申请人： Adam Cohen , Uri Frodis , Michael Lockard , Ananda Kumar , Gang Zhang , Dennis Smalley
发明人： Adam Cohen , Uri Frodis , Michael Lockard , Ananda Kumar , Gang Zhang , Dennis Smalley
IPC分类号： B05D1/38 , C08K3/00 , C25D3/30 , C25D3/38 , C25D3/48 , C25D5/02 , C25D5/10 , C25D21/12 , H01L21/288 , H01L21/301 , H01L21/302 , H01L21/4763 , H01L21/768
CPC分类号： C25D5/48 , B33Y10/00 , B81C1/00492 , B81C99/0065 , B81C2201/0104 , B81C2201/0197 , C25D1/00 , C25D1/003 , C25D5/022 , C25D5/10 , C25D21/12 , H01L21/2885 , H01L21/76885 , Y10T156/1052
摘要： Electrochemical fabrication methods for forming single and multilayer mesoscale and microscale structures are disclosed which include the use of diamond machining (e.g. fly cutting or turning) to planarize layers. Some embodiments focus on systems of sacrificial and structural materials which are useful in Electrochemical fabrication and which can be diamond machined with minimal tool wear (e.g. Ni—P and Cu, Au and Cu, Cu and Sn, Au and Cu, Au and Sn, and Au and Sn—Pb), where the first material or materials are the structural materials and the second is the sacrificial material). Some embodiments focus on methods for reducing tool wear when using diamond machining to planarize structures being electrochemically fabricated using difficult-to-machine materials (e.g. by depositing difficult to machine material selectively and potentially with little excess plating thickness, and/or pre-machining depositions to within a small increment of desired surface level (e.g. using lapping or a rough cutting operation) and then using diamond fly cutting to complete he process, and/or forming structures or portions of structures from thin walled regions of hard-to-machine material as opposed to wide solid regions of structural material.
摘要翻译：公开了用于形成单层和多层中尺度和微结构的电化学制造方法，其包括使用金刚石加工（例如飞切或车削）来平坦化层。一些实施例集中于可用于电化学制造的牺牲和结构材料的系统，并且可以以最小的工具磨损（例如Ni-P和Cu，Au和Cu，Cu和Sn，Au和Cu，Au和Sn，和Au和Sn-Pb），其中第一材料或材料是结构材料，第二材料是牺牲材料）。一些实施例着重于在使用金刚石加工以平面化使用难以加工的材料进行电化学制造的结构（例如，通过沉积难以机械材料选择性且潜在地具有少量多余电镀厚度和/或预加工沉积到所需表面水平的小增量（例如使用研磨或粗切割操作），然后使用金刚石飞切切割来完成其加工，和/或从硬质材料的薄壁区域形成结构或部分结构而不是结构材料的宽固体区域。

33. 发明申请

US20050142739A1 Probe arrays and method for making 审中-公开
标题翻译：探针阵列和制作方法
公开(公告)号：US20050142739A1
公开(公告)日：2005-06-30
申请号：US11028958
申请日：2005-01-03
申请人： Ananda Kumar , Ezekiel Kruglick , Adam Cohen , Kieun Kim , Gang Zhang
发明人： Ananda Kumar , Ezekiel Kruglick , Adam Cohen , Kieun Kim , Gang Zhang
IPC分类号： H01L21/8242
CPC分类号： G01R3/00 , G01R1/06738 , G01R1/07378
摘要： Embodiments of invention are directed to the formation of microprobes (i.e. compliant electrical or electronic contact elements) on a temporary substrate, dicing individual probe arrays, and then transferring the arrays to space transformers or other permanent substrates.
摘要翻译：本发明的实施例涉及在临时衬底上形成微探针（即柔性电气或电子接触元件），切割单独的探针阵列，然后将阵列转移到空间变压器或其它永久衬底。

34. 发明申请

US20180090509A1 SEMICONDUCTOR MEMORY DEVICES 审中-公开
公开(公告)号：US20180090509A1
公开(公告)日：2018-03-29
申请号：US15822586
申请日：2017-11-27
申请人： Gang Zhang , Hyuk KIM , Yong-Hyun KWON , Sangwuk PARK
发明人： Gang Zhang , Hyuk KIM , Yong-Hyun KWON , Sangwuk PARK
IPC分类号： H01L27/092 , H01L27/12 , H01L23/522 , H01L27/118
CPC分类号： H01L27/11573 , H01L23/5226 , H01L27/0925 , H01L27/1157 , H01L27/11575 , H01L27/11582 , H01L27/1207 , H01L2027/11861 , H01L2924/1438
摘要： Provided is a semiconductor memory device. The semiconductor memory device includes a peripheral circuit gate pattern on a first substrate, an impurity region in the first substrate and spaced apart from the peripheral circuit gate pattern, a cell array structure on the peripheral circuit gate pattern, a second substrate between the peripheral circuit gate pattern and the cell array structure, and a via that is in contact with the impurity region and disposed between the first substrate and the second substrate. The via electrically connects the first and second substrates to each other.

35. 发明申请

US20160071855A1 Semiconductor Device 审中-公开
标题翻译：半导体器件
公开(公告)号：US20160071855A1
公开(公告)日：2016-03-10
申请号：US14841328
申请日：2015-08-31
申请人： Sang Wuk Park , Hyuk Kim , Kyoung Sub Shin , Gang Zhang
发明人： Sang Wuk Park , Hyuk Kim , Kyoung Sub Shin , Gang Zhang
IPC分类号： H01L27/115
CPC分类号： H01L27/11582 , H01L27/11524 , H01L27/11556 , H01L27/1157
摘要： A semiconductor device includes gate stacks disposed on a substrate and spaced apart from each other in a first direction, with a separation region interposed between the gate stacks; channel regions penetrating through the gate stacks and disposed within each of the gate stacks; and a guide region adjacent to the separation region, penetrating through at least a portion of the gate stack, and having a bent portion that is bent toward the separation region.
摘要翻译：半导体器件包括设置在衬底上并且在第一方向上彼此间隔开的栅极叠层，隔离区域插入在栅极堆叠之间; 沟道区域穿过栅极堆叠并设置在每个栅极堆叠内; 以及与所述分离区域相邻的引导区域，穿过所述栅极堆叠的至少一部分，并且具有朝向所述分离区域弯曲的弯曲部分。

36. 发明授权

US09153705B2 Vertical memory devices and methods of manufacturing the same 有权
标题翻译：垂直存储器件及其制造方法
公开(公告)号：US09153705B2
公开(公告)日：2015-10-06
申请号：US14187548
申请日：2014-02-24
申请人： Gang Zhang , Kyoung-Sub Shin
发明人： Gang Zhang , Kyoung-Sub Shin
IPC分类号： H01L27/115 , H01L29/792 , H01L29/78 , H01L27/105 , H01L27/24 , H01L29/66
CPC分类号： H01L29/792 , H01L27/1052 , H01L27/11575 , H01L27/11578 , H01L27/11582 , H01L27/2481 , H01L29/66833 , H01L29/7827 , H01L29/7926
摘要： A memory device includes a plurality of channels, a plurality of first charge storage sites coupled to first sides of respective ones of the channels, and a plurality of second charge storage sites coupled to second sides of respective ones of the channels. The first charge storage sites correspond to first memory cells and the second charge storage sites coupled to second memory cells. At least one of the channels is a dummy channel not connected to a bit line, and a blocking layer is contiguously formed around the first and second charge storage sites and the channels.
摘要翻译：存储器件包括多个通道，耦合到相应通道的第一侧的多个第一电荷存储位置以及耦合到相应通道的第二侧的多个第二电荷存储位置。第一电荷存储位置对应于第一存储器单元和耦合到第二存储器单元的第二电荷存储位置。通道中的至少一个是不连接到位线的虚拟通道，并且阻挡层围绕第一和第二电荷存储位置和通道连续地形成。

37. 发明授权

US08553827B2 ADC-based mixed-mode digital phase-locked loop 失效
标题翻译：基于ADC的混合模式数字锁相环
公开(公告)号：US08553827B2
公开(公告)日：2013-10-08
申请号：US12582661
申请日：2009-10-20
申请人： Gang Zhang
发明人： Gang Zhang
IPC分类号： H03D3/24
CPC分类号： H03L7/1072 , H03L7/093 , H03L7/1976
摘要： A Phase-Locked Loop (PLL) includes a Phase-to-Digital Converter (PDC), a programmable digital loop filter, a Digitally-Controlled Oscillator (DCO), and a loop divider. Within the PDC, phase information is converted into a stream of digital values by a charge pump and an Analog-to-Digital Converter (ADC). The stream of digital values is supplied to the digital loop filter which in turn supplies digital tuning words to the DCO. A number of types of ADCs can be used for the ADC including a continuous-time delta-sigma oversampling Digital ADC and a Successive Approximation ADC. The voltage signal on the charge pump output is a small amplitude midrange voltage signal. The small voltage amplitude of the signal leads to numerous advantages including improved charge pump linearity, reduced charge pump noise, and lower supply voltage operation of the overall PLL.
摘要翻译：锁相环（PLL）包括一个相位数转换器（PDC），一个可编程数字环路滤波器，一个数字控制振荡器（DCO）和一个环路分频器。在PDC中，相位信息由电荷泵和模数转换器（ADC）转换成数字值流。数字值流被提供给数字环路滤波器，数字环路滤波器又向DCO提供数字调谐字。 ADC可以使用多种类型的ADC，包括连续时间Δ-sigma过采样数字ADC和逐次逼近ADC。电荷泵输出上的电压信号是一个小幅度的中频电压信号。信号的小电压幅度导致许多优点，包括改善电荷泵线性度，降低电荷泵噪声，以及整个PLL的较低电源电压操作。

38. 发明授权

US07878385B2 Probe arrays and method for making 有权
标题翻译：探针阵列和制作方法
公开(公告)号：US07878385B2
公开(公告)日：2011-02-01
申请号：US11929539
申请日：2007-10-30
申请人： Ananda H. Kumar , Ezekiel J. J. Kruglick , Adam L. Cohen , Kieun Kim , Gang Zhang , Richard T. Chen , Christopher A. Bang , Vacit Arat , Michael S. Lockard , Uri Frodis , Pavel B. Lembrikov , Jeffrey A. Thompson
发明人： Ananda H. Kumar , Ezekiel J. J. Kruglick , Adam L. Cohen , Kieun Kim , Gang Zhang , Richard T. Chen , Christopher A. Bang , Vacit Arat , Michael S. Lockard , Uri Frodis , Pavel B. Lembrikov , Jeffrey A. Thompson
IPC分类号： B23K31/02
CPC分类号： B23K35/0222 , C23C18/1605 , C23C18/1651 , C25D1/003 , C25D1/12 , G01R1/06744 , G01R1/07307 , G01R1/07314 , G01R3/00 , H01L21/6835 , H01L24/11 , H01L24/12 , H01L24/16 , H01L24/81 , H01L24/95 , H01L2221/68313 , H01L2221/68354 , H01L2221/68363 , H01L2224/0401 , H01L2224/05568 , H01L2224/10126 , H01L2224/1147 , H01L2224/11831 , H01L2224/1184 , H01L2224/1191 , H01L2224/13017 , H01L2224/13018 , H01L2224/13076 , H01L2224/131 , H01L2224/1403 , H01L2224/81001 , H01L2224/81054 , H01L2224/81136 , H01L2224/8121 , H01L2224/8181 , H01L2224/81815 , H01L2924/00013 , H01L2924/0002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/0102 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01045 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/01327 , H01L2924/014 , H01L2924/09701 , H01L2924/10253 , H01L2924/14 , H01L2924/1461 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H01L2924/3651 , H01L2924/3841 , H01L2224/13099 , H01L2224/29099 , H01L2924/00 , H01L2224/05552 , H01L2924/00012
摘要： Embodiments of invention are directed to the formation of microprobes (i.e. compliant electrical or electronic contact elements) on a temporary substrate, dicing individual probe arrays, and then transferring the arrays to space transformers or other permanent substrates. Some embodiments of the invention transfer probes to permanent substrates prior to separating the probes from a temporary substrate on which the probes were formed while other embodiments do the opposite. Some embodiments, remove sacrificial material prior to transfer while other embodiments remove sacrificial material after transfer. Some embodiments are directed to the bonding of first and second electric components together using one or more solder bumps with enhanced aspect ratios (i.e. height to width ratios) obtained as a result of surrounding the bumps at least in part with rings of a retention material. The retention material may act be a solder mask material.
摘要翻译：本发明的实施例涉及在临时衬底上形成微探针（即柔性电气或电子接触元件），切割单独的探针阵列，然后将阵列转移到空间变压器或其它永久衬底。在将探针从其上形成探针的临时基底分离出来之前，本发明的一些实施方案将探针转移到永久性基底上，而其他实施方案相反。一些实施例，在转移之前去除牺牲材料，而其它实施例在转移后去除牺牲材料。一些实施例涉及使用一个或多个具有增强的纵横比（即，高度与宽度比）的焊料凸块来将第一和第二电气部件接合在一起，这是由于至少部分地由保持材料的环围绕凸块而得到的。保留材料可以用作焊接掩模材料。

39. 发明授权

US07864915B2 Low-power asynchronous counter and method 有权
标题翻译：低功耗异步计数器和方法
公开(公告)号：US07864915B2
公开(公告)日：2011-01-04
申请号：US12247970
申请日：2008-10-08
申请人： Gang Zhang
发明人： Gang Zhang
IPC分类号： H03K23/50
CPC分类号： H03L7/183 , H03K21/12 , H03L2207/50
摘要： Design techniques for a low-power asynchronous counter. In an exemplary embodiment, the clock inputs and signal outputs of a plurality of flip-flops are serially concatenated to implement an asynchronous counting mechanism. The signal outputs of the plurality of flip-flops are sampled by successively delayed versions of a reference signal. Further design techniques for generating successively delayed versions of the reference signal are disclosed. In an exemplary embodiment, the asynchronous counting techniques may be utilized in a high-speed counter for a digital-phase locked loop (DPLL).
摘要翻译：低功耗异步计数器的设计技术。在示例性实施例中，多个触发器的时钟输入和信号输出串联连接以实现异步计数机制。多个触发器的信号输出通过参考信号的连续延迟版本进行采样。公开了用于产生参考信号的连续延迟版本的进一步的设计技术。在示例性实施例中，可以在用于数字锁相环（DPLL）的高速计数器中使用异步计数技术。

40. 发明申请

US20100314258A1 Electrochemical Fabrication Processes Incorporating Non-Platable Metals and/or Metals that are Difficult to Plate On 审中-公开
标题翻译：掺入难以镀上的不可镀金属和/或金属的电化学制造工艺
公开(公告)号：US20100314258A1
公开(公告)日：2010-12-16
申请号：US12816914
申请日：2010-06-16
申请人： Adam L. Cohen , Michael S. Lockard , Gang Zhang
发明人： Adam L. Cohen , Michael S. Lockard , Gang Zhang
IPC分类号： C25D5/00
CPC分类号： C25D5/00 , B33Y10/00 , B81C99/0095 , B81C2201/0181 , C23C4/02 , C23C18/1605 , C23C18/1651 , C23C26/00 , C23C28/021 , C23C28/023 , C23C28/028 , C25D1/003
摘要： Embodiments are directed to electrochemically fabricating multi-layer three dimensional structures where each layer comprises at least one structural and at least one sacrificial material and wherein at least some metals or alloys are electrodeposited during the formation of some layers and at least some metals are deposited during the formation of some layers that are either difficult to electrodeposit and/or are difficult to electrodeposit onto. In some embodiments, the hard to electrodeposit metals (e.g. Ti, NiTi, W, Ta, Mo, etc.) may be deposited via chemical or physical vacuum deposition techniques while other techniques are used in other embodiments. In some embodiments, prior to electrodepositing metals, the surface of the previously formed layer is made to undergo appropriate preparation for receiving an electrodeposited material. Various surface preparation techniques are possible, including, for example, anodic activation, cathodic activation, and vacuum deposition of a seed layer and possibly an adhesion layer.
摘要翻译：实施例涉及电化学制造多层三维结构，其中每层包括至少一种结构和至少一种牺牲材料，并且其中至少一些金属或合金在形成一些层期间被电沉积，并且至少一些金属在形成难以电沉积和/或难以电沉积的一些层。在一些实施方案中，可以通过化学或物理真空沉积技术沉积难以电沉积的金属（例如Ti，NiTi，W，Ta，Mo等），而在其它实施方案中使用其它技术。在一些实施方案中，在电沉积金属之前，使先前形成的层的表面经历适当的准备以接收电沉积材料。各种表面处理技术是可能的，包括例如阳极活化，阴极活化和种子层以及可能的粘附层的真空沉积。

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