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31. 发明申请

US20090289324A1 MASK OVERHANG REDUCTION OR ELIMINATION AFTER SUBSTRATE ETCH 有权
标题翻译：基板蚀刻后掩盖过度减少或消除
公开(公告)号：US20090289324A1
公开(公告)日：2009-11-26
申请号：US12467019
申请日：2009-05-15
申请人： BRIAN E. GOODLIN , THOMAS D. BONIFIELD
发明人： BRIAN E. GOODLIN , THOMAS D. BONIFIELD
IPC分类号： H01L29/06 , H01L21/02 , H01L21/768 , H01L21/762 , H01L23/48
CPC分类号： H01L29/945 , H01L21/308 , H01L21/31111 , H01L21/31116 , H01L21/76229 , H01L21/76898 , H01L27/1087 , H01L29/66181 , Y10S438/978
摘要： A method of forming IC devices includes providing a substrate and forming a patterned masking layer including at least one masked region having at least one masking layer, and a feature region bounded by the masking layer. Etching forms an etched feature in the substrate, wherein undercutting during the etching forms at least one mask overhang region over a surface portion of the etched feature that is recessed relative to an outer edge of the masking layer. A pullback etch process exclusive of any additional patterning step laterally etches the masking layer. The conditions for the pullback etch retain at least a portion of the masking layer and reduce a length of the mask overhang region by at least 50%, or eliminate the mask overhang region entirely. The etched feature is then filled after the pullback etch process to form a filled etched feature.
摘要翻译：一种形成IC器件的方法包括提供衬底并形成图案化掩模层，其包括至少一个具有至少一个掩模层的掩模区域和由掩模层限定的特征区域。蚀刻在衬底中形成蚀刻特征，其中蚀刻期间的底切形成相对于掩模层的外边缘凹陷的蚀刻特征的表面部分上的至少一个掩模悬垂区域。除了任何额外的图案化步骤之外的回拉蚀刻工艺横向蚀刻掩模层。拉回蚀刻的条件保留掩模层的至少一部分并且将掩模悬伸部分的长度减小至少50％，或者完全消除掩模悬垂区域。然后在拉回蚀刻工艺之后填充蚀刻的特征以形成填充的蚀刻特征。

32. 发明申请

US20080128837A1 Nickel Alloy Silicide Including Indium and a Method of Manufacture Therefor 有权
标题翻译：包含铟的镍合金硅化物及其制造方法
公开(公告)号：US20080128837A1
公开(公告)日：2008-06-05
申请号：US12018313
申请日：2008-01-23
申请人： Peijun J. Chen , Duofeng Yue , Amitabh Jain , Sue Crank , Thomas D. Bonifield , Homi Mogul
发明人： Peijun J. Chen , Duofeng Yue , Amitabh Jain , Sue Crank , Thomas D. Bonifield , Homi Mogul
IPC分类号： H01L29/78
CPC分类号： H01L21/28518 , H01L21/26513 , H01L21/26586 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： The invention provides a semiconductor device, a method of manufacture therefore and a method for manufacturing an integrated circuit including the same. The semiconductor device, among other elements, may include a gate structure located over a substrate, the gate structure including a gate dielectric layer and gate electrode layer. The semiconductor device may further include source/drain regions located in/over the substrate and adjacent the gate structure, and a nickel alloy silicide located in the source/drain regions, the nickel alloy silicide having an amount of indium located therein.
摘要翻译：本发明提供一种半导体器件，一种制造方法以及一种用于制造包括该半导体器件的集成电路的方法。除了其他元件之外，半导体器件可以包括位于衬底上的栅极结构，栅极结构包括栅极电介质层和栅极电极层。该半导体器件还可以包括位于衬底中或栅极结构附近的源极/漏极区域和位于源极/漏极区域中的镍合金硅化物，所述镍合金硅化物具有位于其中的铟的量。

33. 发明授权

US5444018A Metallization process for a semiconductor device 失效
标题翻译：半导体器件的金属化工艺
公开(公告)号：US5444018A
公开(公告)日：1995-08-22
申请号：US135863
申请日：1993-10-13
申请人： Dennis J. Yost , Thomas D. Bonifield , Roc Blumenthal
发明人： Dennis J. Yost , Thomas D. Bonifield , Roc Blumenthal
IPC分类号： H01L21/28 , H01L21/285 , H01L21/768 , H01L23/522 , H01L21/441
CPC分类号： H01L21/28512 , H01L21/76895 , H01L2924/0002
摘要： A contact for a semiconductor device has a via extending through a dielectric and collimated titanium in the via. Depositing titanium by collimation places sufficient metal into high aspect ratio contacts to make good electrical connection. The collimated titanium may be reacted in a nitrogen containing ambient to form a titanium silicide layer at the bottom of the contact and a titanium nitride layer over the titanium silicide layer. The titanium silicide layer provides good electrical contact to a device in a silicon semiconductor substrate and lowers contact resistance. Tungsten may be deposited over the colliminated titanium to form a conductor layer. The titanium nitride layer provides a sticking layer for the tungsten. The contact structure and the method are useful in high aspect ratio contacts present in VLSI multilevel interconnected devices such as dynamic random access memories.
摘要翻译：用于半导体器件的触点具有延伸穿过通孔中的电介质和准直钛的通孔。通过准直沉积钛将足够的金属置入高纵横比触点，以实现良好的电连接。准直的钛可以在含氮环境中反应以在接触的底部形成硅化钛层，并且在钛硅化物层上方形成氮化钛层。硅化钛层与硅半导体衬底中的器件提供良好的电接触并降低接触电阻。钨可以沉积在准直钛上以形成导体层。氮化钛层为钨提供粘附层。接触结构和方法对于存在于VLSI多级互连设备（例如动态随机存取存储器）中的高纵横比触点是有用的。

34. 发明授权

US5405807A Semiconductor hybrids and method of making same 失效
标题翻译：半导体混合物及其制备方法
公开(公告)号：US5405807A
公开(公告)日：1995-04-11
申请号：US042384
申请日：1993-03-31
申请人： James C. Baker , Emily A. Groves , Douglas Paradis , Charles P. Monaghan , Barry Lanier , Thomas D. Bonifield , Julie S. England
发明人： James C. Baker , Emily A. Groves , Douglas Paradis , Charles P. Monaghan , Barry Lanier , Thomas D. Bonifield , Julie S. England
IPC分类号： H01L21/3105 , H01L21/60
CPC分类号： H01L21/31051
摘要： A method of making a hybrid semiconductor device and the device comprising providing a semiconductor substrate having electrical devices therein, providing a first resilient layer of electrically insulating material over the substrate which can be disposed directly onto the substrate with a substantially planar exposed surface, providing a second resilient layer of electrically insulating material over the first resilient layer which can be disposed directly onto the first layer with a substantially planar exposed surface, the second layer having a relatively resilient state and a rigid state, providing resilient standoff from the third resilient layer at spaced locations on the second layer by removing predetermined portions of the third layer, securing a semiconductor superstrate to the semiconductor device, forming electrical devices on the superstrate, and then connecting the electrical devices on the superstrate to the electrical devices on the substrate.
摘要翻译：一种制造混合半导体器件的方法，所述器件包括提供其中具有电子器件的半导体衬底，在衬底上提供电绝缘材料的第一弹性层，所述第一弹性层可以直接布置在具有基本平坦的暴露表面的衬底上，从而提供所述第一弹性层上的电绝缘材料的第二弹性层可以直接布置在具有基本上平坦的暴露表面的第一层上，所述第二层具有相对弹性状态和刚性状态，从第三弹性层提供弹性支座通过去除第三层的预定部分，将半导体衬底固定到半导体器件上，在衬底上形成电器件，然后将衬底上的电子器件连接到衬底上的电气器件上，从而在第二层上的间隔位置。

35. 发明授权

US5244839A Semiconductor hybrids and method of making same 失效
标题翻译：半导体混合物及其制备方法
公开(公告)号：US5244839A
公开(公告)日：1993-09-14
申请号：US717149
申请日：1991-06-18
申请人： James C. Baker , Emily A. Groves , Douglas Paradis , Charles P. Monaghan , Barry Lanier , Thomas D. Bonifield , Julie S. England , Glenn A. Cerny
发明人： James C. Baker , Emily A. Groves , Douglas Paradis , Charles P. Monaghan , Barry Lanier , Thomas D. Bonifield , Julie S. England , Glenn A. Cerny
IPC分类号： H01L21/3105
CPC分类号： H01L21/31051
摘要： A method of making a hybrid semiconductor device and the device comprising providing a semiconductor substrate having electrical devices therein, providing a first resilient layer of electrically insulating material over the substrate which can be disposed directly onto the substrate with a substantially planar exposed surface, providing a second resilient layer of electrically insulating material over the first resilient layer which can be disposed directly onto the first layer with a substantially planar exposed surface, the second layer having a relatively resilient state and a rigid state, providing resilient standoff from the third resilient layer at spaced locations on the second layer by removing predetermined portions of the third layer, securing a semiconductor superstrate to the semiconductor device, forming electrical devices on the superstrate, and then connecting the electrical devices on the superstrate to the electrical devices on the substrate.
摘要翻译：一种制造混合半导体器件的方法，所述器件包括提供其中具有电子器件的半导体衬底，在衬底上提供电绝缘材料的第一弹性层，所述第一弹性层可以直接布置在具有基本平坦的暴露表面的衬底上，从而提供所述第一弹性层上的电绝缘材料的第二弹性层可以直接布置在具有基本上平坦的暴露表面的第一层上，所述第二层具有相对弹性状态和刚性状态，从第三弹性层提供弹性支座通过去除第三层的预定部分，将半导体衬底固定到半导体器件上，在衬底上形成电器件，然后将衬底上的电子器件连接到衬底上的电气器件上，从而在第二层上的间隔位置。

36. 发明授权

US4758305A Contact etch method 失效
标题翻译：接触蚀刻法
公开(公告)号：US4758305A
公开(公告)日：1988-07-19
申请号：US838965
申请日：1986-03-11
申请人： Thomas D. Bonifield , Vic B. Marriott , Rhett B. Jucha , Monte A. Douglas
发明人： Thomas D. Bonifield , Vic B. Marriott , Rhett B. Jucha , Monte A. Douglas
IPC分类号： H01L21/28 , H01L21/027 , H01L21/302 , H01L21/3065 , H01L21/311 , H01L21/768 , H01L21/8234 , H01L27/088 , B44C1/22 , B29C37/00 , C03C15/00 , C03C25/06
CPC分类号： H01L21/31116 , H01L21/0274 , H01L21/31144 , H01L21/76804 , Y10S438/948 , Y10S438/952
摘要： A method for patterning small-geometry contacts with sloped sidewalls in integrated circuit fabrication. A multilayer resist process is used, and the spacer layer is undercut by overexposure and overdevelopment at the pattern transfer stage. This provides a cantilever etch mask structure, without the need to use any hardmask layers.
摘要翻译：在集成电路制造中用于图形具有倾斜侧壁的小几何接触的方法。使用多层抗蚀剂工艺，并且间隔层在图案转移阶段被过度曝光和过度发展所削弱。这提供了悬臂蚀刻掩模结构，而不需要使用任何硬掩模层。

37. 发明授权

US4654112A Oxide etch 失效
标题翻译：氧化物蚀刻
公开(公告)号：US4654112A
公开(公告)日：1987-03-31
申请号：US655004
申请日：1984-09-26
申请人： Monte A. Douglas , Thomas D. Bonifield
发明人： Monte A. Douglas , Thomas D. Bonifield
IPC分类号： C03C15/00 , G03F7/36 , H01L21/311 , H01L21/768 , B44C1/22 , C03C25/06
CPC分类号： C03C15/00 , G03F7/36 , H01L21/31116 , H01L21/76804 , Y10S438/945
摘要： A new process for plasma etching silicon oxides in integrated circuit structures. A chemistry comprising both oxygen and nitrogen trifluoride is used, with oxygen the dominant component. This provides excellent selectivity to silicon. This etch chemistry also erodes photoresist rapidly, so that it is typically used in combination with a hard-masking process. One particular application of this invention is in a cantilever-etch-mask contact profiling process.
摘要翻译：集成电路结构中等离子体蚀刻氧化硅的新工艺。使用包含氧和三氟化氮的化学，其中氧是主要成分。这为硅提供了极好的选择性。该蚀刻化学品也快速地侵蚀光致抗蚀剂，因此通常与硬掩模工艺结合使用。本发明的一个具体应用是悬臂蚀刻掩模接触分析过程。

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