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31. 发明申请

US20100208504A1 Identification of data positions in magnetic packet memory storage devices, memory systems including such devices, and methods of controlling such devices 有权
标题翻译：识别磁包存储器存储设备中的数据位置，包括这种设备的存储器系统以及控制这些设备的方法
公开(公告)号：US20100208504A1
公开(公告)日：2010-08-19
申请号：US12658859
申请日：2010-02-16
申请人： Ho-jung Kim , Chul-woo Park , Sang-beom Kang , Jong-wan Kim , Hyun-ho Choi , Young-pil Kim , Sung-chul Lee
发明人： Ho-jung Kim , Chul-woo Park , Sang-beom Kang , Jong-wan Kim , Hyun-ho Choi , Young-pil Kim , Sung-chul Lee
IPC分类号： G11C19/00 , G11C7/00
CPC分类号： G11C19/0808 , G11C11/14 , G11C19/0841
摘要： In a memory device and in a method for controlling a memory device, the memory device comprises a magnetic structure that stores information in a plurality of domains of the magnetic structure. A read unit reads information from at least one of the plurality of domains of the magnetic structure by applying a read current to the magnetic structure. A position detector unit compares the information read by a read current from the read unit from multiple domains of the plurality of domains of the magnetic structure to identify the presence of an expected information pattern at select domains of the plurality of domains.
摘要翻译：在存储器装置和用于控制存储器件的方法中，存储器件包括将结构存储在磁性结构的多个域中的磁性结构。读取单元通过向磁性结构施加读取电流来从磁性结构的多个域中的至少一个域读取信息。位置检测器单元将来自读取单元的读取电流读取的信息与磁性结构的多个域的多个域进行比较，以识别多个域的选定域处的预期信息模式的存在。

32. 发明申请

US20100085826A1 Test circuit for measuring resistance distribution of Memory cells and semiconductor system including the same 有权
标题翻译：用于测量存储单元和包括其的半导体系统的电阻分布的测试电路
公开(公告)号：US20100085826A1
公开(公告)日：2010-04-08
申请号：US12588192
申请日：2009-10-07
申请人： Sang Beom Kang , Ho Jung Kim
发明人： Sang Beom Kang , Ho Jung Kim
IPC分类号： G11C7/00
CPC分类号： G11C29/50 , G11C11/16 , G11C29/50008
摘要： The test circuit for measuring a resistance distribution of memory cells includes a sensing circuit and a digital value generation circuit. The sensing circuit compares a reference voltage with a voltage of a sensing node receiving a voltage of a bit line connected with a resistive element and generates a sensing signal. The digital value generation circuit generates a digital value corresponding to a resistance-capacitance (RC) delay of the bit line in response to the sensing signal from the sensing circuit.
摘要翻译：用于测量存储单元的电阻分布的测试电路包括感测电路和数字值产生电路。感测电路将参考电压与接收与电阻元件连接的位线的电压的感测节点的电压进行比较，并产生感测信号。响应于来自感测电路的感测信号，数字值产生电路产生对应于位线的电阻 - 电容（RC）延迟的数字值。

33. 发明授权

US07586776B2 Nonvolatile memory devices having multi-filament variable resistivity memory cells therein 失效
标题翻译：在其中具有多重可变电阻率存储单元的非易失性存储器件
公开(公告)号：US07586776B2
公开(公告)日：2009-09-08
申请号：US11945420
申请日：2007-11-27
申请人： Hyung-rok Oh , Sang-beom Kang , Woo-yeong Cho
发明人： Hyung-rok Oh , Sang-beom Kang , Woo-yeong Cho
IPC分类号： G11C11/00
CPC分类号： G11C8/10 , G11C13/0007 , G11C13/0069 , G11C2013/0083 , G11C2013/0088 , G11C2013/009 , G11C2013/0092 , G11C2213/31 , G11C2213/32 , G11C2213/79
摘要： There is provided a resistive memory device, the device including: a plurality of word lines and a plurality of bit lines arranged such that the word lines intersect the bit lines; a plurality of resistive memory cells each having a variable resistive material coupled between the corresponding word line and the corresponding bit line and an access element; selecting circuits selecting one of the plurality of resistive memory cells; and a filament-forming circuit supplying a filament-forming voltage to the selected resistive memory cell through the bit line coupled to the selected resistive memory cell while increasing the filament-forming voltage from a predetermined voltage level until filaments having a predetermined thickness are formed in the variable resistive material of the selected resistive memory cell.
摘要翻译：提供了一种电阻式存储器件，该器件包括：多个字线和多个位线，其布置成使得字线与位线相交; 每个具有耦合在对应的字线和对应的位线之间的可变电阻材料的电阻性存储单元和一个存取元件; 选择所述多个电阻性存储单元之一的选择电路; 以及丝线形成电路，其通过耦合到所选择的电阻性存储单元的位线向所选择的电阻性存储单元提供丝状形成电压，同时从预定电压电平增加灯丝形成电压，直到形成具有预定厚度的灯丝所选择的电阻性存储单元的可变电阻材料。

34. 发明授权

US07542356B2 Semiconductor memory device and method for reducing cell activation during write operations 有权
标题翻译：用于在写入操作期间减少电池激活的半导体存储器件和方法
公开(公告)号：US07542356B2
公开(公告)日：2009-06-02
申请号：US11790146
申请日：2007-04-24
申请人： Kwang-Jin Lee , Sang-Beom Kang , Hyung-Rok Oh , Beak-Hyung Cho , Woo-Yeong Cho
发明人： Kwang-Jin Lee , Sang-Beom Kang , Hyung-Rok Oh , Beak-Hyung Cho , Woo-Yeong Cho
IPC分类号： G11C7/06
CPC分类号： G11C13/0069 , G11C7/06 , G11C7/1006 , G11C13/0004 , G11C2013/0076 , G11C2211/5647
摘要： Embodiments of the invention provide devices or methods that include a status bit representing an inversion of stored data. New data is written to selected cells, the new data is selectively inverted, and the status bit is selectively toggled, based on a comparison between pre-existing data and new data associated with a write command. A benefit of embodiments of the invention is that fewer memory cells must be activated in many instances (when compared to conventional art approaches). Moreover, embodiments of the invention may also reduce the average amount of activation current required to write to variable resistive memory devices and other memory device types.
摘要翻译：本发明的实施例提供了包括表示存储数据的反转的状态位的设备或方法。将新数据写入所选择的单元，根据预先存在的数据与与写命令相关联的新数据之间的比较，选择性地反转新数据并选择性地切换状态位。本发明的实施例的优点在于，在许多情况下（与传统技术方法相比），必须激活更少的存储器单元。此外，本发明的实施例还可以减少写入可变电阻存储器件和其他存储器件类型所需的平均激活电流量。

35. 发明授权

US07522449B2 Phase change memory device and related programming method 有权
标题翻译：相变存储器件及相关编程方法
公开(公告)号：US07522449B2
公开(公告)日：2009-04-21
申请号：US11790011
申请日：2007-04-23
申请人： Yu-Hwan Ro , Kwang-Jin Lee , Sang-Beom Kang , Woo-Yeong Cho
发明人： Yu-Hwan Ro , Kwang-Jin Lee , Sang-Beom Kang , Woo-Yeong Cho
IPC分类号： G11C11/00
CPC分类号： G11C13/0064 , G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C16/3486 , G11C2013/0076
摘要： In various methods of performing program operations in phase change memory devices, selected memory cells are repeatedly programmed to obtain resistance distributions having desired characteristics such as adequate sensing margins.
摘要翻译：在相变存储器件中执行程序操作的各种方法中，选择的存储器单元被重复编程以获得具有所需特性（例如足够的感测裕度）的电阻分布。

36. 发明申请

US20080175036A1 RESISTANCE RANDOM ACCESS MEMORY HAVING COMMON SOURCE LINE 有权
标题翻译：具有普通源线的电阻随机存取存储器
公开(公告)号：US20080175036A1
公开(公告)日：2008-07-24
申请号：US11964142
申请日：2007-12-26
申请人： Hyung-Rok OH , Sang-Beom KANG , Joon-Min PARK , Woo-Yeong CHO
发明人： Hyung-Rok OH , Sang-Beom KANG , Joon-Min PARK , Woo-Yeong CHO
IPC分类号： G11C11/21
CPC分类号： G11C13/0007 , G11C13/0069 , G11C2013/0071 , G11C2013/009 , G11C2213/31 , G11C2213/79
摘要： A resistance random access memory (RRAM) having a source line shared structure and an associated data access method. The RRAM, in which a write operation of writing data of first state and second state to a selected memory cell is performed through first and second write paths having mutually opposite directions, includes word lines, bit lines, a memory cell array and a plurality of source lines. The memory cell array includes a plurality of memory cells each constructed of an access transistor coupled to a resistive memory device. The memory cells are disposed in a matrix of rows and columns and located at each intersection of a word line and a bit line. Each of the plurality of source lines is disposed between a pair of word lines and in the same direction as the word lines. A positive voltage is applied to a source line in a memory cell write operation. Through the source line shared structure, occupied chip area is reduced and, in a write operating mode, a bit line potential can be determined within a positive voltage level range.
摘要翻译：具有源线共享结构的电阻随机存取存储器（RRAM）和相关联的数据存取方法。其中通过具有相互相反方向的第一和第二写入路径来执行将第一状态和第二状态的数据写入所选存储单元的写入操作，包括字线，位线，存储单元阵列和多个源线。存储单元阵列包括多个存储单元，每个存储单元由耦合到电阻存储器件的存取晶体管构成。存储单元被布置成行和列的矩阵并且位于字线和位线的每个交叉点处。多个源极线中的每一个被设置在一对字线之间并且在与字线相同的方向上。在存储单元写入操作中，将正电压施加到源极线。通过源极线共享结构，占用的芯片面积减小，并且在写入操作模式中，可以在正电压电平范围内确定位线电位。

37. 发明申请

US20080165598A1 BI-DIRECTIONAL RESISTIVE RANDOM ACCESS MEMORY CAPABLE OF MULTI-DECODING AND METHOD OF WRITING DATA THERETO 有权
标题翻译：具有多重解码能力的双向电阻随机存取存储器及其写入方法
公开(公告)号：US20080165598A1
公开(公告)日：2008-07-10
申请号：US11957812
申请日：2007-12-17
申请人： Joon-min PARK , Sang-beom KANG , Woo-yeong CHO , Hyung-rok OH
发明人： Joon-min PARK , Sang-beom KANG , Woo-yeong CHO , Hyung-rok OH
IPC分类号： G11C7/00 , G11C11/21
CPC分类号： G11C13/00 , G11C8/08 , G11C13/0028 , G11C13/0069 , G11C2013/009
摘要： A non-volatile memory device is employed in which data values are determined by the polarities at both ends of a cell, The non-volatile memory device includes a first decoder which decodes a plurality of predetermined bit values of a row address into a first address and is disposed in a row direction of a memory cell array; a second decoder which decodes the other bit values of the row address into a second address and is disposed in a column direction of the memory cell array; and a driver which applies bias voltages to a word line which corresponds to the first address or the second address in accordance with the data values. By including first and second decoders and decoding a row address in two steps, a bi-directional RRAM according to the present invention can perform addressing at high speeds while reducing chip size.
摘要翻译：使用非易失性存储器件，其中数据值由单元两端的极性确定。非易失性存储器件包括将行地址的多个预定位值解码为第一地址的第一解码器并且设置在存储单元阵列的行方向上; 第二解码器，其将所述行地址的其他位值解码为第二地址，并且被布置在所述存储单元阵列的列方向上; 以及根据数据值对与第一地址或第二地址对应的字线施加偏置电压的驱动器。通过包括第一和第二解码器并以两个步骤对行地址进行解码，根据本发明的双向RRAM可以在降低芯片尺寸的同时以高速执行寻址。

38. 发明申请

US20080112209A1 Semiconductor memory device having a three-dimensional cell array structure 有权
标题翻译：具有三维单元阵列结构的半导体存储器件
公开(公告)号：US20080112209A1
公开(公告)日：2008-05-15
申请号：US11755329
申请日：2007-05-30
申请人： Woo-Yeong Cho , Sang-Beom Kang , Du-Eung Kim
发明人： Woo-Yeong Cho , Sang-Beom Kang , Du-Eung Kim
IPC分类号： G11C11/00
CPC分类号： G11C13/0023 , G11C11/1655 , G11C11/1657 , G11C13/0004 , G11C2213/71 , G11C2213/72
摘要： A semiconductor memory device includes a plurality of cell array layers including a plurality of word lines extending in a first direction, a plurality of bit lines extending in a second direction that intersects the first direction, and a plurality of memory cells disposed at intersections of the word lines and the bit lines. Each of the word lines has a word line position, each of the bit lines has a bit line position, and each of the memory cells includes a variable resistance device in series with a diode. The cell array layers are arranged in layers in a third direction that is perpendicular to the first and second directions. The bit lines of each of the cell array layers having a same bit line position are connected to a common column selector transistor, or the word lines of the cell array layers having a same word line position are connected to a common word line driver.
摘要翻译：半导体存储器件包括多个单元阵列层，包括沿第一方向延伸的多个字线，沿与第一方向相交的第二方向延伸的多个位线，以及设置在第一方向的交点处的多个存储单元字线和位线。每个字线具有字线位置，每个位线具有位线位置，并且每个存储单元包括与二极管串联的可变电阻器件。单元阵列层在垂直于第一和第二方向的第三方向上排列成层。具有相同位线位置的每个单元阵列层的位线连接到公共列选择晶体管，或者具有相同字线位置的单元阵列层的字线连接到公共字线驱动器。

39. 发明申请

US20080013362A1 PHASE-CHANGE MEMORY DEVICE AND METHOD THAT MAINTAINS THE RESISTANCE OF A PHASE-CHANGE MATERIAL IN A SET STATE WITHIN A CONSTANT RESISTANCE RANGE 有权
标题翻译：相变存储器件和在恒定电阻范围内保持相变材料在电阻状态下的电阻的方法
公开(公告)号：US20080013362A1
公开(公告)日：2008-01-17
申请号：US11772569
申请日：2007-07-02
申请人： Byung-gil Choi , Choong-keun Kwak , Sang-beom Kang , Joon-yong Choi
发明人： Byung-gil Choi , Choong-keun Kwak , Sang-beom Kang , Joon-yong Choi
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C7/1006 , G11C13/0004 , G11C13/0069 , G11C2013/0076 , G11C2211/5647
摘要： Provided are a phase-change memory device and method that maintains a resistance of a phase-change material in a set state within a constant resistance range; In the method, data is provided to a first phase-change memory cell and then it is first determined whether data stored in the first phase-change memory cell and the data provided to the first phase-change memory cell are identical. If the data stored in the first phase-change memory cell and the data provided to the first phase-change memory cell are not identical, a complementary write current is provided to the first phase-change memory cell and it is second determined whether the data stored in the first phase-change memory cell and the data provided to the first phase-change memory cell are identical; If the data stored in the first phase-change memory cell and the data provided to the first phase-change memory cell are identical, data is provided to a second phase-change memory cell;
摘要翻译：提供一种将相变材料的电阻维持在恒定电阻范围内的相变存储器件和方法，在该方法中，将数据提供给第一相变存储器单元，然后首先确定存储在第一相变存储单元中的数据和提供给第一相变存储单元的数据是否相同。如果存储在第一相变存储单元中的数据和提供给第一相变存储单元的数据不相同，则向第一相变存储单元提供互补写入电流，并且第二相位变换存储单元是否将数据存储在第一相变存储单元中，提供给第一相变存储单元的数据相同; 如果存储在第一相变存储单元中的数据和提供给第一相变存储单元的数据相同，则将数据提供给第二相变存储单元;

40. 发明授权

US07280391B2 Phase change memory device for use in a burst read operation and a data reading method thereof 有权
标题翻译：用于突发读取操作的相变存储器件及其数据读取方法
公开(公告)号：US07280391B2
公开(公告)日：2007-10-09
申请号：US11184184
申请日：2005-07-19
申请人： Sang-Beom Kang , Woo-Yeong Cho
发明人： Sang-Beom Kang , Woo-Yeong Cho
IPC分类号： G11C11/00 , G11C7/10
CPC分类号： G11C13/0004 , G11C7/1027 , G11C13/004 , G11C2013/0054
摘要： A phase change memory device for use in a burst read operation and a data reading method are provided. The memory device includes a plurality of bit lines and a plurality of word lines. A memory cell array block has a plurality of phase change memory cells that are connected to cross points of the plurality of bit lines and the plurality of word lines. A sense amplifier block is connected to corresponding bit lines, and latches data of memory cells connected to the same word line simultaneously during a burst read operation, and then provides the latched data in response to a column address.
摘要翻译：提供了一种用于突发读取操作和数据读取方法的相变存储器件。存储器件包括多个位线和多个字线。存储单元阵列块具有连接到多个位线和多个字线的交叉点的多个相变存储单元。读出放大器块连接到对应的位线，并且在突发读取操作期间同时锁存连接到相同字线的存储器单元的数据，然后响应于列地址提供锁存的数据。

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