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31. 发明授权

US07725556B1 Computer system with concurrent direct memory access 有权
标题翻译：具有并发直接内存访问的计算机系统
公开(公告)号：US07725556B1
公开(公告)日：2010-05-25
申请号：US11553953
申请日：2006-10-27
申请人： Michael S. Schlansker , Erwin Oertli , Norm Jouppi
发明人： Michael S. Schlansker , Erwin Oertli , Norm Jouppi
IPC分类号： G06F15/167 , G06F15/173 , G06F3/00 , G06F13/00
CPC分类号： G06F13/28 , G06F13/385
摘要： A computer system with concurrent direct memory access is provided including a computer node having a processor interface bus and a cut-through network interface controller installed on the processor interface bus. A data transfer is initiated through the cut-through network interface controller by starting a direct memory access to move data from a memory to a transmit buffer in the cut-through network interface controller and a network interface controller physical interface transmitting the data, to the computer node attached to a reliable network, before all of the data is in the transmit buffer.
摘要翻译：提供具有并发直接存储器访问的计算机系统，包括具有处理器接口总线的计算机节点和安装在处理器接口总线上的直通式网络接口控制器。通过直通网络接口控制器启动数据传输，通过启动直接存储器访问来将数据从直通网络接口控制器中的存储器移动到发送缓冲器，以及将数据传输到网络接口控制器物理接口计算机节点附加到可靠的网络，所有的数据都在发送缓冲区中。

32. 发明申请

US20080162663A1 COMPUTER SYSTEM WITH NETWORK INTERFACE RETRANSMIT 有权
标题翻译：具有网络接口重新计算的计算机系统
公开(公告)号：US20080162663A1
公开(公告)日：2008-07-03
申请号：US11553970
申请日：2006-10-27
申请人： Michael S. Schlansker , Boon Ang , Erwin Oertli
发明人： Michael S. Schlansker , Boon Ang , Erwin Oertli
IPC分类号： G06F15/16
CPC分类号： G06F13/385 , H04L49/90 , H04L49/9063
摘要： A computer system is provided including a computer having a bus coupled to a computer system memory with a user buffer allocated therein. A network interface controller is coupled between the bus and a network. A retransmit buffer is coupled to the computer system memory, a transmit/receive buffer coupled to the computer system memory, and a retransmit direct memory access is within the network interface controller for moving data between the user buffer and the transmit/receive buffer, the retransmit buffer, or both as well as for moving the data to the network.
摘要翻译：提供了一种计算机系统，包括计算机，该计算机具有耦合到其中分配有用户缓冲器的计算机系统存储器的总线。网络接口控制器耦合在总线和网络之间。重发缓冲器耦合到计算机系统存储器，耦合到计算机系统存储器的发送/接收缓冲器，并且重新发送直接存储器访问在网络接口控制器内，用于在用户缓冲器和发送/接收缓冲器之间移动数据，重传缓冲区，或两者以及将数据移动到网络。

33. 发明授权

US06993639B2 Processing instruction addressed by received remote instruction and generating remote instruction to respective output port for another cell 有权
标题翻译：由接收的远程指令处理指令，并产生远程指令给另一个单元的相应输出端口
公开(公告)号：US06993639B2
公开(公告)日：2006-01-31
申请号：US10405170
申请日：2003-04-01
申请人： Michael S. Schlansker , Boon Seong Ang
发明人： Michael S. Schlansker , Boon Seong Ang
IPC分类号： G06F15/82
CPC分类号： G06F9/30058 , G06F9/3842 , G06F9/3851 , G06F9/3887 , G06F9/3889
摘要： Embodiments of the invention relate to a processing cell for use in computing systems. Generally, a processing cell generates remote instructions to be received and processed by at least one other processing cell. A processing cell may include a program counter, an instruction memory, and appropriate elements such as a branch lookup, a branch unit, etc. Alternatively, the processing cell may include a state machine that replaces the program counter and the instruction memory. Embodiments of the invention are able to support the VLIW mode, the MIMD) mode, a mixture of both modes of execution, etc.
摘要翻译：本发明的实施例涉及一种用于计算系统的处理单元。通常，处理单元产生由至少一个其他处理单元接收和处理的远程指令。处理单元可以包括程序计数器，指令存储器和诸如分支查找，分支单元等的适当元件。或者，处理单元可以包括替换程序计数器和指令存储器的状态机。本发明的实施例能够支持VLIW模式，MIMD模式，两种执行模式的混合等。

34. 发明授权

US06952816B2 Methods and apparatus for digital circuit design generation 有权
标题翻译：数字电路设计生成方法与装置
公开(公告)号：US06952816B2
公开(公告)日：2005-10-04
申请号：US10266856
申请日：2002-10-07
申请人： Shail Aditya Gupta , Anita B. Rau , Mukund Sivaraman , Darren C. Conquist , Robert S. Schreiber , Michael S. Schlansker
发明人： Bantwal Ramakrishna Rau
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A technique for synthesizing digital circuit designs by incorporating timing convergence and routability considerations. In one aspect, the invention provides a system and programmatic method for generating a circuit design from a functional specification according to at least one design objective. An intermediate representation of the functional specification is formed. The intermediate representation is analyzed for identifying a physical instantiation that will possibly result in unacceptable interconnect delay or congestion. Functional units are allocated from among a plurality of candidate functional units for performing operations of the intermediate representation. Operations are scheduled to occur at specified times on said selected functional units. An architectural representation of the circuit design is formed according to results of scheduling.
摘要翻译：一种通过引入定时收敛和可路由性考虑来合成数字电路设计的技术。一方面，本发明提供一种用于根据至少一个设计目标从功能规范生成电路设计的系统和编程方法。形成功能规范的中间表示。分析中间表示以识别可能导致不可接受的互连延迟或拥塞的物理实例化。从用于执行中间表示的操作的多个候选功能单元中分配功能单元。所述操作被安排在所述功能单元的指定时间发生。根据调度结果形成电路设计的架构表示。

35. 发明授权

US06408428B1 Automated design of processor systems using feedback from internal measurements of candidate systems 失效
标题翻译：使用候选系统内部测量的反馈自动设计处理器系统
公开(公告)号：US06408428B1
公开(公告)日：2002-06-18
申请号：US09378290
申请日：1999-08-20
申请人： Michael S. Schlansker , Vinod K. Kathail , Greg Snider , Shail Aditya Gupta , Scott A. Mahlke , Santosh Abraham
发明人： Michael S. Schlansker , Vinod K. Kathail , Greg Snider , Shail Aditya Gupta , Scott A. Mahlke , Santosh Abraham
IPC分类号： G06F1750
CPC分类号： G06F17/5045 , G06F2217/08
摘要： An automated design system for VLIW processors explores a parameterized design space to assist in identifying candidate processor designs that satisfy desired design constraints, such as processor cost and performance. A VLIW synthesis process takes as input a specification of processor parameters and synthesizes a datapath specification, an instruction format design, and a control path specification. The synthesis process also extracts a machine description suitable to re-target a compiler. The re-targeted compiler generates operation issue statistics for an application program or set of programs. Using these statistics, a procedure for searching the design space can extract internal resources utilization information that is used to determine new candidate processors for evaluation.
摘要翻译：用于VLIW处理器的自动化设计系统探索参数化设计空间，以帮助识别满足期望设计约束（例如处理器成本和性能）的候选处理器设计。 VLIW合成过程将处理器参数的规范作为输入，并合成数据路径规范，指令格式设计和控制路径规范。合成过程还提取适合于重新定位编译器的机器描述。重新定位的编译器生成应用程序或程序集的操作问题统计信息。使用这些统计信息，搜索设计空间的过程可以提取用于确定新的候选处理器进行评估的内部资源利用率信息。

36. 发明授权

US5999738A Flexible scheduling of non-speculative instructions 失效
标题翻译：灵活调度非推测性指令
公开(公告)号：US5999738A
公开(公告)日：1999-12-07
申请号：US964050
申请日：1997-11-06
申请人： Michael S. Schlansker , Vinod Kathail
发明人： Michael S. Schlansker , Vinod Kathail
IPC分类号： G06F9/45
CPC分类号： G06F8/445
摘要： A technique for flexible scheduling of a code sequence wherein a set of instructions for determining a a fully-resolved predicate for each of a set of non-speculative instructions contained in the code sequence is generated. An optimized code sequence is then generated that includes the instructions for determining the fully resolved predicates and that further includes the non-speculative instructions each guarded by one of the fully resolved predicates such that any one of the non-speculative instructions may be executed before any other of the non-speculative instructions.
摘要翻译：一种用于编码序列的灵活调度的技术，其中生成用于为包含在码序列中的一组非推测性指令中的每一个确定完全解析谓词的一组指令。然后生成优化的代码序列，其包括用于确定完全解析的谓词的指令，并且还包括每个由完全解析的谓词之一保护的非推测性指令，使得任何一个非推测性指令可以在任何其他非投机性指示。

37. 发明授权

US5778219A Method and system for propagating exception status in data registers and for detecting exceptions from speculative operations with non-speculative operations 失效
标题翻译：在数据寄存器中传播异常状态的方法和系统，以及用非投机操作检测投机操作的异常
公开(公告)号：US5778219A
公开(公告)日：1998-07-07
申请号：US597784
申请日：1996-02-07
申请人： Frederic C. Amerson , Rajiv Gupta , Vinod K. Kathail , B. Ramakrishna Rau , Michael S. Schlansker , William S. Worley, Jr.
发明人： Frederic C. Amerson , Rajiv Gupta , Vinod K. Kathail , B. Ramakrishna Rau , Michael S. Schlansker , William S. Worley, Jr.
IPC分类号： G06F9/318 , G06F9/38
CPC分类号： G06F9/3865 , G06F9/30072 , G06F9/30181 , G06F9/3842 , G06F9/3863
摘要： A method for supporting speculative execution includes designating operations as speculative or non-speculative, and then deferring exceptions generated by speculative operations while immediately reporting exceptions by non-speculative operations. If a speculative operation uses a result of a speculative operation that has generated an exception, the exception is propagated. Deferred exceptions are detected and reported using a check operation either incorporated into a non-speculative operation or inserted as a separate check operation. A system for supporting speculative execution includes a functional unit for recognizing a speculative operation and deferring any exceptions generated by such an operation. The functional unit may defer an exception by storing information indicating an error has occurred in the register file. To check for deferred exceptions, the functional unit then reads the register file. If an exception is detected, then the exception is processed and one or more of the speculative operation are re-executed (in a non-speculative mode) where necessary to process the exception.
摘要翻译：支持投机执行的方法包括将操作指定为投机或非投机性，然后推迟由投机操作产生的异常，同时立即通过非投机操作报告异常。如果推测操作使用产生异常的推测操作的结果，则会传播该异常。使用检查操作检测和报告延期异常，并将其合并到非推测操作中或作为单独检查操作插入。用于支持推测执行的系统包括用于识别投机操作并推迟由这种操作产生的任何异常的功能单元。功能单元可以通过存储指示在寄存器文件中发生错误的信息来延迟异常。要检查延迟异常，功能单元然后读取寄存器文件。如果检测到异常，则处理异常，并且在需要处理异常的情况下重新执行一个或多个推测操作（以非推测模式）。

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