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31. 发明申请

US20050067663A1 Oxide-nitride stack gate dielectric 有权
标题翻译：氧化氮化物堆叠栅极电介质
公开(公告)号：US20050067663A1
公开(公告)日：2005-03-31
申请号：US10950332
申请日：2004-09-24
申请人： Krishnaswamy Ramkumar , Sundar Narayanan
发明人： Krishnaswamy Ramkumar , Sundar Narayanan
IPC分类号： H01L21/28 , H01L21/314 , H01L29/49 , H01L29/78 , H01L21/20
CPC分类号： H01L21/022 , H01L21/0217 , H01L21/02233 , H01L21/02337 , H01L21/28044 , H01L21/3144 , H01L29/4941 , H01L29/78
摘要： A method of making a semiconductor structure comprises forming an oxide layer on a substrate; forming a silicon nitride layer on the oxide layer; annealing the layers in NO; and annealing the layers in ammonia. The equivalent oxide thickness of the oxide layer and the silicon nitride layer together is at most 25 Angstroms.
摘要翻译：制造半导体结构的方法包括在衬底上形成氧化物层; 在氧化物层上形成氮化硅层; 在NO中退火层; 并在氨中退火层。氧化物层和氮化硅层的等效氧化物厚度在一起为至多25埃。

32. 发明授权

US06841491B1 In situ deposition of a nitride layer and of an anti-reflective layer 有权
标题翻译：原位沉积氮化物层和抗反射层
公开(公告)号：US06841491B1
公开(公告)日：2005-01-11
申请号：US10039469
申请日：2001-11-08
申请人： Sharmin Sadoughi , Krishnaswamy Ramkumar
发明人： Sharmin Sadoughi , Krishnaswamy Ramkumar
IPC分类号： H01L21/027 , H01L21/318 , H01L21/31
CPC分类号： H01L21/0276 , H01L21/3185
摘要： A process for fabricating a semiconductor structure comprises depositing a nitride layer on a semiconductor substrate with a first tool, and depositing an anti-reflective layer on the semiconductor substrate with the first tool. The nitride layer includes silicon and nitrogen.
摘要翻译：一种用于制造半导体结构的工艺包括用第一工具在半导体衬底上沉积氮化物层，并在第一工具上在半导体衬底上沉积抗反射层。氮化物层包括硅和氮。

33. 发明授权

US06838392B1 Methods of forming semiconductor structures, and articles and devices formed thereby 有权
标题翻译：形成半导体结构的方法以及由此形成的制品和装置
公开(公告)号：US06838392B1
公开(公告)日：2005-01-04
申请号：US10119574
申请日：2002-04-09
申请人： Krishnaswamy Ramkumar
发明人： Krishnaswamy Ramkumar
IPC分类号： H01L21/00 , H01L21/306 , H01L21/311 , H01L21/762
CPC分类号： H01L21/02052 , H01L21/31111 , H01L21/76232
摘要： A method of forming a semiconductor structure is described that includes etching a trench in a semiconductor substrate, wherein an oxide layer overlies the semiconductor substrate, and a nitride layer overlies the oxide layer; and cleaning the semiconductor substrate while simultaneously performing a pull back of the nitride layer. Methods of making semiconductor devices and electronic devices, and silicon wafers having trenches and isolation regions formed by the above-mentioned methods are also described.

34. 发明授权

US06818558B1 Method of manufacturing a dielectric layer for a silicon-oxide-nitride-oxide-silicon (SONOS) type devices 有权
标题翻译：制造氧化硅 - 氧化物 - 氧化物 - 硅（SONOS）型器件的介质层的方法
公开(公告)号：US06818558B1
公开(公告)日：2004-11-16
申请号：US10185470
申请日：2002-06-28
申请人： Manuj Rathor , Krishnaswamy Ramkumar , Fred Jenne , Loren Lancaster
发明人： Manuj Rathor , Krishnaswamy Ramkumar , Fred Jenne , Loren Lancaster
IPC分类号： H01L21311
CPC分类号： H01L27/11568 , H01L27/115 , H01L29/42332 , H01L29/7882
摘要： A method of forming a charge storing layer is disclosed. According to an embodiment, a method may include the steps of forming a first portion of a charge storing layer with a first gas flow rate ratio (step 102), forming at least a second portion of the charge storing layer by changing to a second gas flow rate ratio that is different than the first gas flow rate ratio (step 104), and forming at least a third portion of the charge storing layer by changing to a third gas flow rate ratio that is different than the second gas flow rate ratio (step 106).
摘要翻译：公开了形成电荷存储层的方法。根据实施例，一种方法可以包括以第一气体流速比形成电荷存储层的第一部分（步骤102）的步骤，通过改变到第二气体形成电荷存储层的至少第二部分流量比与第一气体流量比不同（步骤104），并且通过改变到与第二气体流量比不同的第三气体流量比形成至少第三部分的电荷存储层（步骤106）。

35. 发明授权

US06803321B1 Nitride spacer formation 有权
标题翻译：氮化物间隔物形成
公开(公告)号：US06803321B1
公开(公告)日：2004-10-12
申请号：US10313049
申请日：2002-12-06
申请人： Alain Blosse , Krishnaswamy Ramkumar , Sundar Narayanan
发明人： Alain Blosse , Krishnaswamy Ramkumar , Sundar Narayanan
IPC分类号： H01I21302
CPC分类号： H01L21/76897 , H01L21/28247 , H01L21/31116 , H01L21/3185
摘要： A method of forming a semiconductor structure comprises forming a nitride layer on a stack, and etching the nitride layer to form spacers in contact with sides of the stack. The stack is on a semiconductor substrate, the stack comprises (i) a gate layer, comprising silicon, (ii) a metallic layer, on the gate layer, and (iii) an etch-stop layer, on the metallic layer. The forming is by CVD with a gas comprising SixL2x, L is an amino group, and X is 1 or 2.
摘要翻译：形成半导体结构的方法包括在叠层上形成氮化物层，并蚀刻氮化物层以形成与堆叠的侧面接触的间隔物。叠层在半导体衬底上，堆叠包括（i）栅极层，包括硅，（ii）栅极层上的金属层，和（iii）金属层上的蚀刻停止层。通过CVD形成气体，其中包含SixL2x的气体，L是氨基，X是1或2。

36. 发明授权

US06774452B1 Semiconductor structure having alignment marks with shallow trench isolation 失效
标题翻译：半导体结构具有浅沟槽隔离的对准标记
公开(公告)号：US06774452B1
公开(公告)日：2004-08-10
申请号：US10321965
申请日：2002-12-17
申请人： Krishnaswamy Ramkumar , Sharmin Sadoughi
发明人： Krishnaswamy Ramkumar , Sharmin Sadoughi
IPC分类号： H01L2176
CPC分类号： H01L21/76229 , H01L23/544 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure including a semiconductor substrate, an isolation trench in the semiconductor substrate, and an alignment trench in the semiconductor substrate is disclosed. The structure also includes a dielectric layer and a metallic layer. The dielectric layer is on the semiconductor substrate and in both the isolation trench and the alignment trench. The dielectric layer fills the isolation trench and does not fill the alignment trench. The metallic layer is on the dielectric layer.
摘要翻译：公开了一种包括半导体衬底，半导体衬底中的隔离沟槽和半导体衬底中的对准沟槽的半导体结构。该结构还包括电介质层和金属层。介电层位于半导体衬底上并且在隔离沟槽和对准沟槽中。电介质层填充隔离沟槽并且不填充对准沟槽。金属层位于电介质层上。

37. 发明授权

US06773975B1 Formation of a shallow trench isolation structure in integrated circuits 有权
标题翻译：在集成电路中形成浅沟槽隔离结构
公开(公告)号：US06773975B1
公开(公告)日：2004-08-10
申请号：US10326707
申请日：2002-12-20
申请人： Krishnaswamy Ramkumar , Sundar Narayanan , Shahin Sharifzadeh
发明人： Krishnaswamy Ramkumar , Sundar Narayanan , Shahin Sharifzadeh
IPC分类号： H01L218238
CPC分类号： H01L21/823481 , H01L21/76229
摘要： In one embodiment, a transistor is fabricated by forming gate materials, such as a gate oxide layer and a gate polysilicon layer, prior to forming a shallow trench isolation (STI) structure. Forming the gate materials early in the process minimizes exposure of the STI structure to processing steps that may expose its corners. Also, to minimize cross-diffusion of dopants and to help lower gate resistance, a metal stack comprising a barrier layer and a metal layer may be employed as a conductive line between gates. In one embodiment, the metal stack comprises a barrier layer of tungsten-nitride and a metal layer of tungsten.
摘要翻译：在一个实施例中，在形成浅沟槽隔离（STI）结构之前，通过形成栅极材料，例如栅极氧化物层和栅极多晶硅层来制造晶体管。在此过程早期形成栅极材料可最大限度地减少STI结构暴露其角落的处理步骤。此外，为了最小化掺杂剂的交叉扩散并有助于降低栅极电阻，可以使用包括阻挡层和金属层的金属堆叠作为栅极之间的导电线。在一个实施例中，金属堆叠包括氮化钨的阻挡层和钨的金属层。

38. 发明授权

US06680516B1 Controlled thickness gate stack 有权
标题翻译：可控厚度栅极叠层
公开(公告)号：US06680516B1
公开(公告)日：2004-01-20
申请号：US10313267
申请日：2002-12-06
申请人： Alain Blosse , Krishnaswamy Ramkumar
发明人： Alain Blosse , Krishnaswamy Ramkumar
IPC分类号： H01L2976
CPC分类号： H01L21/76897 , H01L29/42372
摘要： A semiconductor structure, comprises a semiconductor substrate, a gate layer on the semiconductor substrate, a metallic layer on the gate layer, and an etch-stop layer on the metallic layer. A distance between the substrate and a top of the etch-stop layer is a gate stack height, and the gate stack height is at most 2700 angstroms. In addition, the etch-stop layer has a thickness of at least 800 angstroms.
摘要翻译：半导体结构包括半导体衬底，半导体衬底上的栅极层，栅极层上的金属层以及金属层上的蚀刻停止层。衬底与蚀刻停止层的顶部之间的距离是栅堆叠高度，栅叠层高度至多为2700埃。此外，蚀刻停止层的厚度至少为800埃。

39. 发明授权

US09102522B2 Method of ONO integration into logic CMOS flow 有权
标题翻译： ONO集成到逻辑CMOS流程中的方法
公开(公告)号：US09102522B2
公开(公告)日：2015-08-11
申请号：US13434347
申请日：2012-03-29
申请人： Krishnaswamy Ramkumar , Bo Jin , Fredrick Jenne
发明人： Krishnaswamy Ramkumar , Bo Jin , Fredrick Jenne
IPC分类号： H01L21/336 , B82Y10/00 , H01L21/28 , H01L29/66 , H01L29/792 , H01L27/115 , H01L21/8234 , H01L21/8238 , H01L27/105
CPC分类号： B82Y10/00 , H01L21/28282 , H01L21/823431 , H01L21/823821 , H01L27/105 , H01L27/1052 , H01L27/11568 , H01L27/11573 , H01L29/66833 , H01L29/792 , H01L29/7926
摘要： An embodiment of a method of integration of a non-volatile memory device into a logic MOS flow is described. Generally, the method includes: forming a pad dielectric layer of a MOS device above a first region of a substrate; forming a channel of the memory device from a thin film of semiconducting material overlying a surface above a second region of the substrate, the channel connecting a source and drain of the memory device; forming a patterned dielectric stack overlying the channel above the second region, the patterned dielectric stack comprising a tunnel layer, a charge-trapping layer, and a sacrificial top layer; simultaneously removing the sacrificial top layer from the second region of the substrate, and the pad dielectric layer from the first region of the substrate; and simultaneously forming a gate dielectric layer above the first region of the substrate and a blocking dielectric layer above the charge-trapping layer.
摘要翻译：描述了将非易失性存储器件集成到逻辑MOS流中的方法的实施例。通常，该方法包括：在衬底的第一区域之上形成MOS器件的焊盘电介质层; 从半导体材料的薄膜形成存储器件的沟道，该半导体材料的薄膜覆盖在衬底的第二区域上方的表面，所述通道连接存储器件的源极和漏极; 形成覆盖在第二区域上方的通道上的图案化电介质堆叠，所述图案化电介质叠层包括隧道层，电荷俘获层和牺牲顶层; 同时从衬底的第二区域去除牺牲顶层，以及从衬底的第一区域去除焊盘介电层; 并且同时在衬底的第一区域上方形成栅极电介质层，并且在电荷俘获层上方形成阻挡电介质层。

40. 发明授权

US08993453B1 Method of fabricating a nonvolatile charge trap memory device 有权
标题翻译：制造非易失性电荷陷阱存储器件的方法
公开(公告)号：US08993453B1
公开(公告)日：2015-03-31
申请号：US13620071
申请日：2012-09-14
申请人： Krishnaswamy Ramkumar , Jeong Byun , Sagy Levy
发明人： Krishnaswamy Ramkumar , Jeong Byun , Sagy Levy
IPC分类号： H01L21/31
CPC分类号： H01L21/28282 , H01L21/3144 , H01L21/3145 , H01L29/4234 , H01L29/66833
摘要： A method for fabricating a nonvolatile charge trap memory device and the device are described. In one embodiment, the method includes providing a substrate in an oxidation chamber, wherein the substrate comprises a first exposed crystal plane and a second exposed crystal plane, and wherein the crystal orientation of the first exposed crystal plane is different from the crystal orientation of the second exposed crystal plane. The substrate is then subjected to a radical oxidation process to form a first portion of a dielectric layer on the first exposed crystal plane and a second portion of the dielectric layer on the second exposed crystal plane, wherein the thickness of the first portion of the dielectric layer is approximately equal to the thickness of the second portion of the dielectric layer.
摘要翻译：描述了一种用于制造非易失性电荷陷阱存储器件及其装置的方法。在一个实施例中，该方法包括在氧化室中提供衬底，其中衬底包括第一暴露的晶体面和第二暴露的晶面，并且其中第一暴露的晶面的晶体取向不同于第二次暴露的晶面。然后对基板进行自由基氧化处理，以在第一暴露的晶面上形成电介质层的第一部分，在第二暴露的晶面上形成电介质层的第二部分，其中电介质的第一部分的厚度层大致等于电介质层的第二部分的厚度。

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