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31. 发明授权

US08723245B2 Nonvolatile memory device 有权
标题翻译：非易失性存储器件
公开(公告)号：US08723245B2
公开(公告)日：2014-05-13
申请号：US13052531
申请日：2011-03-21
申请人： Hiroshi Akahori , Kiyohito Nishihara , Masaki Kondo , Yingkang Zhang , Shigeo Kondo , Hidenobu Nagashima , Kazuaki Iwasawa , Takashi Ichikawa
发明人： Hiroshi Akahori , Kiyohito Nishihara , Masaki Kondo , Yingkang Zhang , Shigeo Kondo , Hidenobu Nagashima , Kazuaki Iwasawa , Takashi Ichikawa
IPC分类号： H01L29/788
CPC分类号： H01L29/7883 , H01L27/11521
摘要： According to one embodiment, a nonvolatile memory device includes a substrate, first and second tunnel insulating films, first and second floating gate electrodes, an intergate insulating film and a control gate electrode. The substrate has first and second active regions isolated from each other by an element isolation trench. The first and second tunnel insulating films are located in the first and second active regions, respectively. The first and second floating gate electrodes are located on the first and second tunnel insulating films, respectively. The intergate insulating film includes a first insulating layer of a first insulating material, an electron trap layer of a second insulating material on the first insulating layer, and a second insulating layer of the first insulating material on the electron trap layer. The control gate electrode is located on the intergate insulating film.
摘要翻译：根据一个实施例，非易失性存储器件包括衬底，第一和第二隧道绝缘膜，第一和第二浮栅电极，栅间绝缘膜和控制栅电极。衬底具有通过元件隔离沟槽彼此隔离的第一和第二有源区。第一和第二隧道绝缘膜分别位于第一和第二有源区中。第一和第二浮栅电极分别位于第一和第二隧道绝缘膜上。隔间绝缘膜包括第一绝缘材料的第一绝缘层，第一绝缘层上的第二绝缘材料的电子陷阱层和电子陷阱层上的第一绝缘材料的第二绝缘层。控制栅电极位于隔间绝缘膜上。

32. 发明申请

US20130015518A1 SEMICONDUCTOR MEMORY DEVICE 审中-公开
标题翻译：半导体存储器件
公开(公告)号：US20130015518A1
公开(公告)日：2013-01-17
申请号：US13353818
申请日：2012-01-19
申请人： Hiroyasu SATO , Kiyohito NISHIHARA , Hidefumi NAWATA , Masayuki ICHIGE , Ryuji OHBA
发明人： Hiroyasu SATO , Kiyohito NISHIHARA , Hidefumi NAWATA , Masayuki ICHIGE , Ryuji OHBA
IPC分类号： H01L29/788
CPC分类号： H01L29/7881 , H01L21/764 , H01L27/11524 , H01L29/40114 , H01L29/42336 , H01L29/66825
摘要： In general, according to one embodiment, a semiconductor memory device includes active areas extending in a first direction, tunnel films provided on the active areas, floating gate electrodes provided on the tunnel films, an interelectrode insulating film provided on the floating gate electrodes and extending in a second direction, a control gate electrode provided on the interelectrode insulating film and extending in the second direction, a lower insulating portion provided between the active areas, between the tunnel films, and between the floating gate electrodes adjacent in the second direction, and an upper insulating portion provided between the lower insulating portion and the interelectrode insulating film. The lower insulating portion includes a void. Relative dielectric constant of the upper insulating portion is higher than that of the lower insulating portion. Relative dielectric constant of the interelectrode insulating film is higher than that of the upper insulating portion.
摘要翻译：通常，根据一个实施例，半导体存储器件包括在第一方向上延伸的有源区域，设置在有源区域上的隧道膜，设置在隧道膜上的浮置栅极电极，设置在浮动栅电极上并延伸的电极间绝缘膜在第二方向上，设置在电极间绝缘膜上并沿第二方向延伸的控制栅电极，设置在有源区之间，隧道膜之间以及在第二方向相邻的浮栅之间的下绝缘部分，以及设置在下绝缘部和电极间绝缘膜之间的上绝缘部。下绝缘部分包括空隙。上绝缘部分的相对介电常数高于下绝缘部分的相对介电常数。电极间绝缘膜的相对介电常数高于上绝缘部分。

33. 发明授权

US08212308B2 Nonvolatile semiconductor flash memory 失效
标题翻译：非易失性半导体闪存
公开(公告)号：US08212308B2
公开(公告)日：2012-07-03
申请号：US12618058
申请日：2009-11-13
申请人： Kiyohito Nishihara , Fumitaka Arai
发明人： Kiyohito Nishihara , Fumitaka Arai
IPC分类号： H01L29/788
CPC分类号： H01L29/42336 , H01L21/764 , H01L27/11521 , H01L27/11524 , H01L29/7881
摘要： Two diffusion layers are provided in an element area. A tunnel insulating film is provided on the surface of the element area between the two diffusion layers. A charge storage layer is provided on the tunnel insulating film. A first insulator provided on the upper surface of the charge storage layer. An inter-electrode insulating film provided on the first insulator, on the side surface of the charge storage layer in a first direction and on the isolation insulating film. And a control gate electrode extends in the first direction and covers the charge storage layer via the first insulator and the inter-electrode insulating film. The first insulator is thicker than the inter-electrode insulating film, and the inter-electrode insulating film has a first slit on the first insulator.
摘要翻译：在元件区域中设置两个扩散层。隧道绝缘膜设置在两个扩散层之间的元件区域的表面上。电荷存储层设置在隧道绝缘膜上。设置在电荷存储层的上表面上的第一绝缘体。一种电极间绝缘膜，设置在第一绝缘体上，在电荷存储层的第一方向的侧表面上以及隔离绝缘膜上。并且控制栅极电极沿第一方向延伸并且经由第一绝缘体和电极间绝缘膜覆盖电荷存储层。第一绝缘体比电极间绝缘膜厚，并且电极间绝缘膜在第一绝缘体上具有第一狭缝。

34. 发明授权

US08183624B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08183624B2
公开(公告)日：2012-05-22
申请号：US12061075
申请日：2008-04-02
申请人： Makoto Mizukami , Kiyohito Nishihara
发明人： Makoto Mizukami , Kiyohito Nishihara
IPC分类号： H01L29/788
CPC分类号： H01L27/105 , H01L27/0688 , H01L27/11529 , H01L27/11531 , H01L27/11556
摘要： A semiconductor memory device includes a substrate having a step including a first upper surface and a second upper surface higher than the first upper surface, a memory cell array formed on the first upper surface, and a peripheral circuit formed on the second upper surface and configured to supply an electrical signal to the memory cell array. The memory cell array includes a stacked structure having a plurality of first interconnection layers and a plurality of second interconnection layers respectively connected to the first interconnection layers. The first interconnection layers are stacked on the first upper surface, are separated from each other by insulating films, and extend in a first direction. The second interconnection layers extend upward and are separated from each other by insulating films.
摘要翻译：半导体存储器件包括具有包括第一上表面和高于第一上表面的第二上表面的步骤的衬底，形成在第一上表面上的存储单元阵列和形成在第二上表面上的外围电路，以向存储单元阵列提供电信号。存储单元阵列包括具有分别连接到第一互连层的多个第一互连层和多个第二互连层的层叠结构。第一互连层堆叠在第一上表面上，通过绝缘膜彼此分离，并沿第一方向延伸。第二互连层向上延伸并通过绝缘膜彼此分离。

35. 发明授权

US08039886B2 Depletion-type NAND flash memory 有权
标题翻译：消耗型NAND闪存
公开(公告)号：US08039886B2
公开(公告)日：2011-10-18
申请号：US12603099
申请日：2009-10-21
申请人： Makoto Mizukami , Kiyohito Nishihara
发明人： Makoto Mizukami , Kiyohito Nishihara
IPC分类号： H01L29/94
CPC分类号： H01L27/11568 , G11C16/0483 , H01L21/84 , H01L27/11521 , H01L27/11524 , H01L27/11556 , H01L27/11578 , H01L27/11582 , H01L27/1203
摘要： A depletion-type NAND flash memory includes a NAND string composed of a plurality of serially connected FETs, a control circuit which controls gate potentials of the plurality of FETs in a read operation, a particular potential storage, and an adjacent memory cell threshold storage, wherein each of the plurality of FETs is a transistor whose threshold changes in accordance with a charge quantity in a charge accumulation layer, the adjacent memory cell threshold storage stores a threshold of a source line side FET adjacent to a source line side of a selected FET, and the control circuit applies a potential to the gate electrode of the source line side FET in the read operation, the applied potential being obtained by adding a particular potential stored in the particular potential storage to a threshold stored in the adjacent memory cell threshold storage.
摘要翻译：耗尽型NAND闪存包括由多个串联连接的FET组成的NAND串，控制电路，其在读取操作中控制多个FET的栅极电位，特定的电位存储器和相邻的存储单元阈值存储器，其中，所述多个FET中的每一个是其阈值根据电荷累积层中的电荷量而变化的晶体管，所述相邻存储单元阈值存储器存储与所选择的FET的源极侧相邻的源极侧FET的阈值，并且控制电路在读取操作中向源极侧FET的栅电极施加电位，所施加的电位通过将存储在特定电位存储器中的特定电位加到存储在相邻存储单元阈值存储器中的阈值。

36. 发明申请

US20110012185A1 SEMICONDUCTOR MEMORY DEVICE AND WRITE METHOD OF THE SAME 有权
标题翻译：半导体存储器件及其写入方法
公开(公告)号：US20110012185A1
公开(公告)日：2011-01-20
申请号：US12889848
申请日：2010-09-24
申请人： Kiyohito NISHIHARA
发明人： Kiyohito NISHIHARA
IPC分类号： H01L29/788
CPC分类号： H01L29/7883 , G11C13/0009 , H01L27/115 , H01L27/2463 , H01L29/42324 , H01L29/42328 , H01L29/512 , H01L45/085 , H01L45/1206 , H01L45/142 , H01L45/143
摘要： A write and erase method of a semiconductor memory device includes a floating gate type transistor having a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a floating gate electrode formed on the gate insulating film, and a control gate electrode opposing the floating gate electrode with a hollow portion being sandwiched therebetween. A capacitance between the semiconductor substrate and the control gate electrode is controlled by one of an operation of forming, in the hollow portion, an electrical path which electrically connects the floating gate electrode and the control gate electrode, and an operation of eliminating the electrical path.
摘要翻译：半导体存储器件的写入和擦除方法包括具有半导体衬底的浮栅型晶体管，形成在半导体衬底上的栅极绝缘膜，形成在栅极绝缘膜上的浮置栅电极和与浮置栅极相对的控制栅电极夹着中空部的栅电极。在半导体衬底和控制栅电极之间的电容通过在空心部分中形成电连接浮栅电极和控制栅电极的电路以及消除电路的操作之一来控制。

37. 发明申请

US20100140213A1 APPARATUS FOR MANUFACTURING CARBON NANO TUBES AND METHOD OF SORTING CARBON NANO TUBES 审中-公开
标题翻译：用于制造碳纳米管的装置和分配碳纳米管的方法
公开(公告)号：US20100140213A1
公开(公告)日：2010-06-10
申请号：US12618039
申请日：2009-11-13
申请人： Makoto MIZUKAMI , Kiyohito NISHIHARA
发明人： Makoto MIZUKAMI , Kiyohito NISHIHARA
IPC分类号： B44C1/22 , B05D3/00 , B03C1/00
CPC分类号： B03C1/08 , B03C1/24 , B03C2201/20 , B03C2201/26 , B82Y30/00 , B82Y40/00 , C01B32/172 , C01B2202/22
摘要： An apparatus for manufacturing carbon nano tubes of an aspect of the present invention including an introducing unit commonly introducing a first carbon nano tube having first magnetic characteristics and a second carbon nano tube having second magnetic characteristics different from the first magnetic characteristics, first and second collecting units collecting the first and second carbon nano tubes, respectively, a transport unit transporting the first and second carbon nano tubes from the introducing unit to the first and second collecting units, and at least one of a magnetic field generating unit which is provided adjacent to the transport unit and applies a magnetic field to the first and second carbon nano tubes, wherein the first carbon nano tube and the second carbon nano tube are sorted by the magnetic field generating unit.
摘要翻译：本发明的一个方面的碳纳米管的制造装置，其特征在于，包括通常导入具有第一磁特性的第一碳纳米管的导入部和具有与第一磁特性不同的第二磁特性的第二碳纳米管，第一和第二收集分别收集第一和第二碳纳米管的传送单元，其将第一和第二碳纳米管从引入单元传送到第一和第二收集单元;以及至少一个磁场产生单元，所述输送单元对所述第一和第二碳纳米管施加磁场，其中所述第一碳纳米管和所述第二碳纳米管由所述磁场产生单元分选。

38. 发明申请

US20100117134A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100117134A1
公开(公告)日：2010-05-13
申请号：US12562558
申请日：2009-09-18
申请人： Kiyohito NISHIHARA
发明人： Kiyohito NISHIHARA
IPC分类号： H01L27/105 , H01L21/336
CPC分类号： H01L27/11578 , H01L27/11565 , H01L27/11573 , H01L27/11582 , H01L29/40117 , H01L29/66833 , H01L29/792 , H01L29/7926
摘要： A dielectric film is formed on a silicon substrate made of single crystal silicon, an opening is formed in the dielectric film, an amorphous silicon film is formed on the dielectric film, the amorphous silicon film being in contact with the silicon substrate through the opening, solid-phase epitaxial growth of this amorphous silicon film is caused to start at the silicon substrate, and thereafter patterning is performed. Thereby, a seed layer made of the single crystal silicon is formed in part of a region deviated from immediately above the opening. Next, the amorphous silicon film is deposited so as to cover the seed layer, forming a single crystal silicon film by solid-phase epitaxial growth of the amorphous silicon film starting at the seed layer. The silicon pillar is formed by patterning the single crystal silicon film.
摘要翻译：在由单晶硅制成的硅衬底上形成电介质膜，在电介质膜中形成开口，在电介质膜上形成非晶硅膜，非晶硅膜通过开口与硅衬底接触，使该非晶硅膜的固相外延生长从硅衬底开始，然后进行图案化。由此，在从开口的正上方偏离的区域的一部分形成由单晶硅构成的种子层。接下来，沉积非晶硅膜以覆盖种子层，通过从种子层开始的非晶硅膜的固相外延生长形成单晶硅膜。通过图案化单晶硅膜形成硅柱。

39. 发明申请

US20090090959A1 NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：非挥发性半导体存储器件及其制造方法
公开(公告)号：US20090090959A1
公开(公告)日：2009-04-09
申请号：US12244174
申请日：2008-10-02
申请人： Kiyohito Nishihara , Fumitaka Arai
发明人： Kiyohito Nishihara , Fumitaka Arai
IPC分类号： H01L29/423 , H01L21/28
CPC分类号： H01L27/1203 , H01L27/11565 , H01L27/11568 , H01L27/11578 , H01L27/11582 , H01L29/792 , H01L29/7926
摘要： A first lamination part includes: a charge accumulation layer provided on the respective sidewalls of laminated first conductive layers and accumulating charges; and a first semiconductor layer provided in contact with the fourth insulation layer and formed to extend to the lamination direction. A second lamination part includes a second semiconductor layer provided in contact with the first semiconductor layer. A third lamination part includes: a plurality of first contact layers formed in contact with the respective second lamination part, extending to a first direction perpendicular to the lamination direction, and in line with each other along a second direction perpendicular to the first direction; and a plurality of contact plug layers formed in contact with any one of the first contact layers and extending to the lamination direction. The contact plug layers are arranged at different positions relative to each other in the first direction.
摘要翻译：第一层压部件包括：电荷累积层，设置在层叠的第一导电层的各个侧壁上并积累电荷; 以及第一半导体层，设置成与所述第四绝缘层接触并形成为向层叠方向延伸。第二层压部件包括与第一半导体层接触设置的第二半导体层。第三层压部件包括：多个第一接触层，其形成为与相应的第二层压部分接触，延伸到垂直于层叠方向的第一方向，并且沿着垂直于第一方向的第二方向彼此成直线; 以及多个接触塞层，其形成为与所述第一接触层中的任一个接触并延伸到层叠方向。接触塞层在第一方向上相对于彼此设置在不同的位置。

40. 发明申请

US20090003071A1 SEMICONDUCTOR STORAGE DEVICE AND READ VOLTAGE CORRECTION METHOD 审中-公开
标题翻译：半导体存储器件和读取电压校正方法
公开(公告)号：US20090003071A1
公开(公告)日：2009-01-01
申请号：US11850390
申请日：2007-09-05
申请人： Kiyohito NISHIHARA , Fumitaka Arai
发明人： Kiyohito NISHIHARA , Fumitaka Arai
IPC分类号： G11C16/06
CPC分类号： H01L27/105 , G11C16/0483 , G11C16/26 , G11C16/3427 , H01L27/115 , H01L27/11502 , H01L27/11509 , H01L27/11526
摘要： A semiconductor memory device comprises a semiconductor memory, a corrected voltage storage circuit which stores a corrected voltage produced by correcting a read voltage of the semiconductor memory, and a memory controller which reads the corrected voltage from the corrected voltage storage circuit and performs a read operation of the semiconductor memory using the corrected voltage.
摘要翻译：半导体存储器件包括：半导体存储器，存储通过校正半导体存储器的读取电压产生的校正电压的校正电压存储电路;以及从校正后的电压存储电路读取校正电压并进行读取操作的存储器控制器的半导体存储器。

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