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31. 发明申请

US20090240483A1 SYSTEM AND COMPUTER PROGRAM PRODUCT FOR AUTOMATIC LOGIC MODEL BUILD PROCESS WITH AUTONOMOUS QUALITY CHECKING 失效
标题翻译：具有自动质量检查功能的自动逻辑建模过程的系统和计算机程序产品
公开(公告)号：US20090240483A1
公开(公告)日：2009-09-24
申请号：US12051288
申请日：2008-03-19
申请人： Matthew A. Adams , Khary J. Alexander , Matthew G. Pardini
发明人： Matthew A. Adams , Khary J. Alexander , Matthew G. Pardini
IPC分类号： G06F9/455
CPC分类号： G06F11/261 , G06F17/5022 , G06F2217/86
摘要： A computer program product stored including machine executable instructions stored on machine readable media, the instructions configured for performing automatic logic build processes and implementing autonomic quality checking, by implementing a method including: providing a model repository for holding at least one component; updating the model repository with at least one component; creating a tag for each sub-component of a selected component of the model repository; associating each tag with a latest version of each respective sub-component; and issuing a component submit notice to identify at least one of a dependency and a priority between selected components. A system is also provided.
摘要翻译：存储的计算机程序产品包括存储在机器可读介质上的机器可执行指令，所述指令被配置为执行自动逻辑构建过程并执行自主质量检查，所述方法包括：提供用于保持至少一个组件的模型库; 使用至少一个组件更新模型库; 为模型存储库的所选组件的每个子组件创建标签; 将每个标签与每个相应子组件的最新版本相关联; 以及发布组件提交通知以识别所选组件之间的依赖关系和优先级中的至少一个。还提供了一个系统。

32. 发明申请

US20090210661A1 METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR AN IMPLICIT PREDICTED RETURN FROM A PREDICTED SUBROUTINE 失效
标题翻译：方法，系统和计算机程序产品预测从预测的SUBROUTINE返回
公开(公告)号：US20090210661A1
公开(公告)日：2009-08-20
申请号：US12034066
申请日：2008-02-20
申请人： Khary J. Alexander , James J. Bonanno , Brian R. Prasky , Anthony Saporito , Robert J. Sonnelitter, III , Charles F. Webb
发明人： Khary J. Alexander , James J. Bonanno , Brian R. Prasky , Anthony Saporito , Robert J. Sonnelitter, III , Charles F. Webb
IPC分类号： G06F9/312
CPC分类号： G06F9/30054 , G06F9/3804 , G06F9/3806 , G06F9/3844
摘要： A method, system and computer program product for performing an implicit predicted return from a predicted subroutine are provided. The system includes a branch history table/branch target buffer (BHT/BTB) to hold branch information, including a target address of a predicted subroutine and a branch type. The system also includes instruction buffers, and instruction fetch controls to perform a method including fetching a branch instruction at a branch address and a return-point instruction. The method also includes receiving the target address and the branch type, and fetching a fixed number of instructions in response to the branch type. The method further includes referencing the return-point instruction within the instruction buffers such that the return-point instruction is available upon completing the fetching of the fixed number of instructions absent a re-fetch of the return-point instruction.
摘要翻译：提供了一种用于从预测子程序执行隐含预测返回的方法，系统和计算机程序产品。该系统包括用于保持分支信息的分支历史表/分支目标缓冲器（BHT / BTB），包括预测子程序的目标地址和分支类型。该系统还包括指令缓冲器和指令获取控制，以执行包括在分支地址和返回点指令处获取分支指令的方法。该方法还包括接收目标地址和分支类型，以及响应于分支类型取出固定数目的指令。该方法还包括引用指令缓冲器内的返回点指令，使得在没有重新获取返回点指令的情况下完成取出固定数目的指令后，返回点指令是可用的。

33. 发明授权

US09218288B2 Monitoring a value in storage without repeated storage access 有权
标题翻译：在不重复存储访问的情况下监视存储中的值
公开(公告)号：US09218288B2
公开(公告)日：2015-12-22
申请号：US13524063
申请日：2012-06-15
申请人： Khary J. Alexander , Ute Gaertner , Jonathan T. Hsieh , Christian Jacobi , Timothy J. Slegel
发明人： Khary J. Alexander , Ute Gaertner , Jonathan T. Hsieh , Christian Jacobi , Timothy J. Slegel
IPC分类号： G06F12/02 , G06F12/08 , G06F3/06
CPC分类号： G06F12/0808 , G06F3/0653 , G06F12/0815 , G06F12/0831 , G06F12/0833 , G06F12/0891
摘要： A technique is provided for monitoring a value without repeated storage access. A processing circuit processes an instruction of a program that specifies a memory address of a memory location to be monitored. The processing circuit configures a monitor station for monitoring the memory location. The memory location includes a state descriptor for the program. The processing circuit receives a cross-invalidate request from a memory controller. The cross-invalidate request indicates to the monitor station that content of the memory location has been changed by another processing circuit.
摘要翻译：提供了一种用于监视值而不重复存储访问的技术。处理电路处理指定要监视的存储器位置的存储器地址的程序的指令。处理电路配置用于监视存储器位置的监视站。存储器位置包括程序的状态描述符。处理电路从存储器控制器接收到交叉无效请求。交叉无效请求向监视台指示存储器位置的内容已被另一处理电路改变。

34. 发明授权

US09164912B2 Conflict resolution of cache store and fetch requests 有权
标题翻译：冲突解决缓存存储和提取请求
公开(公告)号：US09164912B2
公开(公告)日：2015-10-20
申请号：US13495781
申请日：2012-06-13
申请人： Khary J. Alexander , David A. Webber , Patrick M. West, Jr.
发明人： Khary J. Alexander , David A. Webber , Patrick M. West, Jr.
IPC分类号： G06F13/00 , G06F12/08 , G06F9/38
CPC分类号： G06F12/0855 , G06F9/3824 , G06F9/3826 , G06F9/3834 , G06F9/3867 , G06F12/0804
摘要： According to an embodiment, a computer system for cache management includes a processor and a cache, the computer system configured to perform a method including receiving a first store request for a first address in the cache and receiving a first fetch request for the first address in the cache. The method also includes executing the first store request and the first fetch request, latching the first store request in a store write-back pipeline in the cache, detecting, in the processor, a conflict following execution of the first store request and the first fetch request and receiving the first store request from a recycle path including the store write-back pipeline and executing the first store request a second time.
摘要翻译：根据实施例，用于高速缓存管理的计算机系统包括处理器和高速缓存，该计算机系统被配置为执行一种方法，该方法包括：在高速缓存中接收第一地址的第一存储请求，并且接收第一地址的第一提取请求缓存。该方法还包括执行第一存储请求和第一提取请求，将第一存储请求锁存在高速缓存中的存储回写流水线中，在处理器中检测在执行第一存储请求和第一存取之后的冲突从包括商店回写流水线的再循环路径请求并接收第一商店请求，并且第二次执行第一商店请求。

35. 发明授权

US09021240B2 System and method for Controlling restarting of instruction fetching using speculative address computations 有权
标题翻译：使用推测地址计算控制指令重写的系统和方法
公开(公告)号：US09021240B2
公开(公告)日：2015-04-28
申请号：US12035911
申请日：2008-02-22
申请人： Khary J. Alexander , Brian R. Prasky , Anthony Saporito , Robert J. Sonnelitter, III
发明人： Khary J. Alexander , Brian R. Prasky , Anthony Saporito , Robert J. Sonnelitter, III
IPC分类号： G06F9/38 , G06F9/32
CPC分类号： G06F9/3861 , G06F9/322 , G06F9/3804 , G06F9/3806 , G06F9/3838 , G06F9/3842 , G06F9/3867
摘要： A system and method for controlling restarting of instruction fetching using speculative address computations in a processor are provided. The system includes a predicted target queue to hold branch prediction logic (BPL) generated target address values. The system also includes target selection logic including a recycle queue. The target selection logic selects a saved branch target value between a previously speculatively calculated branch target value from the recycle queue and an address value from the predicted target queue. The system further includes a compare block to identify a wrong target in response to a mismatch between the saved branch target value and a current calculated branch target, where instruction fetching is restarted in response to the wrong target.
摘要翻译：提供了一种用于使用处理器中的推测地址计算来控制重新启动指令取出的系统和方法。该系统包括预测的目标队列以保持分支预测逻辑（BPL）生成的目标地址值。系统还包括目标选择逻辑，包括循环队列。目标选择逻辑从先前推测计算出的来自再循环队列的分支目标值和来自预测目标队列的地址值之间选择保存的分支目标值。系统还包括比较块，用于响应于所保存的分支目标值与当前计算的分支目标之间的不匹配来识别错误的目标，其中响应于错误的目标重新启动指令获取。

36. 发明申请

US20130339628A1 DETERMINING THE LOGICAL ADDRESS OF A TRANSACTION ABORT 有权
标题翻译：确定交易的逻辑地址
公开(公告)号：US20130339628A1
公开(公告)日：2013-12-19
申请号：US13524342
申请日：2012-06-15
申请人： Khary J. Alexander , Jonathan T. Hsieh , Christian Jacobi
发明人： Khary J. Alexander , Jonathan T. Hsieh , Christian Jacobi
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/00 , G06F9/3004 , G06F9/30087 , G06F9/3834 , G06F9/3859 , G06F12/08 , G06F12/0808 , G06F12/0815 , G06F12/0822 , G06F12/0831 , G06F12/0833 , G06F12/0891
摘要： Embodiments relate to determining the logical address of a transaction abort. In an embodiment, one or more instructions are received are received from an application. The one or more instructions are executed within a first transaction. The first transaction delays committing stores to memory until it has completed. At least one of the one or more instructions includes a first logical memory address. The first logical memory address corresponds to a first memory address in a memory system. It is determined if the first memory address is equal to a second memory address that is stored in a conflict register. Based on determining that they are equal the first logical memory address is saved as a logical address associated with a cross invalidate (XI) signal at a location available to the application.
摘要翻译：实施例涉及确定事务中止的逻辑地址。在一个实施例中，从应用程序接收一个或多个接收的指令。一个或多个指令在第一事务中执行。第一个交易延迟将存储提交到内存，直到它完成。所述一个或多个指令中的至少一个包括第一逻辑存储器地址。第一逻辑存储器地址对应于存储器系统中的第一存储器地址。确定第一存储器地址是否等于存储在冲突寄存器中的第二存储器地址。基于确定它们相等，第一逻辑存储器地址被保存为与应用可用的位置处的交叉无效（XI）信号相关联的逻辑地址。

37. 发明申请

US20130339614A1 MITIGATING CONFLICTS FOR SHARED CACHE LINES 有权
标题翻译：缓解高速缓存行的冲突
公开(公告)号：US20130339614A1
公开(公告)日：2013-12-19
申请号：US13523453
申请日：2012-06-14
申请人： Khary J. Alexander , Chung-Lung K. Shum
发明人： Khary J. Alexander , Chung-Lung K. Shum
IPC分类号： G06F12/08
CPC分类号： G06F12/084 , G06F12/08
摘要： A computer program product for mitigating conflicts for shared cache lines between an owning core currently owning a cache line and a requestor core. The computer program product includes a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method. The method includes determining whether the owning core is operating in a transactional or non-transactional mode and setting a hardware-based reject threshold at a first or second value with the owning core determined to be operating in the transactional or non-transactional mode, respectively. The method further includes taking first or second actions to encourage cache line sharing between the owning core and the requestor core in response to a number of rejections of requests by the requestor core reaching the reject threshold set at the first or second value, respectively.
摘要翻译：一种用于减轻当前拥有高速缓存行和请求者核心的所有核心之间的共享高速缓存行的冲突的计算机程序产品。计算机程序产品包括可由处理电路读取的有形存储介质，并且存储由处理电路执行以执行方法的指令。该方法包括确定所拥有的核心是以事务性还是非交易模式操作，并且将所确定的拥有核心分别以事务性或非事务性模式操作的第一或第二值设置为基于硬件的拒绝阈值。该方法还包括采取第一或第二动作以响应于请求者核心达到以第一或第二值设置的拒绝阈值的请求的拒绝次数来鼓励拥有核心和请求者核心之间的高速缓存行共享。

38. 发明授权

US08516228B2 Supporting partial recycle in a pipelined microprocessor 有权
标题翻译：支持流水线微处理器的部分回收
公开(公告)号：US08516228B2
公开(公告)日：2013-08-20
申请号：US12051486
申请日：2008-03-19
申请人： Khary J. Alexander , Michael Billeci , Fadi Y. Busaba , Bruce C. Giamei
发明人： Khary J. Alexander , Michael Billeci , Fadi Y. Busaba , Bruce C. Giamei
IPC分类号： G06F9/00
CPC分类号： G06F9/3865 , G06F9/3836 , G06F9/3842
摘要： A computer processing system is provided. The computer processing system includes a first datastore that stores a subset of information associated with an instruction. A first stage of a processor pipeline writes the subset of information to the first datastore based on an execution of an operation associated with the instruction. A second stage of the pipeline initiates reprocessing of the operation associated with the instruction based on the subset of information stored in the first datastore.
摘要翻译：提供了一种计算机处理系统。计算机处理系统包括存储与指令相关联的信息的子集的第一数据存储区。处理器流水线的第一阶段基于与指令相关联的操作的执行将信息子集写入第一数据存储区。管道的第二阶段基于存储在第一数据存储区中的信息子集来启动与指令相关联的操作的再处理。

39. 发明授权

US08201067B2 Processor error checking for instruction data 有权
标题翻译：处理器错误检查指令数据
公开(公告)号：US08201067B2
公开(公告)日：2012-06-12
申请号：US12037038
申请日：2008-02-25
申请人： Fadi Y. Busaba , Khary J. Alexander , Michael Billeci , Bruce C. Giamei , Vimal M. Kapadia
发明人： Fadi Y. Busaba , Khary J. Alexander , Michael Billeci , Bruce C. Giamei , Vimal M. Kapadia
IPC分类号： G06F11/00 , G08C25/00 , H03M13/00 , H04L1/00
CPC分类号： G06F11/10
摘要： A method for processor error checking including receiving an instruction data, generating a pre-processing parity data based on the instruction data, maintaining the pre-processing parity data, processing the instruction data, generating a post-processing parity data based on the processed instruction data, checking for an error related to processing the instruction data by comparing the post-processing parity data to the pre-processing parity data, and transmitting an error signal that indicates the error related to processing the instruction data occurred if the post-processing parity data does not match the pre-processing parity data, wherein checking for the error related to processing the instruction data is performed without using a duplicate processing circuitry.
摘要翻译：一种用于处理器错误检查的方法，包括接收指令数据，基于指令数据产生预处理奇偶校验数据，维持预处理奇偶校验数据，处理指令数据，基于处理指令产生后处理奇偶校验数据数据，通过将后处理奇偶校验数据与预处理奇偶校验数据进行比较来检查与处理指令数据相关的错误，以及如果后处理奇偶校验数据发送指示与处理指令数据相关的错误的错误信号数据与预处理奇偶校验数据不匹配，其中在不使用重复处理电路的情况下执行检查与处理指令数据有关的错误。

40. 发明申请

US20110167244A1 EARLY INSTRUCTION TEXT BASED OPERAND STORE COMPARE REJECT AVOIDANCE 失效
标题翻译：早期指导性文本操作存储比较对象避免
公开(公告)号：US20110167244A1
公开(公告)日：2011-07-07
申请号：US13050484
申请日：2011-03-17
申请人： Khary J. Alexander , Fadi Y. Busaba , Bruce C. Giamei , David S. Hutton , Chung-Lung K. Shum
发明人： Khary J. Alexander , Fadi Y. Busaba , Bruce C. Giamei , David S. Hutton , Chung-Lung K. Shum
IPC分类号： G06F9/30
CPC分类号： G06F9/3826 , G06F9/3016 , G06F9/382 , G06F9/3834 , G06F9/3836 , G06F9/3861
摘要： A method and system for early instruction text based operand store compare avoidance in a processor are provided. The system includes a processor pipeline for processing instruction text in an instruction stream, where the instruction text includes operand address information. The system also includes delay logic to monitor the instruction stream. The delay logic performs a method that includes detecting a load instruction following a store instruction in the instruction stream, comparing the operand address information of the store instruction with the load instruction. The method also includes delaying the load instruction in the processor pipeline in response to detecting a common field value between the operand address information of the store instruction and the load instruction.
摘要翻译：提供了一种用于处理器中早期指令文本操作数存储比较避免的方法和系统。该系统包括用于处理指令流中的指令文本的处理器流水线，其中指令文本包括操作数地址信息。该系统还包括监视指令流的延迟逻辑。延迟逻辑执行一种方法，其包括检测在指令流中的存储指令之后的加载指令，将存储指令的操作数地址信息与加载指令进行比较。响应于检测存储指令的操作数地址信息和加载指令之间的公共字段值，该方法还包括延迟处理器流水线中的加载指令。

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