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31. 发明申请

US20110006346A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20110006346A1
公开(公告)日：2011-01-13
申请号：US12919640
申请日：2009-03-12
申请人： Yuji Ando , Yasuhiro Okamoto , Kazuki Ota , Takashi Inoue , Tatsuo Nakayama , Hironobu Miyamoto
发明人： Yuji Ando , Yasuhiro Okamoto , Kazuki Ota , Takashi Inoue , Tatsuo Nakayama , Hironobu Miyamoto
IPC分类号： H01L29/737
CPC分类号： H01L29/7783 , H01L29/2003 , H01L29/4236 , H01L29/518 , H01L29/7785
摘要： The present invention provides a semiconductor device that has high electron mobility while reducing a gate leakage current, and superior uniformity and reproducibility of the threshold voltage, and is also applicable to the enhancement mode type. The semiconductor device according to the present invention is a semiconductor device having such a structure formed by sequentially laminating a lower barrier layer composed of lattice-relaxed AlxGa1-xN (0≦x≦1), a channel layer composed of InyGa1-yN (0≦y≦1) with compressive strain and a contact layer composed of AlzGa1-zN (0≦z≦1), wherein a two-dimensional electron gas is produced in the vicinity of an interface of said InyGa1-yN channel layer with said AlzGa1-zN contact layer; a gate electrode is formed so as to be embedded in the recessed portion with intervention of an insulating film, which recessed portion is formed by removing a part of said AlzGa1-zN contact layer by etching it away until said InyGa1-yN channel layer is exposed; and, ohmic electrodes are formed on the AlzGa1-zN contact layer. Thus, there is provided a semiconductor device that has superior uniformity and reproducibility of the threshold voltage while maintaining a low gate leakage current and high electron mobility, and thereby, is capable of operation in enhancement mode.
摘要翻译：本发明提供了一种在降低栅极漏电流的同时具有高电子迁移率并具有优异的阈值电压的均匀性和再现性的半导体器件，并且也适用于增强型。根据本发明的半导体器件是具有这样的结构的半导体器件，该半导体器件通过顺序地层叠由晶格弛豫的Al x Ga 1-x N（0＆lt; n 1; x＆n 1; 1）构成的下阻挡层，由InyGa1-yN（0＆ ; y＆nlE; 1）具有压应变和由AlzGa1-zN（0＆amp; nlE; z＆nlE; 1）组成的接触层，其中在所述In y Ga 1-y N沟道层的界面附近产生二维电子气体与所述AlzGa1 -zN接触层通过介入绝缘膜形成嵌入在凹陷部分中的栅电极，该凹陷部分通过蚀刻除去所述AlzGa1-zN接触层的一部分而形成，直到所述In y Ga 1-y N沟道层暴露 ; 并且在AlzGa1-zN接触层上形成欧姆电极。因此，提供了具有优异的阈值电压的均匀性和再现性的半导体器件，同时保持低栅极漏电流和高电子迁移率，从而能够在增强模式下操作。

32. 发明申请

US20100270559A1 FIELD EFFECT TRANSISTOR AND PROCESS FOR MANUFACTURING SAME 有权
标题翻译：场效应晶体管及其制造方法
公开(公告)号：US20100270559A1
公开(公告)日：2010-10-28
申请号：US12742587
申请日：2008-11-17
申请人： Kazuki Ota
发明人： Kazuki Ota
IPC分类号： H01L29/80 , H01L21/337 , H01L29/205
CPC分类号： H01L29/7787 , H01L29/2003 , H01L29/66462
摘要： A field effect transistor includes: a channel layer 103 containing GaN or InGaN; a first electron-supplying layer 104 disposed over the channel layer 103 and containing InxAlyGa1-x-yN (0≦x
摘要翻译：场效应晶体管包括：包含GaN或InGaN的沟道层103; 第一电子供应层104设置在沟道层103上并且包含In x Al y Ga 1-x-y N（0＆nl E; x <1,0

33. 发明申请

US20090267114A1 FIELD EFFECT TRANSISTOR 审中-公开
标题翻译：场效应晶体管
公开(公告)号：US20090267114A1
公开(公告)日：2009-10-29
申请号：US12295104
申请日：2007-03-23
申请人： Tatsuo Nakayama , Yuji Ando , Hironobu Miyamoto , Yasuhiro Okamoto , Takashi Inoue , Kazuki Ota , Yasuhiro Murase , Naotaka Kuroda
发明人： Tatsuo Nakayama , Yuji Ando , Hironobu Miyamoto , Yasuhiro Okamoto , Takashi Inoue , Kazuki Ota , Yasuhiro Murase , Naotaka Kuroda
IPC分类号： H01L29/772 , H01L29/205
CPC分类号： H01L29/7787 , H01L29/2003 , H01L29/42316 , H01L29/66462 , H01L29/8128
摘要： A field effect transistor 100 includes a group III-V nitride semiconductor layer structure containing a hetero junction, a source electrode 105 and a drain electrode 106 formed on the group III-V nitride semiconductor layer structure to be spaced apart from each other; a gate electrode 110 arranged between the source electrode 105 and the drain electrode 106, and an insulating layer 107 provided over, and in contact with, the group III-V nitride semiconductor layer structure in a region between the gate electrode 110 and the drain electrode 106 or in a region between the source electrode 105 and the gate electrode 110. A portion of the gate electrode 110 is buried in the group III-V nitride semiconductor layer structure, and a side edge of the gate electrode in an interface of the group III-V nitride semiconductor layer and the insulating layer 107 is spaced apart from the gate electrode 110.
摘要翻译：场效应晶体管100包括在III-V族氮化物半导体层结构上彼此间隔开的含有异质结的III-V族氮化物半导体层结构，源电极105和漏电极106。布置在源电极105和漏电极106之间的栅电极110以及在栅电极110和漏电极之间的区域中设置在III-V族氮化物半导体层结构上并与III-V族氮化物半导体层结构接触的绝缘层107 106或源极电极105和栅电极110之间的区域中。栅电极110的一部分被掩埋在III-V族氮化物半导体层结构中，并且栅极电极在该组的界面中的侧边缘 III-V族氮化物半导体层和绝缘层107与栅电极110间隔开。

34. 发明授权

US08716835B2 Bipolar transistor 有权
标题翻译：双极晶体管
公开(公告)号：US08716835B2
公开(公告)日：2014-05-06
申请号：US13124873
申请日：2009-10-16
申请人： Yuji Ando , Hironobu Miyamoto , Tatsuo Nakayama , Yasuhiro Okamoto , Takashi Inoue , Kazuki Ota
发明人： Yuji Ando , Hironobu Miyamoto , Tatsuo Nakayama , Yasuhiro Okamoto , Takashi Inoue , Kazuki Ota
IPC分类号： H01L29/66 , H01L29/737 , H01L29/20
CPC分类号： H01L29/7371 , H01L29/0649 , H01L29/0817 , H01L29/0821 , H01L29/2003 , H01L29/205 , H01L29/475 , H01L29/66318
摘要： A bipolar transistor is provided with an emitter layer, a base layer and a collector layer. The emitter layer is formed above a substrate and is an n-type conductive layer including a first nitride semiconductor. The base layer is formed on the emitter layer and is a p-type conductive including a second nitride semiconductor. The collector layer is formed on the base layer and includes a third nitride semiconductor. The collector layer, the base layer and the emitter layer are formed such that a crystal growth direction to the substrate surface is parallel to a substrate direction of [000-1]. The third nitride semiconductor contains InycAlxcGa1-xc-ycN (0•xc•1, 0•yc•1, 0
摘要翻译：双极晶体管设置有发射极层，基极层和集电极层。发射极层形成在衬底之上，并且是包括第一氮化物半导体的n型导电层。基极层形成在发射极层上，是包含第二氮化物半导体的p型导体。集电极层形成在基极层上并且包括第三氮化物半导体。形成集电体层，基极层和发射极层，使得到基板表面的晶体生长方向平行于[000-1]的基板方向。第三氮化物半导体含有InycAlxcGa1-xc-ycN（0·xc·1,0,0·yc·1,0,0cc·yc·1）。第三氮化物半导体中的表面侧的a轴长度比基板侧的a轴长短。

35. 发明授权

US08674407B2 Semiconductor device using a group III nitride-based semiconductor 有权
标题翻译：使用III族氮化物基半导体的半导体器件
公开(公告)号：US08674407B2
公开(公告)日：2014-03-18
申请号：US12919640
申请日：2009-03-12
申请人： Yuji Ando , Yasuhiro Okamoto , Kazuki Ota , Takashi Inoue , Tatsuo Nakayama , Hironobu Miyamoto
发明人： Yuji Ando , Yasuhiro Okamoto , Kazuki Ota , Takashi Inoue , Tatsuo Nakayama , Hironobu Miyamoto
IPC分类号： H01L29/66
CPC分类号： H01L29/7783 , H01L29/2003 , H01L29/4236 , H01L29/518 , H01L29/7785
摘要： The present invention provides a semiconductor device having such a structure formed by sequentially laminating a lower barrier layer composed of lattice-relaxed AlxGa1-xN (0≦x≦1), a channel layer composed of InyGa1-yN (0≦y≦1) with compressive strain and a contact layer composed of AlzGa1-zN (0≦z≦1), wherein a two-dimensional electron gas is produced in the vicinity of an interface of said InyGa1-yN channel layer with said AlzGa1-zN contact layer; a gate electrode is formed so as to be embedded in the recessed portion with intervention of an insulating film, which recessed portion is formed by removing a part of said AlzGa1-zN contact layer by etching it away until said InyGa1-yN channel layer is exposed; and, ohmic electrodes are formed on the AlzGa1-zN contact layer. Thus, the semiconductor device has superior uniformity and reproducibility of the threshold voltage while maintaining a low gate leakage current, and is also applicable to the enhancement mode type.
摘要翻译：本发明提供一种具有这样的结构的半导体器件，该半导体器件通过依次层叠由晶格弛豫的Al x Ga 1-x N（0 @ x @ 1）构成的下阻挡层，由InyGa1-yN（0 @ y @ 1）具有压应变和由Al z Ga 1-z N（0 @ z @ 1）组成的接触层，其中在所述In y Ga 1-y N沟道层与所述Al z Ga 1-z N接触层的界面附近产生二维电子气; 通过介入绝缘膜形成嵌入在凹陷部分中的栅电极，该凹陷部分通过蚀刻除去所述AlzGa1-zN接触层的一部分而形成，直到所述In y Ga 1-y N沟道层暴露 ; 并且在AlzGa1-zN接触层上形成欧姆电极。因此，半导体器件在保持低栅极漏电流的同时具有优异的阈值电压的均匀性和再现性，并且也适用于增强型。

36. 发明申请

US20110241075A1 BIPOLAR TRANSISTOR 有权
标题翻译：双极晶体管
公开(公告)号：US20110241075A1
公开(公告)日：2011-10-06
申请号：US13124872
申请日：2009-10-16
申请人： Yuji Ando , Hironobu Miyamoto , Tatsuo Nakayama , Yasuhiro Okamoto , Takashi Inoue , Kazuki Ota
发明人： Yuji Ando , Hironobu Miyamoto , Tatsuo Nakayama , Yasuhiro Okamoto , Takashi Inoue , Kazuki Ota
IPC分类号： H01L29/737
CPC分类号： H01L29/7371 , H01L29/045 , H01L29/2003
摘要： A bipolar transistor includes: a substrate; a collector and a base layer with a p-conductive-type, an emitter layer with an n-conductive-type. The collector layer is formed above the substrate and includes a first nitride semiconductor. The base layer with the p-conductive-type is formed on the collector layer and includes a second nit ride semiconductor. The emitter layer with the n-conductive-type is formed on the base layer and includes a third nitride semiconductor. The collector layer, the base layer and the emitter layer are formed so that crystal growing directions with respect to a surface of the substrate are in parallel to a [0001] direction of the substrate. The first nitride semiconductor includes: InycAlxcGa1-xc-ycN (0≦xc≦1, 0≦yc≦1, 0
摘要翻译：双极晶体管包括：基板; 具有p导电型的集电极和基极层，具有n导电型的发射极层。集电极层形成在衬底上方并且包括第一氮化物半导体。具有p型导电型的基底层形成在集电极层上，并且包括第二耐磨半导体。具有n导电型的发射极层形成在基极层上并且包括第三氮化物半导体。形成集电体层，基极层和发射极层，使得相对于基板的表面的晶体生长方向与基板的[0001]方向平行。第一氮化物半导体包括：InycAlxcGa1-xc-ycN（0＆nlE; xc＆nlE; 1,0＆amp; nlE; yc＆nlE; 1,0

37. 发明授权

US09780738B2 Semiconductor device 有权
公开(公告)号：US09780738B2
公开(公告)日：2017-10-03
申请号：US14239810
申请日：2012-08-21
申请人： Kazuki Ota
发明人： Kazuki Ota
IPC分类号： H03F3/16 , H01L29/40 , H01L29/778 , H01L29/20
CPC分类号： H03F3/16 , H01L29/2003 , H01L29/402 , H01L29/7786
摘要： A semiconductor device is provided with: a field-effect transistor that has a source electrode and a drain electrode that are connected to a semiconductor layer, a gate electrode that is provided on the surface of the semiconductor layer between the source electrode and the drain electrode, and a field plate electrode that is provided on the surface of the semiconductor layer in the vicinity of the gate electrode via an insulating layer, wherein the field-effect transistor amplifies high frequency signals received by the gate electrode to be outputted from the drain electrode; and a voltage dividing circuit that divides a potential difference between the drain electrode and a reference potential GND, and applies a bias voltage such that respective parts of the field plate electrode have a mutually equal potential.

38. 发明授权

US08853666B2 Field effect transistor, and multilayered epitaxial film for use in preparation of field effect transistor 有权
标题翻译：场效应晶体管和用于制备场效应晶体管的多层外延膜
公开(公告)号：US08853666B2
公开(公告)日：2014-10-07
申请号：US12159599
申请日：2006-10-25
申请人： Takashi Inoue , Tatsuo Nakayama , Yuji Ando , Yasuhiro Murase , Kazuki Ota , Hironobu Miyamoto , Katsumi Yamanoguchi , Naotaka Kuroda , Akio Wakejima , Yasuhiro Okamoto
发明人： Takashi Inoue , Tatsuo Nakayama , Yuji Ando , Yasuhiro Murase , Kazuki Ota , Hironobu Miyamoto , Katsumi Yamanoguchi , Naotaka Kuroda , Akio Wakejima , Yasuhiro Okamoto
IPC分类号： H01L29/06 , H01L29/15 , H01L29/778 , H01L29/423 , H01L29/20
CPC分类号： H01L29/7783 , H01L29/0607 , H01L29/155 , H01L29/2003 , H01L29/205 , H01L29/42316 , H01L29/7787
摘要： In a group III nitride-type field effect transistor, the present invention reduces a leak current component by conduction of residual carriers in a buffer layer, and achieves improvement in a break-down voltage, and enhances a carrier confinement effect (carrier confinement) of a channel to improve pinch-off characteristics (to suppress a short channel effect). For example, when applying the present invention to a GaN-type field effect transistor, besides GaN of a channel layer, a composition-modulated (composition-gradient) AlGaN layer in which aluminum composition reduces toward a top gradually or stepwise is used as a buffer layer (hetero buffer). To gate length Lg of a FET to be prepared, a sum a of layer thicknesses of an electron supply layer and a channel layer is selected so as to fulfill Lg/a≧5, and in such a case, the layer thickness of the channel layer is selected in a range of not exceeding 5 times (about 500 Å) as long as a de Broglie wavelength of two-dimensional electron gas accumulated in the channel layer in room temperature.
摘要翻译：在III族氮化物型场效应晶体管中，本发明通过缓冲层中的残留载流子的传导来减少漏电流成分，并且可以实现击穿电压的提高，并提高载流子限制效应（载流子限制）提高夹断特性的通道（抑制短路效应）。例如，当将本发明应用于GaN型场效应晶体管时，除了沟道层的GaN之外，使用其中铝组成逐渐或逐步朝向顶部的组分调制（组成梯度）AlGaN层用作缓冲层（杂质缓冲液）。对于要制备的FET的栅极长度Lg，选择电子供给层和沟道层的层厚度的和a以满足Lg /a≥5，并且在这种情况下，沟道的层厚度只要在室温下积聚在通道层中的二维电子气的德布罗意波长，不超过5倍（约500）的范围内选择层。

39. 发明授权

US08618578B2 Field effect transistor 有权
标题翻译：场效应晶体管
公开(公告)号：US08618578B2
公开(公告)日：2013-12-31
申请号：US13147676
申请日：2010-02-03
申请人： Kazuki Ota , Yasuhiro Okamoto , Hironobu Miyamoto
发明人： Kazuki Ota , Yasuhiro Okamoto , Hironobu Miyamoto
IPC分类号： H01L29/66
CPC分类号： H01L29/4236 , H01L29/1029 , H01L29/2003 , H01L29/42316 , H01L29/66462 , H01L29/66621 , H01L29/7783 , H01L29/7787
摘要： A field effect transistor includes a nitride-based semiconductor multi-layer structure, a source electrode (108), a drain electrode (109), a protective film (110), and a gate electrode (112) that is provided in a recess structure, which is formed by etching, directly or with a gate insulating film interposed therebetween. The nitride-based semiconductor multi-layer structure includes at least a base layer (103) made of AlXGa1-XN (0≦1), a channel layer (104) made of GaN or InGaN, a first electron supply layer (105), which is an undoped or n-type AlYGa1-YN layer, a threshold value control layer (106), which is an undoped AlZGa1-ZN layer, and a second electron supply layer (107), which is an undoped or n-type AlWGa1-WN layer, epitaxially grown in this order on a substrate (101) with a buffer layer (102) interposed therebetween. The Al composition of each layer in the nitride-based semiconductor multi-layer structure satisfies 0
摘要翻译：场效应晶体管包括氮化物基半导体多层结构，源电极（108），漏电极（109），保护膜（110）和设置在凹槽结构中的栅电极（112），其通过蚀刻直接形成，或者在其间插入栅极绝缘膜。所述氮化物系半导体多层结构至少包括由Al x Ga 1-x N（0 1）构成的基极层（103），由GaN或InGaN构成的沟道层（104），第1电子供给层（105）其是未掺杂的或n型AlYGa1-YN层，作为未掺杂的AlZGa1-ZN层的阈值控制层（106）和作为未掺杂的或n型AlWGa1的第二电子供给层（107） -WN层，在衬底（101）上依次外延生长，缓冲层（102）插入其间。氮化物类半导体多层结构中的各层的Al组成满足0

40. 发明授权

US08466495B2 Field effect transistor with reduced gate leakage current 有权
标题翻译：具有减小栅极漏电流的场效应晶体管
公开(公告)号：US08466495B2
公开(公告)日：2013-06-18
申请号：US13468373
申请日：2012-05-10
申请人： Yuji Ando , Hironobu Miyamoto , Tatsuo Nakayama , Yasuhiro Okamoto , Takashi Inoue , Yasuhiro Murase , Kazuki Ota , Akio Wakejima , Naotaka Kuroda
发明人： Yuji Ando , Hironobu Miyamoto , Tatsuo Nakayama , Yasuhiro Okamoto , Takashi Inoue , Yasuhiro Murase , Kazuki Ota , Akio Wakejima , Naotaka Kuroda
IPC分类号： H01L29/80
CPC分类号： H01L29/7787 , H01L29/2003
摘要： Disclosed is an HJFET 110 which comprises: a channel layer 12 composed of InyGa1-yN (0≦y≦1); a carrier supply layer 13 composed of AlxGa1-xN (0≦x≦1), the carrier supply layer 13 being provided over the channel layer 12 and including at least one p-type layer; and a source electrode 15S, a drain electrode 15D and a gate electrode 17 which are disposed facing the channel layer 12 through the p-type layer, and provided over the carrier supply layer 13. The following relational expression is satisfied: 5.6×1011x
摘要翻译：公开了一种HJFET 110，其包括：由In y Ga 1-y N（0 @ y 1）组成的沟道层12; 由Al x Ga 1-x N（0 @ x 1）构成的载流子供给层13，载流子供给层13设置在沟道层12上并且包括至少一个p型层; 以及源极电极15S，漏极电极15D和栅极电极17，其通过p型层面对沟道层12，并且设置在载流子供给层13上。满足以下关系式：5.6×10×11× NA×eta×t [cm-2] <5.6×1013x，其中x表示载体供给层的Al组成比，t表示所述p型层的厚度，NA表示杂质浓度，eta表示活化比。

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