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    • 31. 发明申请
    • Home network system and control method thereof
    • 家庭网络系统及其控制方法
    • US20060178777A1
    • 2006-08-10
    • US11348496
    • 2006-02-06
    • Jong-Ho ParkJae-Seok ParkJun-Ku KimJong-Chang Lee
    • Jong-Ho ParkJae-Seok ParkJun-Ku KimJong-Chang Lee
    • B29C45/00G06F19/00
    • H04L12/2803B25J9/0003H04L12/2818
    • A home network system and a control method thereof. A user with a mobile station at a remote location can control a home robot and monitor security conditions and home appliance conditions at a house via a wireless network. In the home network system, the mobile station is adapted to transmit a control request message for the remote control of the home robot and monitoring-request messages for the monitoring at a house via a first network, and receive control result information related to the home robot control and monitoring information via the first network for display. A server is adapted to analyze the request messages received from the mobile station via the first network, transmit a corresponding request message to the home robot via a second network, and receive the control result information and the monitoring information from the home robot via the second network to transmit to the mobile station.
    • 家庭网络系统及其控制方法。 在远程位置具有移动台的用户可以通过无线网络来控制家庭机器人并监视房屋的安全状况和家电条件。 在家庭网络系统中,移动台适于通过第一网络发送用于家庭机器人的远程控制的控制请求消息和用于在家庭进行监视的监视请求消息,并且接收与家庭相关的控制结果信息 机器人控制和监控信息通过第一个网络进行显示。 服务器适于经由第一网络分析从移动站接收到的请求消息,经由第二网络向家庭机器人发送相应的请求消息,并且经由第二网络从家庭机器人接收控制结果信息和监视信息 网络传输到移动台。
    • 32. 发明授权
    • Methods of manufacturing semiconductor devices having chamfered silicide layers therein
    • 制造其中具有倒角的硅化物层的半导体器件的方法
    • US06740550B2
    • 2004-05-25
    • US10190086
    • 2002-07-03
    • Chang-won ChoiDae-hyuk ChungWoo-sik KimShin-woo NamYeo-cheol YoonBum-su KimJong-ho ParkJi-hwan Choi
    • Chang-won ChoiDae-hyuk ChungWoo-sik KimShin-woo NamYeo-cheol YoonBum-su KimJong-ho ParkJi-hwan Choi
    • H01L218238
    • H01L21/02071H01L21/28114H01L21/32134H01L21/32137H01L21/76897H01L23/5258H01L29/42376H01L2924/0002H01L2924/00
    • A semiconductor device having a chamfered silicide layer and a manufacturing method of the same. The semiconductor device includes: a first insulation layer overlying a semiconductor substrate; gate structures including first conductive layer patterns formed on the first insulation layer, and second conductive layer patterns which are formed on the first conductive layer patterns, wherein the lower sides of the second conductive layer patterns are substantially perpendicular to the major surface of the semiconductor substrate and the upper sides of the second conductive layer patterns are chamfered; and a second insulation layer formed with a first width W on the second conductive layer patterns, wherein the sidewalls of the second insulation layer overhang the upper edges of the second conductive layer patterns. In the semiconductor device manufacture, in forming undercut regions which define the chamfered upper edges of the metal silicide layer patterns, isotropic dry etching is carried out, wherein the isotropic dry etching can be performed simultaneously with ashing of photoresist patterns, or immediately after the ashing process in the same chamber. In either case, after the ashing of the photoresist patterns, an isotropic wet etching can be carried out immediately after performing an existing stripping process, so as to form the undercut regions.
    • 具有倒角硅化​​物层的半导体器件及其制造方法。 半导体器件包括:覆盖半导体衬底的第一绝缘层; 包括形成在第一绝缘层上的第一导电层图案的栅结构和形成在第一导电层图案上的第二导电层图案,其中第二导电层图案的下侧基本垂直于半导体衬底的主表面 并且第二导电层图案的上侧被倒角; 以及在第二导电层图案上形成有第一宽度W的第二绝缘层,其中第二绝缘层的侧壁悬垂在第二导电层图案的上边缘上。 在半导体器件制造中,在形成限定金属硅化物层图案的倒角上边缘的底切区域时,进行各向同性干蚀刻,其中各向同性干蚀刻可以与光致抗蚀剂图案的灰化或灰化之后立即同时进行 过程在同一个房间。 在任一种情况下,在光致抗蚀剂图案的灰化之后,可以在执行现有的剥离工艺之后立即执行各向同性的湿蚀刻,以形成底切区域。
    • 33. 发明授权
    • Method for manufacturing a semiconductor device having a wiring layer
without producing silicon precipitates
    • 制造具有布线层而不产生硅沉淀物的半导体器件的方法
    • US5843842A
    • 1998-12-01
    • US697880
    • 1996-09-03
    • Sang-in LeeJeong-in HongJong-ho Park
    • Sang-in LeeJeong-in HongJong-ho Park
    • H01L23/52H01L21/027H01L21/285H01L21/3205H01L21/768H01L23/485H01L23/522H01L23/532H01L21/441
    • H01L21/76843H01L21/0276H01L21/28512H01L21/76855H01L21/76858H01L21/76864H01L21/76877H01L21/76879H01L23/485H01L23/53223H01L23/53271H01L2924/0002
    • A wiring layer of a semiconductor device having a novel contact structure is disclosed. The semiconductor device includes a semiconductor substrate, an insulating layer having an opening (contact hole) and a first conductive layer formed on the insulating layer which completely fills the opening. The first conductive layer does not produce any Si precipitates in a subsequent heat-treating step for filling the opening with the first conductive layer material. The semiconductor device may further include a second conductive layer having a planarized surface on the first conductive layer. This improves subsequent photolithography. An anti-reflective layer may be formed on the second conductive layer for preventing an unwanted reflection during a photo lithography process. The semiconductor device preferably includes a diffusion barrier layer under the first conductive layer and on the semiconductor substrate, on the insulating layer, and on the inner surface of the opening which prevents a reaction between the first conductive layer and the semiconductor substrate or the insulating layer. A method for forming the wiring layer is also disclosed. Providing a semiconductor device with the wiring layer reduces the leakage current by preventing Al spiking. Since the first conductive layer undergoes a heat-treatment step at a temperature below the melting point, while flowing into the opening and completely filling it with the first conductive layer material, no void is formed in the opening. Good semiconductor device reliability is ensured in spite of the contact hole being less than 1 .mu.m in size and having an aspect ratio greater than 1.0.
    • 公开了具有新型接触结构的半导体器件的布线层。 半导体器件包括半导体衬底,具有开口(接触孔)的绝缘层和形成在绝缘层上的完全填充开口的第一导电层。 在随后的用第一导电层材料填充开口的热处理步骤中,第一导电层不产生任何Si沉淀物。 半导体器件还可以包括在第一导电层上具有平坦化表面的第二导电层。 这改善了随后的光刻。 可以在第二导电层上形成抗反射层,以防止在光刻工艺期间不期望的反射。 半导体器件优选地包括在第一导电层下方,半导体衬底上的绝缘层上的扩散阻挡层,以及防止第一导电层与半导体衬底或绝缘层之间的反应的开口内表面 。 还公开了一种用于形成布线层的方法。 提供具有布线层的半导体器件通过防止Al尖峰来减少漏电流。 由于第一导电层在低于熔点的温度下经历热处理步骤,同时流入开口并用第一导电层材料完全填充,因此在开口中不形成空隙。 尽管接触孔的尺寸小于1μm,并且纵横比大于1.0,确保良好的半导体器件的可靠性。
    • 37. 发明申请
    • METHOD FOR GENERATING SYNTHETIC IMAGE AND ULTRASONIC IMAGING APPARATUS USING SAME
    • 使用合成图像和超声波成像装置生成方法
    • US20140071792A1
    • 2014-03-13
    • US13997848
    • 2011-11-08
    • Yang Mo YooTai-Kyong SongJin Ho ChangJeong ChoJong Ho Park
    • Yang Mo YooTai-Kyong SongJin Ho ChangJeong ChoJong Ho Park
    • G01S15/89
    • G01S15/8904G01S7/52026G01S7/52047G01S15/8915G01S15/8997
    • The present disclosure relates to a method for generating a synthetic image. In the method, image data is generated using a receiving dynamic beamforming method, image data is generated using a synthetic aperture beamforming method, and the image data generated using the receiving dynamic beamforming method and the image data generated using the synthetic aperture beamforming method are synthesized with being applied with weighting factors according to advancing distances of ultrasonic waves. By using a zone blending method, in which image data according to a receiving dynamic beamforming method is mainly used for an ultrasonic image having a predetermined depth or less, and image data according to a synthetic aperture beamforming method is mainly used for an ultrasonic image having any other depth, a grating lobe and distortion of image brightness are eliminated. In addition, the non-uniformity of the image is compensated, and a uniform energy density is acquired even in an area near a virtual transmission sound source.
    • 本公开涉及一种用于产生合成图像的方法。 在该方法中,使用接收动态波束成形方法生成图像数据,使用合成孔径波束成形方法生成图像数据,并且使用接收动态波束成形方法生成的图像数据和使用合成孔径波束成形方法生成的图像数据被合成 根据超声波的行进距离应用加权因子。 通过使用区域混合方法,其中根据接收动态波束成形方法的图像数据主要用于具有预定深度或更小的超声波图像,并且根据合成孔径波束成形方法的图像数据主要用于具有 消除了任何其他深度,光栅和图像亮度的失真。 此外,补偿了图像的不均匀性,并且即使在虚拟透射声源附近的区域也获得均匀的能量密度。
    • 38. 发明申请
    • NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE DEVICE
    • 非易失性存储器件和用于制造器件的方法
    • US20130181278A1
    • 2013-07-18
    • US13608796
    • 2012-09-10
    • Sung-Hun LEESung-Hoi HurJong-Ho Park
    • Sung-Hun LEESung-Hoi HurJong-Ho Park
    • H01L29/792
    • H01L27/1157H01L21/764H01L27/11524H01L29/40114H01L29/40117H01L29/42324H01L29/4234
    • Provided is a non-volatile memory device that includes a substrate including a plurality of active regions extending in a first direction and a plurality of element isolation trenches disposed between the active regions, a plurality of tunnel insulating layer patterns and a plurality of storage layer patterns sequentially disposed on the substrate, a plurality of blocking insulating layers and a plurality of gate electrodes disposed on the storage layer patterns and extending in a second direction perpendicular to the first direction, and first insulating layers including air gaps disposed between the active regions on the element isolation trenches and extending in the first direction, wherein the active regions include first active regions and second active regions adjacent to the first active regions, wherein a width of first air gaps is different from a width of second air gaps.
    • 提供了一种非易失性存储器件,其包括:衬底,其包括在第一方向上延伸的多个有源区和设置在有源区之间的多个元件隔离沟槽;多个隧道绝缘层图案和多个存储层图案 顺序地设置在基板上,多个阻挡绝缘层和多个栅电极,其设置在存储层图案上并沿垂直于第一方向的第二方向延伸,并且第一绝缘层包括设置在第一方向上的有源区之间的气隙 元件隔离沟槽并沿第一方向延伸,其中有源区包括与第一有源区相邻的第一有源区和第二有源区,其中第一气隙的宽度不同于第二气隙的宽度。
    • 40. 发明授权
    • Semiconductor device and method of fabricating the same
    • 半导体装置及其制造方法
    • US08330218B2
    • 2012-12-11
    • US12870913
    • 2010-08-30
    • Jong-ho ParkHyi-Jeong ParkHye-mi KimChang-Ki Jeon
    • Jong-ho ParkHyi-Jeong ParkHye-mi KimChang-Ki Jeon
    • H01L29/76H01L29/94H01L31/062H01L31/113H01L31/119
    • H01L21/8249H01L21/823412H01L21/823418H01L21/823807H01L21/823814H01L27/0623H01L27/0922H01L29/0653H01L29/41766H01L29/456H01L29/66719H01L29/66727H01L29/7809H01L29/7812
    • Provided are a semiconductor device and a method of fabricating the semiconductor device. The semiconductor device using a DMOS device includes: a semiconductor substrate, in which a first conductive type well is formed; a first conductive type gate electrode formed on the semiconductor substrate with a gate insulating layer intervening between the gate electrode and the semiconductor substrate; a second conductive type body electrode formed on the semiconductor substrate and separated from the gate electrode; a first conductive type drain electrode formed on the semiconductor substrate and separated from the gate electrode and the body electrode; a second conductive type first body region formed in the well under the body electrode; a second conductive type second body region extending from the first body region to the gate insulating layer and formed in the well; a first conductive type source region formed in the second body region and extending from the first body region to the gate insulating layer; and a first conductive type source electrode extending from the source region to surround the gate electrode on the semiconductor substrate with an insulating layer intervening between the source electrode and gate electrode.
    • 提供半导体器件和制造半导体器件的方法。 使用DMOS器件的半导体器件包括:形成第一导电型阱的半导体衬底; 形成在所述半导体衬底上的第一导电型栅极电极,所述栅极绝缘层介于所述栅电极和所述半导体衬底之间; 形成在所述半导体基板上并与所述栅电极分离的第二导电型体电极; 形成在所述半导体基板上并与所述栅电极和所述主体电极分离的第一导电型漏电极; 形成在所述体电极下方的所述阱内的第二导电型第一体区域; 第二导电类型的第二主体区域,其从所述第一主体区域延伸到所述栅极绝缘层并形成在所述阱中; 形成在所述第二主体区域中并从所述第一主体区域延伸到所述栅极绝缘层的第一导电型源极区域; 以及第一导电型源电极,其从所述源极区域延伸,以在所述半导体衬底上围绕所述栅极电极,所述绝缘层介于所述源电极和栅电极之间。