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31. 发明申请

US20060111331A1 Gave10 agonists for treating inflammation 审中-公开
标题翻译： Gave10激动剂治疗炎症
公开(公告)号：US20060111331A1
公开(公告)日：2006-05-25
申请号：US10995997
申请日：2004-11-23
申请人： Haifeng Eishingdrelo , Kin Yu , Jidong Cai , Paul Weissensee , Jian Shen
发明人： Haifeng Eishingdrelo , Kin Yu , Jidong Cai , Paul Weissensee , Jian Shen
IPC分类号： A61K31/58
CPC分类号： A61K31/58
摘要： Disclosed is a method for inhibiting TNFα, IL-6, and activating GAVE10, treating, for example, inflammation thereby, the method comprising the step of administering to a subject an effective amount of a compound of the following formula: or a pharmaceutically acceptable salt, solvate, hydrate, or prodrug thereof, wherein B1 and B2 are each independently —OH, (C1-C6)alkyl, or —H; X is Z-K; Z is —CO or —CH2; K is —N(R1)n, —NR1N(R2)n, —NR1R5R2R4, —N(R1)pR2NR3R4, or —N(R1)pR5R2R4 R1, R2, and R3 are each independently (C1-C6)alkyl or absent; n is from 0 to 3; p is from 0 to 2; R4 is absent or is R5 is absent or is
摘要翻译：公开了一种抑制TNFα，IL-6和激活GAVE10，从而治疗例如炎症的方法，所述方法包括向受试者施用有效量的下式化合物或其药学上可接受的盐，其溶剂合物，水合物或前药，其中B 1和B 2各自独立地为-OH，（C 1 -C 3） 6）烷基或-H; X是Z-K; Z是-CO或-CH 2。 K是-N（R 1）n N， - NR 1 N（R 2 N）N R 1，R 2，R 3，R 3，R 3，R 3，R 3， R 1，R 2，R 3，R 3，R 3，R 3，R 3，R 3， 1 2 1 R 2，R 3和R 3各自独立地为（C 1 -C 6 -C 6）烷基或不存在; n为0〜3; p为0〜2; R 4不存在或者R 5不存在或不存在

32. 发明申请

US20050280030A1 Dual gate layout for thin film transistor 有权
标题翻译：薄膜晶体管的双栅极布局
公开(公告)号：US20050280030A1
公开(公告)日：2005-12-22
申请号：US11211606
申请日：2005-08-26
申请人： Wein-Town Sun , Chun-Sheng Li , Jian-Shen Yu
发明人： Wein-Town Sun , Chun-Sheng Li , Jian-Shen Yu
IPC分类号： H01L27/12 , H01L29/423 , H01L29/786 , H01L29/739
CPC分类号： H01L29/78645 , H01L27/12 , H01L29/42384 , H01L29/78621
摘要： A dual gate layout of a thin film transistor of liquid crystal display to alleviate dark current leakage is disclosed. The layout comprises (1) a polysilicon on a substrate having a L-shaped or a snake shaped from top-view, which has a heavily doped source region, a first lightly doped region, a first gate channel, a second lightly doped region, a second gate channel, a third lightly doped region and a heavily doped drain region formed in order therein; (2) a gate oxide layer formed on the polysilicon layer and the substrate, (3) a gate metal layer then formed on the gate oxide layer having a scanning line and an extension portion with a L-shaped or an I-shaped. The gate metal intersects with the polysilicon layer thereto define the forgoing gate channels. Among of gate channels, at least one is along the signal line, which is connected to the source region through a source contact.
摘要翻译：公开了液晶显示器的薄膜晶体管的双栅极布局，以减轻暗电流泄漏。布局包括（1）在基板上具有从顶视图形成的L形或蛇形的多晶硅，其具有重掺杂的源极区，第一轻掺杂区，第一栅极沟道，第二轻掺杂区，第二栅极沟道，第三轻掺杂区和重掺杂漏极区; （2）形成在多晶硅层和基板上的栅极氧化层，（3）然后在栅极氧化物层上形成栅极金属层，栅极氧化物层具有扫描线和具有L形或I形的延伸部分。栅极金属与多晶硅层相交，限定了前述栅极沟道。在栅极通道中，沿着信号线至少有一个通过源极接触连接到源极区域。

33. 发明授权

US06972594B2 Level-shifting circuit 有权
标题翻译：电平转换电路
公开(公告)号：US06972594B2
公开(公告)日：2005-12-06
申请号：US10615464
申请日：2003-07-07
申请人： Jian-Shen Yu
发明人： Jian-Shen Yu
IPC分类号： H03K3/356 , H03K19/0175 , H03K19/094
CPC分类号： H03K3/356104
摘要： A level-shifting circuit comprising an enable circuit is disclosed. The level modulating circuit includes an input terminal and an inverse input terminal for respectively receiving a complementary pair of small signals, and a first output terminal for outputting a voltage level in response to the complementary pair of small signals. The enable circuit is coupled to the first output terminal and makes the first output terminal output a predetermined voltage level signal when receiving a disable signal.
摘要翻译：公开了一种包括使能电路的电平移动电路。电平调制电路包括用于分别接收互补的一对小信号的输入端子和反相输入端子，以及用于响应互补的一对小信号而输出电压电平的第一输出端子。使能电路耦合到第一输出端子，并且当接收到禁止信号时使第一输出端子输出预定的电压电平信号。

34. 发明授权

US06956552B2 Method and apparatus for driving a display 有权
标题翻译：用于驱动显示器的方法和装置
公开(公告)号：US06956552B2
公开(公告)日：2005-10-18
申请号：US10294164
申请日：2002-11-14
申请人： Jian-Shen Yu
发明人： Jian-Shen Yu
IPC分类号： G02F1/133 , G09G3/20 , G09G3/36
CPC分类号： G09G3/3677 , G09G3/3614 , G09G3/3659 , G09G2310/065 , G09G2330/021
摘要： A method for driving a display having display cells with capacitors coupled to gate lines. The method comprises the steps of floating the gates of the transistors of the Nth and (N+1)th display cell, applying a high voltage level to the gate of the transistor of the Nth display cell to turn it on and keeping the gate of the transistor of the (N+1)th display cell floated, applying a low voltage level to the gate of the transistor of the Nth display cell to turn it off and the first voltage level to the gate of the transistor of the (N+1)th display cell to turn it on, and floating the gate of the transistor of the Nth display cell and applying the low voltage level to the gate of the transistor of the (N+1)th display cell to turn it off.
摘要翻译：一种用于驱动具有与栅极线耦合的电容器的显示单元的显示器的方法。该方法包括以下步骤：浮置第N和第（N + 1）个显示单元的晶体管的栅极，向第N个显示单元的晶体管的栅极施加高电压电平，将其导通并保持第（N + 1）个显示单元的晶体管浮起来，向第N个显示单元的晶体管的栅极施加低电压电平，将其截止，并将第（N + 1）个显示单元的晶体管的栅极施加第一电压电平， 1）显示单元将其导通，并且浮置第N个显示单元的晶体管的栅极并将低电压电平施加到第（N + 1）个显示单元的晶体管的栅极以使其截止。

35. 发明授权

US06953788B1 3-mercaptoacetylamino-1,5-substituted-2-oxo-azepan derivatives useful as inhibitors of matrix metalloproteinase 失效
标题翻译：可用作基质金属蛋白酶抑制剂的3-巯基乙酰氨基-1,5-取代-2-氧代氮杂环庚烷衍生物
公开(公告)号：US06953788B1
公开(公告)日：2005-10-11
申请号：US08893080
申请日：1997-12-19
申请人： Alan M. Warshawsky , Joseph T. Tsay , Michael J. Janusz , Jian Shen , Gary A. Flynn , Ramalinga M. Dharanipragada , Joseph P. Burkhart , Douglas W. Beight , Meena V. Patel
发明人： Alan M. Warshawsky , Joseph T. Tsay , Michael J. Janusz , Jian Shen , Gary A. Flynn , Ramalinga M. Dharanipragada , Joseph P. Burkhart , Douglas W. Beight , Meena V. Patel
IPC分类号： A61K31/55 , A61P19/02 , C07D223/12 , C07D243/00 , C07D243/08 , C07D401/00 , C07D403/12
CPC分类号： C07D403/12 , C07D223/12 , C07D243/08
摘要： The present invention relates to certain novel 3-mercaptoacetylamino-1,5-substituted-2-oxo-azepan derivatives useful as inhibitors of matrix metalloproteinase. Pharmaceutical compositions containing said compounds as well as methods of treating various disease states responding to inhibition of matrix metalloproteinase are also claimed herein.
摘要翻译：本发明涉及可用作基质金属蛋白酶抑制剂的某些新型3-巯基乙酰基氨基-1,5-取代-2-氧代氮杂环庚烷衍生物。本文还要求含有所述化合物的药物组合物以及治疗对基质金属蛋白酶抑制作用的各种疾病状态的方法。

36. 发明申请

US20050164711A1 Apparatus and method for suppressing mechanical resonance in a mass transit vehicle 有权
标题翻译：用于抑制集体运输车辆中的机械共振的装置和方法
公开(公告)号：US20050164711A1
公开(公告)日：2005-07-28
申请号：US10765251
申请日：2004-01-27
申请人： Jian Shen , Fred Marton , Linda Clawson , Kenneth Karg
发明人： Jian Shen , Fred Marton , Linda Clawson , Kenneth Karg
IPC分类号： G05D1/00 , G05D19/02
CPC分类号： G05D19/02
摘要： A mass transit vehicle traction motor control system includes an automatic control block for receiving and processing a tachometer signal having a first resonance signal superimposed thereon to produce a rate request signal having a corresponding second resonance signal superimposed thereon. A filter is provided for decreasing an amplitude of the second resonance signal whereupon the rate request signal is isolated therefrom. A communication and control block and a propulsion and control block co-act to process the isolated rate request signal to produce a speed control signal that is configured to cause a traction motor of a mass transit vehicle to provide motive force to the mass transit vehicle at a rate related to the value of the speed control signal.
摘要翻译：公共交通工具牵引电动机控制系统包括：自动控制块，用于接收和处理具有叠加在其上的第一谐振信号的转速计信号，以产生具有叠加在其上的对应的第二谐振信号的速率请求信号。提供了一个滤波器，用于减小第二谐振信号的幅度，因此速率请求信号被隔离。通信和控制块以及推进和控制块协同处理隔离速率请求信号以产生速度控制信号，该速度控制信号被配置成使公共交通车辆的牵引电动机向公共交通车辆提供动力与速度控制信号的值相关的速率。

37. 发明授权

US06894755B2 Liquid crystal display device integrating driving circuit on matrix substrate 有权
标题翻译：在矩阵基板上集成驱动电路的液晶显示装置
公开(公告)号：US06894755B2
公开(公告)日：2005-05-17
申请号：US10410769
申请日：2003-04-10
申请人： Jian-Shen Yu
发明人： Jian-Shen Yu
IPC分类号： G02F1/1343 , G02F1/1362 , G09G3/30
CPC分类号： G02F1/134309 , G02F1/1362
摘要： A liquid crystal display (LCD) device integrating driving circuit on an active-matrix substrate. A common electrode disposed on a counter substrate has an opening slit corresponding to a clock line disposed on the matrix substrate, thereby eliminating parasitic capacitance between the clock line and the common electrode.
摘要翻译：一种在有源矩阵基板上集成驱动电路的液晶显示器（LCD）装置。配置在对置基板上的公共电极具有与设置在矩阵基板上的时钟线对应的开口狭缝，从而消除了时钟线与公共电极之间的寄生电容。

38. 发明申请

US20050088397A1 [CLOCK SIGNAL AMPLIFYING METHOD AND DRIVING STAGE FOR LCD DRIVING CIRCUIT ] 有权
标题翻译： [LCD驱动电路的时钟信号放大方法和驱动阶段]
公开(公告)号：US20050088397A1
公开(公告)日：2005-04-28
申请号：US10708178
申请日：2004-02-13
申请人： Jian-Shen Yu , Shih-Chian Liu
发明人： Jian-Shen Yu , Shih-Chian Liu
IPC分类号： G09G3/20 , G09G3/36
CPC分类号： G09G3/2096 , G09G3/3688 , G09G2310/0289 , G09G2330/021
摘要： A clock signal amplifying method and driving stage for LCD driving circuit is provided. The driving stage includes a clock input, a level shifter, and an output buffer. Firstly, the clock input receives a cock signal oscillating between a high original level and a low original level. Thereafter, a level shifter is biased at a high target level and a low target level, and amplifies the clock signal to a relay signal, which oscillates between a high relay level and a low relay level. Lastly, the output buffer is biased at the high relay level and the low relay level for amplifying the relay signal to a target signal, which oscillates between the high target level and the low target level.
摘要翻译：提供了用于LCD驱动电路的时钟信号放大方法和驱动级。驱动级包括时钟输入，电平移位器和输出缓冲器。首先，时钟输入接收在高原始电平和低原始电平之间振荡的旋转信号。此后，电平移位器被偏置在高目标电平和低目标电平，并且将时钟信号放大到在高继电器电平和低继电器电平之间振荡的继电器信号。最后，输出缓冲器被偏置在高继电器电平和低继电器电平，用于将继电器信号放大到目标信号，该目标信号在高目标电平和低目标电平之间振荡。

39. 发明授权

US06813331B1 Bi-directional shift-register circuit 有权
标题翻译：双向移位寄存器电路
公开(公告)号：US06813331B1
公开(公告)日：2004-11-02
申请号：US10733096
申请日：2003-12-11
申请人： Jian-Shen Yu , Shi-Hsiang Lu , Chung-Hong Kuo
发明人： Jian-Shen Yu , Shi-Hsiang Lu , Chung-Hong Kuo
IPC分类号： G11C1900
CPC分类号： G11C19/28 , G11C19/00
摘要： A bi-directional shift-register circuit for outputting data in different turns and reducing the power loss according to a low-voltage clock signal, a first directional signal, and a second directional signal.
摘要翻译：一种双向移位寄存器电路，用于输出不同匝数的数据，并根据低电压时钟信号，第一定向信号和第二定向信号降低功率损耗。

40. 发明授权

US06784711B2 Sequential pulse train generator 有权
公开(公告)号：US06784711B2
公开(公告)日：2004-08-31
申请号：US10600785
申请日：2003-06-19
申请人： Jian-Shen Yu
发明人： Jian-Shen Yu
IPC分类号： H03K702
CPC分类号： G11C19/184 , G09G3/3677 , G09G2310/0289 , G09G2330/021 , G11C19/00 , G11C19/28
摘要： A sequential pulse train generator. Each stage of the sequential pulse train generator includes a dynamic shift register circuit, level shifter, and buffer composed of inverters. The dynamic shift register circuits, allow the pulse generator to operate with a low-voltage clock signal so that power consumption in transmission of the clock signal is reduced.

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