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31. 发明授权

US08711505B2 Storage device having clock adjustment circuitry with firmware-based predictive correction 有权
标题翻译：存储设备具有基于固件的预测校正的时钟调整电路
公开(公告)号：US08711505B2
公开(公告)日：2014-04-29
申请号：US13306320
申请日：2011-11-29
申请人： Jeffrey P. Grundvig , Jason D. Byrne
发明人： Jeffrey P. Grundvig , Jason D. Byrne
IPC分类号： G11B5/09
CPC分类号： G11B20/10509 , G11B20/10222 , G11B2220/20
摘要： A hard disk drive or other disk-based storage device comprises a storage disk, a read/write head configured to read data from and write data to the storage disk, and control circuitry coupled to the read/write head and configured to process data received from and supplied to the read/write head. The control circuitry comprises clock adjustment circuitry configured to generate a control signal for adjusting a parameter of a clock signal based at least in part on timing information obtained by detecting a timing pattern on a surface of the storage disk. The control signal is generated utilizing at least a predictive correction control loop, with the clock adjustment circuitry comprising predictive control firmware that implements at least a portion of the predictive correction control loop.
摘要翻译：硬盘驱动器或其他基于磁盘的存储设备包括存储盘，被配置为从存储盘读取数据并将数据写入存储盘的读/写头，以及耦合到读/写头并被配置为处理接收到的数据的控制电路从读取/写入头提供。控制电路包括时钟调整电路，其被配置为至少部分地基于通过检测存储盘表面上的定时模式获得的定时信息来产生用于调整时钟信号的参数的控制信号。控制信号是利用至少一个预测校正控制环来产生的，其中时钟调整电路包括实现预测校正控制环路的至少一部分的预测控制固件。

32. 发明授权

US08526131B2 Systems and methods for signal polarity determination 有权
标题翻译：用于信号极性确定的系统和方法
公开(公告)号：US08526131B2
公开(公告)日：2013-09-03
申请号：US12955789
申请日：2010-11-29
申请人： Viswanath Annampedu , Jeffrey P. Grundvig , Keith R. Bloss , Vishal Narielwala
发明人： Viswanath Annampedu , Jeffrey P. Grundvig , Keith R. Bloss , Vishal Narielwala
IPC分类号： G11B5/09
CPC分类号： G11B5/59688 , G11B5/09 , G11B5/59655 , G11B20/10009 , G11B20/10435
摘要： Various embodiments of the present invention provide systems and methods for determining head polarity. As an example, a head polarity detection circuit includes: a first computation circuit, a second computation circuit, and an inversion determination circuit. The first computation circuit is operable to sum an absolute value of each sample of a first subset of a series of data samples corresponding to a first phase of an analog input to yield a first sum, and the second computation circuit is operable to sum an absolute value of each sample of a second subset of the series of data samples corresponding to a second phase of the analog input to yield a second sum. The first phase is more than ninety degrees offset from the second phase.
摘要翻译：本发明的各种实施例提供了用于确定磁头极性的系统和方法。作为例子，头极性检测电路包括：第一计算电路，第二计算电路和反转确定电路。第一计算电路可操作地对应于与模拟输入的第一相位相对应的一系列数据样本的第一子集的每个样本的绝对值，以产生第一和，并且第二计算电路可操作以将绝对值所述一系列数据样本的第二子集的每个采样值对应于模拟输入的第二相，以产生第二和。第一阶段与第二阶段偏离九十度。

33. 发明申请

US20130077188A1 Systems and Methods for Controlled Wedge Spacing in a Storage Device 有权
标题翻译：存储设备中控制楔形间距的系统和方法
公开(公告)号：US20130077188A1
公开(公告)日：2013-03-28
申请号：US13242983
申请日：2011-09-23
申请人： Jeffrey P. Grundvig
发明人： Jeffrey P. Grundvig
IPC分类号： G11B5/09
CPC分类号： G11B20/1403 , G11B5/5965 , G11B20/10222
摘要： Various embodiments of the present invention provide systems and methods for data processing. For example, some embodiments of the present invention provide clock generation systems that include: a first clock multiplier circuit, a second clock multiplier circuit, a modulus accumulator circuit, and a data clock phase control circuit. The first clock multiplier circuit is operable to multiply a reference clock by a first multiplier to yield a first domain clock, and the second clock multiplier circuit is operable to multiply the reference clock by a second multiplier to yield a second domain clock. The modulus accumulator circuit is operable to yield a value indicating a fractional amount of the second domain clock that an edge of the second domain clock is offset from a trigger signal. The data clock phase control circuit is operable to phase shift the second domain clock by a phase amount corresponding to the fractional amount.
摘要翻译：本发明的各种实施例提供了用于数据处理的系统和方法。例如，本发明的一些实施例提供了时钟产生系统，其包括：第一时钟乘法器电路，第二时钟乘法器电路，模数累加器电路和数据时钟相位控制电路。第一时钟乘法器电路可操作以将参考时钟乘以第一乘法器以产生第一域时钟，并且第二时钟乘法器电路可操作以将参考时钟乘以第二乘法器以产生第二域时钟。模数累加器电路可操作以产生指示第二域时钟的边缘与触发信号偏移的第二域时钟的分数量的值。数据时钟相位控制电路可操作以将第二域时钟相移相应于分数量的相位量。

34. 发明申请

US20120134042A1 Systems and Methods for Signal Polarity Determination 有权
标题翻译：信号极性测定系统与方法
公开(公告)号：US20120134042A1
公开(公告)日：2012-05-31
申请号：US12955789
申请日：2010-11-29
申请人： Viswanath Annampedu , Jeffrey P. Grundvig , Keith R. Bloss , Vishal Narielwala
发明人： Viswanath Annampedu , Jeffrey P. Grundvig , Keith R. Bloss , Vishal Narielwala
IPC分类号： G11B27/36
CPC分类号： G11B5/59688 , G11B5/09 , G11B5/59655 , G11B20/10009 , G11B20/10435
摘要： Various embodiments of the present invention provide systems and methods for determining head polarity. As an example, a head polarity detection circuit includes: a first computation circuit, a second computation circuit, and an inversion determination circuit. The first computation circuit is operable to sum an absolute value of each sample of a first subset of a series of data samples corresponding to a first phase of an analog input to yield a first sum, and the second computation circuit is operable to sum an absolute value of each sample of a second subset of the series of data samples corresponding to a second phase of the analog input to yield a second sum. The first phase is more than ninety degrees offset from the second phase.
摘要翻译：本发明的各种实施例提供了用于确定磁头极性的系统和方法。作为例子，头极性检测电路包括：第一计算电路，第二计算电路和反转确定电路。第一计算电路可操作地对应于与模拟输入的第一相位相对应的一系列数据样本的第一子集的每个样本的绝对值，以产生第一和，并且第二计算电路可操作以将绝对值所述一系列数据样本的第二子集的每个采样值对应于模拟输入的第二相，以产生第二和。第一阶段与第二阶段偏离九十度。

35. 发明授权

US08174784B2 Systems and methods for inter-location control of storage access 有权
标题翻译：存储访问的位置间控制的系统和方法
公开(公告)号：US08174784B2
公开(公告)日：2012-05-08
申请号：US12527311
申请日：2007-10-30
申请人： Jeffrey P. Grundvig , Richard Rauschmayer , Timothy T. Ding
发明人： Jeffrey P. Grundvig , Richard Rauschmayer , Timothy T. Ding
IPC分类号： G11B5/09 , G11B5/596
CPC分类号： G11B5/09 , G11B20/10 , G11B20/10222 , G11B2020/1267 , G11B2020/1281 , G11B2220/2516
摘要： Various embodiments of the present invention provide systems and methods for controlling access to a magnetic storage medium. As one example, a method for controlling access to a magnetic storage medium is disclosed that includes providing a location count indicating a location between a portion of a first servo data sector of a magnetic storage media and a portion of a second servo data sector of the magnetic storage media, and asserting an enable window signal based upon the location count.
摘要翻译：本发明的各种实施例提供了用于控制对磁存储介质的访问的系统和方法。作为一个示例，公开了一种用于控制对磁存储介质的访问的方法，其包括提供指示磁存储介质的第一伺服数据扇区的一部分与第二伺服数据扇区的部分之间的位置的位置计数磁存储介质，并且基于位置计数来确定使能窗口信号。

36. 发明授权

US08059349B2 Methods and systems for estimating time corresponding to peak signal amplitude 有权
标题翻译：用于估计对应于峰值信号幅度的时间的方法和系统
公开(公告)号：US08059349B2
公开(公告)日：2011-11-15
申请号：US12772085
申请日：2010-04-30
申请人： Viswanath Annampedu , Keith R. Bloss , Tianyang Ding , Jeffrey P. Grundvig , Roy S. Neville
发明人： Viswanath Annampedu , Keith R. Bloss , Tianyang Ding , Jeffrey P. Grundvig , Roy S. Neville
IPC分类号： G11B5/09 , G11B21/02
CPC分类号： G11B20/10009 , G11B5/59661 , G11B5/59666 , G11B2020/1282
摘要： Various systems and methods for peak signal detection. As one example, a method for peak signal detection that includes receiving a signal is disclosed. The received signal includes a signal region where the signal is increasing in amplitude, another signal region where the signal is decreasing in amplitude, and a transitional signal region coupling the first two signal regions. In some cases, the transitional region is of zero duration and the signal transitions directly from the increasing region to the decreasing region. The method further include calculating a distance between the signal region of increasing amplitude and the signal region of decreasing amplitude, and determining a peak of the received signal that is one half the distance from the signal region of increasing amplitude.
摘要翻译：用于峰值信号检测的各种系统和方法。作为一个示例，公开了一种包括接收信号的峰值信号检测方法。接收到的信号包括信号幅度增加的信号区域，信号幅度减小的另一个信号区域以及耦合前两个信号区域的过渡信号区域。在某些情况下，过渡区域为零持续时间，信号直接从增加区域转移到减少区域。该方法还包括计算增加振幅的信号区域和幅度减小的信号区域之间的距离，以及确定接收信号的峰值是与增加振幅的信号区域的距离的一半。

37. 发明授权

US08049982B1 Methods and apparatus for measuring servo address mark distance in a read channel using selective fine phase estimate 有权
标题翻译：使用选择性精细相位估计在读通道中测量伺服地址标记距离的方法和装置
公开(公告)号：US08049982B1
公开(公告)日：2011-11-01
申请号：US12847676
申请日：2010-07-30
申请人： Jeffrey P. Grundvig , Viswanath Annampedu , Xun Zhang
发明人： Jeffrey P. Grundvig , Viswanath Annampedu , Xun Zhang
IPC分类号： G11B5/09
CPC分类号： G11B20/10009 , G11B20/10037 , G11B20/10074 , G11B20/1024 , G11B20/10277 , G11B20/14 , G11B2020/10916 , G11B2020/1281 , G11B2020/1484 , G11B2220/2516
摘要： Methods and apparatus are provided for measuring servo address mark distance in a read channel using selective fine phase estimates. A distance between servo address marks (SAMs) in servo data of a magnetic recording media can be computed by obtaining a count of a number of time intervals between SAM patterns; obtaining a plurality of fractional phase estimates; selecting at least one of the plurality of fractional phase estimates as a selected fractional phase estimate based on a selection criteria; and combining the count and the selected fractional phase estimate to compute the distance. The fractional phase estimates can include a first fractional phase estimate having a lower resolution and higher accuracy in the presence of frequency errors relative to a second fractional phase estimate and wherein the second fractional phase estimate has more resolution and lower accuracy in the presence of the frequency errors relative to the first fractional phase estimate. The selection criteria can comprise a frequency error threshold.
摘要翻译：提供了使用选择性精细相位估计来测量读取通道中的伺服地址标记距离的方法和装置。可以通过获得SAM图案之间的时间间隔数的计数来计算磁记录介质的伺服数据中的伺服地址标记（SAM）之间的距离; 获得多个分数阶段估计; 基于选择标准来选择所述多个分数阶段估计中的至少一个作为选择的分数阶段估计; 并结合计数和所选择的分数相位估计来计算距离。分数阶段估计可以包括在存在相对于第二分数阶段估计的频率误差的情况下具有较低分辨率和较高精度的第一分数相位估计，并且其中第二分数相位估计在频率存在的情况下具有更高的分辨率和更低的精度相对于第一分数阶段估计的误差。选择标准可以包括频率误差阈值。

38. 发明授权

US07738200B2 Systems and methods for estimating time corresponding to peak signal amplitude 有权
标题翻译：用于估计对应于峰值信号幅度的时间的系统和方法
公开(公告)号：US07738200B2
公开(公告)日：2010-06-15
申请号：US11415819
申请日：2006-05-01
申请人： Viswanath Annampedu , Keith R. Bloss , Tianyang Ding , Jeffrey P. Grundvig , Roy S. Neville
发明人： Viswanath Annampedu , Keith R. Bloss , Tianyang Ding , Jeffrey P. Grundvig , Roy S. Neville
IPC分类号： G11B5/09 , G11B21/02
CPC分类号： G11B20/10009 , G11B5/59661 , G11B5/59666 , G11B2020/1282
摘要： Various systems and methods for peak signal detection. As one example, a method for peak signal detection that includes receiving a signal is disclosed. The received signal includes a signal region where the signal is increasing in amplitude, another signal region where the signal is decreasing in amplitude, and a transitional signal region coupling the first two signal regions. In some cases, the transitional region is of zero duration and the signal transitions directly from the increasing region to the decreasing region. The method further include calculating a distance between the signal region of increasing amplitude and the signal region of decreasing amplitude, and determining a peak of the received signal that is one half the distance from the signal region of increasing amplitude.
摘要翻译：用于峰值信号检测的各种系统和方法。作为一个示例，公开了一种包括接收信号的峰值信号检测方法。接收到的信号包括信号幅度增加的信号区域，信号幅度减小的另一个信号区域以及耦合前两个信号区域的过渡信号区域。在某些情况下，过渡区域为零持续时间，信号直接从增加区域转移到减少区域。该方法还包括计算增加振幅的信号区域和幅度减小的信号区域之间的距离，以及确定接收信号的峰值是与增加振幅的信号区域的距离的一半。

39. 发明申请

US20100142078A1 Systems and Methods for Memory Efficient Repeatable Run Out Processing 有权
标题翻译：用于存储器高效重复运行处理的系统和方法
公开(公告)号：US20100142078A1
公开(公告)日：2010-06-10
申请号：US12328024
申请日：2008-12-04
申请人： Viswanath Annampedu , Terence Karanink , Xun Zhang , Jeffrey P. Grundvig
发明人： Viswanath Annampedu , Terence Karanink , Xun Zhang , Jeffrey P. Grundvig
IPC分类号： G11B5/09
CPC分类号： G11B5/59627
摘要： Various embodiments of the present invention provide systems and methods for low overhead disk wobble compensation. As an example, a method for performing synchronous wobble compensation processing is disclosed. The method includes providing a medium that includes a servo data region and a user data region. The servo data region includes a clock recovery pattern and a location pattern. A detectable pattern is written to the user data region a known number of bit periods from the location pattern. The detectable pattern is read back, and a fractional processing delay is calculated. Based at least on the fractional processing delay and a known number of bit periods from the location pattern to the end of the servo data region, a wobble compensation pattern is written an integral number of bit periods from the location pattern.
摘要翻译：本发明的各种实施例提供了用于低架空磁盘摆动补偿的系统和方法。作为示例，公开了一种用于执行同步摆动补偿处理的方法。该方法包括提供包括伺服数据区和用户数据区的介质。伺服数据区域包括时钟恢复模式和位置模式。将可检测图案从位置图案写入用户数据区域已知数量的位周期。读取可检测图案，并计算分数处理延迟。至少基于分数处理延迟和从位置模式到伺服数据区域的结束的已知数量的位周期，摆动补偿模式从位置模式写入整数个位周期。

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