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1. 发明授权

US08711505B2 Storage device having clock adjustment circuitry with firmware-based predictive correction 有权
标题翻译：存储设备具有基于固件的预测校正的时钟调整电路
公开(公告)号：US08711505B2
公开(公告)日：2014-04-29
申请号：US13306320
申请日：2011-11-29
申请人： Jeffrey P. Grundvig , Jason D. Byrne
发明人： Jeffrey P. Grundvig , Jason D. Byrne
IPC分类号： G11B5/09
CPC分类号： G11B20/10509 , G11B20/10222 , G11B2220/20
摘要： A hard disk drive or other disk-based storage device comprises a storage disk, a read/write head configured to read data from and write data to the storage disk, and control circuitry coupled to the read/write head and configured to process data received from and supplied to the read/write head. The control circuitry comprises clock adjustment circuitry configured to generate a control signal for adjusting a parameter of a clock signal based at least in part on timing information obtained by detecting a timing pattern on a surface of the storage disk. The control signal is generated utilizing at least a predictive correction control loop, with the clock adjustment circuitry comprising predictive control firmware that implements at least a portion of the predictive correction control loop.
摘要翻译：硬盘驱动器或其他基于磁盘的存储设备包括存储盘，被配置为从存储盘读取数据并将数据写入存储盘的读/写头，以及耦合到读/写头并被配置为处理接收到的数据的控制电路从读取/写入头提供。控制电路包括时钟调整电路，其被配置为至少部分地基于通过检测存储盘表面上的定时模式获得的定时信息来产生用于调整时钟信号的参数的控制信号。控制信号是利用至少一个预测校正控制环来产生的，其中时钟调整电路包括实现预测校正控制环路的至少一部分的预测控制固件。

2. 发明申请

US20130135766A1 STORAGE DEVICE HAVING CLOCK ADJUSTMENT CIRCUITRY WITH FIRMWARE-BASED PREDICTIVE CORRECTION 有权
标题翻译：具有基于固定预测校正的时钟调整电路的存储设备
公开(公告)号：US20130135766A1
公开(公告)日：2013-05-30
申请号：US13306320
申请日：2011-11-29
申请人： Jeffrey P. Grundvig , Jason D. Byrne
发明人： Jeffrey P. Grundvig , Jason D. Byrne
IPC分类号： G11B27/10
CPC分类号： G11B20/10509 , G11B20/10222 , G11B2220/20
摘要： A hard disk drive or other disk-based storage device comprises a storage disk, a read/write head configured to read data from and write data to the storage disk, and control circuitry coupled to the read/write head and configured to process data received from and supplied to the read/write head. The control circuitry comprises clock adjustment circuitry configured to generate a control signal for adjusting a parameter of a clock signal based at least in part on timing information obtained by detecting a timing pattern on a surface of the storage disk. The control signal is generated utilizing at least a predictive correction control loop, with the clock adjustment circuitry comprising predictive control firmware that implements at least a portion of the predictive correction control loop.
摘要翻译：硬盘驱动器或其他基于磁盘的存储设备包括存储盘，被配置为从存储盘读取数据并将数据写入存储盘的读/写头，以及耦合到读/写头并被配置为处理接收到的数据的控制电路从读取/写入头提供。控制电路包括时钟调整电路，其被配置为至少部分地基于通过检测存储盘表面上的定时模式获得的定时信息来产生用于调整时钟信号的参数的控制信号。控制信号是利用至少一个预测校正控制环来产生的，其中时钟调整电路包括实现预测校正控制环路的至少一部分的预测控制固件。

3. 发明授权

US08498071B2 Systems and methods for inter-track alignment 有权
标题翻译：用于轨道间对准的系统和方法
公开(公告)号：US08498071B2
公开(公告)日：2013-07-30
申请号：US13173088
申请日：2011-06-30
申请人： Jeffrey P. Grundvig , Jason D. Byrne , Jefferson Singleton
发明人： Jeffrey P. Grundvig , Jason D. Byrne , Jefferson Singleton
IPC分类号： G11B27/36 , G11B5/09
CPC分类号： G11B20/10435 , G11B5/59616 , G11B5/59627 , G11B19/045 , G11B2020/1282 , G11B2020/1287 , G11B2220/2516
摘要： Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is discussed that includes: a servo address mark count circuit, a user sync mark count circuit, and an offset calculation circuit. The servo address mark count circuit is operable to provide: a first count corresponding to a first servo address mark within a first track of a storage medium, a second count corresponding to a second servo address mark within the first track, a third count corresponding to a third servo address mark within a second track of the storage medium, and a fourth count corresponding to a fourth servo address mark within the second track. The user sync mark count circuit is operable to provide: a fifth count corresponding to a first user sync mark within the first track, and to provide a sixth count corresponding to a second user sync mark within the second track. The offset calculation circuit is operable to calculate an offset between the first track and the second track based at least in part on the first count, the second count, the third count, the fourth count, the fifth count, and the sixth count.
摘要翻译：本发明的各种实施例提供了用于数据处理的系统和方法。作为示例，讨论了包括：伺服地址标记计数电路，用户同步标记计数电路和偏移计算电路的数据处理电路。伺服地址标记计数电路可操作地提供：与存储介质的第一轨道内的第一伺服地址标记相对应的第一计数，对应于第一轨道内的第二伺服地址标记的第二计数，对应于在存储介质的第二磁道内的第三伺服地址标记，以及对应于第二磁道内的第四伺服地址标记的第四计数。用户同步标记计数电路可操作以提供：对应于第一轨道内的第一用户同步标记的第五计数，并且提供对应于第二轨道内的第二用户同步标记的第六计数。偏移计算电路至少部分地基于第一计数，第二计数，第三计数，第四计数，第五计数和第六计数来计算第一轨道和第二轨道之间的偏移。

4. 发明申请

US20130003214A1 Systems and Methods for Inter-Track Alignment 有权
标题翻译：轨道间对准的系统和方法
公开(公告)号：US20130003214A1
公开(公告)日：2013-01-03
申请号：US13173088
申请日：2011-06-30
申请人： Jeffrey P. Grundvig , Jason D. Byrne , Jefferson Singleton
发明人： Jeffrey P. Grundvig , Jason D. Byrne , Jefferson Singleton
IPC分类号： G11B5/09
CPC分类号： G11B20/10435 , G11B5/59616 , G11B5/59627 , G11B19/045 , G11B2020/1282 , G11B2020/1287 , G11B2220/2516
摘要： Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is discussed that includes: a servo address mark count circuit, a user sync mark count circuit, and an offset calculation circuit. The servo address mark count circuit is operable to provide: a first count corresponding to a first servo address mark within a first track of a storage medium, a second count corresponding to a second servo address mark within the first track, a third count corresponding to a third servo address mark within a second track of the storage medium, and a fourth count corresponding to a fourth servo address mark within the second track. The user sync mark count circuit is operable to provide: a fifth count corresponding to a first user sync mark within the first track, and to provide a sixth count corresponding to a second user sync mark within the second track. The offset calculation circuit is operable to calculate an offset between the first track and the second track based at least in part on the first count, the second count, the third count, the fourth count, the fifth count, and the sixth count.
摘要翻译：本发明的各种实施例提供了用于数据处理的系统和方法。作为示例，讨论了包括：伺服地址标记计数电路，用户同步标记计数电路和偏移计算电路的数据处理电路。伺服地址标记计数电路可操作地提供：与存储介质的第一轨道内的第一伺服地址标记相对应的第一计数，对应于第一轨道内的第二伺服地址标记的第二计数，对应于在存储介质的第二磁道内的第三伺服地址标记，以及对应于第二磁道内的第四伺服地址标记的第四计数。用户同步标记计数电路可操作以提供：对应于第一轨道内的第一用户同步标记的第五计数，并且提供对应于第二轨道内的第二用户同步标记的第六计数。偏移计算电路至少部分地基于第一计数，第二计数，第三计数，第四计数，第五计数和第六计数来计算第一轨道和第二轨道之间的偏移。

5. 发明授权

US06657800B1 Viterbi detector and method for recovering a binary sequence from a read signal 有权
标题翻译：维特比检测器和从读取信号中恢复二进制序列的方法
公开(公告)号：US06657800B1
公开(公告)日：2003-12-02
申请号：US09783801
申请日：2001-02-14
申请人： Hakan Ozdemir , Jason D. Byrne , Fereidoon Heydari
发明人： Hakan Ozdemir , Jason D. Byrne , Fereidoon Heydari
IPC分类号： G11B509
CPC分类号： H03M13/6331 , G11B20/10009 , G11B20/1426 , H03M13/3961 , H03M13/41 , H03M13/6343
摘要： A Viterbi detector receives a signal that represents a binary sequence having groups of no more and no fewer than a predetermined number of consecutive bits each having a first logic level, where the groups are separated from each other by respective bits having a second logic level. The Viterbi detector recovers the binary sequence from the signal by calculating a respective path metric for each of no more than four possible states of the binary sequence, and determining a surviving path from the calculated path metrics, where the binary sequence lies along the surviving path. Or, the Viterbi detector recovers the binary sequence from the signal by calculating respective path metrics for possible states of the binary sequence, calculating multiple path metrics for no more than one of the possible states, and determining the surviving path from the calculated path metrics.
摘要翻译：维特比检测器接收表示具有不超过并且不小于预定数量的连续位的组的二进制序列的信号，每个连续位具有第一逻辑电平，其中通过具有第二逻辑电平的各个位彼此分离。维特比检测器通过为二进制序列中不超过四个可能状态的每一个计算相应的路径度量，从信号中恢复二进制序列，以及从计算出的路径度量确定存活路径，其中二进制序列沿着存活路径。或者，维特比检测器通过计算二进制序列的可能状态的相应路径度量来计算来自信号的二进制序列，计算不超过一个可能状态的多个路径度量，以及根据计算的路径度量确定幸存路径。

6. 发明授权

US06775084B1 Circuit and method for determining the phase difference between a sample clock and a sampled signal 失效
标题翻译：用于确定采样时钟和采样信号之间的相位差的电路和方法
公开(公告)号：US06775084B1
公开(公告)日：2004-08-10
申请号：US09503453
申请日：2000-02-14
申请人： Hakan Ozdemir , Jason D. Byrne
发明人： Hakan Ozdemir , Jason D. Byrne
IPC分类号： G11B502
CPC分类号： G11B20/10037 , G11B20/10009 , G11B20/1403 , H03L7/091
摘要： A circuit includes a buffer for receiving and storing two samples of a signal, and a phase calculation circuit for calculating from the samples a phase difference between one of the samples and a predetermined point of the signal. Such a circuit can be used to decrease the alignment-acquisition time of a digital timing-recovery loop, and thus allows a shortening of the sector preambles and a corresponding increase in the data-storage density of a disk. In one application, the circuit determines an initial phase difference between a disk-drive read signal and a read-signal sample clock. The digital timing-recovery loop uses this phase difference to provide an initial coarse alignment between the read signal and the sample clock. By providing an initial coarse alignment, the recovery loop reduces the overall alignment-acquisition time.
摘要翻译：电路包括用于接收和存储信号的两个采样的缓冲器，以及相位计算电路，用于从样本中计算一个采样之间的相位差和信号的预定点。这样的电路可以用于减小数字定时恢复环路的对准采集时间，从而允许扇区前导码的缩短以及盘的数据存储密度的相应增加。在一个应用中，电路确定磁盘驱动器读取信号和读取信号采样时钟之间的初始相位差。数字定时恢复循环使用该相位差来提供读取信号和采样时钟之间的初始粗略对准。通过提供初始粗略对准，恢复循环减少了整体对准采集时间。

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