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31. 发明授权

US06821880B1 Process of dual or single damascene utilizing separate etching and DCM apparati 失效
标题翻译：使用单独蚀刻和DCM装置的双或单镶嵌工艺
公开(公告)号：US06821880B1
公开(公告)日：2004-11-23
申请号：US10725138
申请日：2003-12-01
申请人： Hun-Jan Tao , Chao-Cheng Chen
发明人： Hun-Jan Tao , Chao-Cheng Chen
IPC分类号： H01L214763
CPC分类号： H01L21/76814 , H01L21/67155 , H01L21/76801 , H01L21/76808 , H01L21/76838
摘要： A process of dual damascene or damascene. The dual damascene process entails providing an etching apparatus, a DCM machine and a wafer, the wafer having a metal line, a stop layer, a dielectric layer, a contact, and a photoresist layer. The dielectric layer and the contact are etched in the etching apparatus to form a trench. The photoresist and the contact are ashed in the DCM machine. Finally the wafer is wet cleaned.
摘要翻译：一个双镶嵌或镶嵌的过程。双镶嵌工艺需要提供蚀刻装置，DCM机器和晶片，晶片具有金属线，阻挡层，介电层，接触和光致抗蚀剂层。在蚀刻装置中蚀刻介电层和接触以形成沟槽。在DCM机器中将光致抗蚀剂和接触物灰化。最后将晶片湿式清洗。

32. 发明授权

US06764903B1 Dual hard mask layer patterning method 失效
标题翻译：双硬掩模层图案化方法
公开(公告)号：US06764903B1
公开(公告)日：2004-07-20
申请号：US10427451
申请日：2003-04-30
申请人： Bor-Wen Chan , Yuan-Hung Chiu , Hun-Jan Tao
发明人： Bor-Wen Chan , Yuan-Hung Chiu , Hun-Jan Tao
IPC分类号： H01L21336
CPC分类号： H01L21/28123 , H01L21/31116 , H01L21/31138 , H01L21/32137 , H01L21/32139
摘要： A method for forming a patterned target layer from a blanket target layer employs a pair of blanket hard mask layers laminated upon the blanket target layer. A patterned third mask layer is formed thereover. The method also employs four separate etch steps. One etch step is an anisotropic etch step for forming a patterned upper lying hard mask layer from the blanket upper lying hard mask layer. The patterned upper lying hard mask layer is then isotropically etched in a second etch step to form an isotropically etched patterned upper lying hard mask layer. The method is particularly useful for forming gate electrodes of diminished linewidths and enhanced dimensional control within semiconductor products.
摘要翻译：从覆盖目标层形成图案化目标层的方法采用层叠在覆盖目标层上的一对覆盖层硬掩模层。在其上形成图案化的第三掩模层。该方法还采用四个独立的蚀刻步骤。一个蚀刻步骤是用于从橡皮布上面的硬掩模层形成图案化的上卧硬掩模层的各向异性蚀刻步骤。然后在第二蚀刻步骤中各向同性蚀刻图案化的上卧硬掩模层，以形成各向同性蚀刻的图案化的上面的硬掩模层。该方法对于形成半导体产品中线宽减小和尺寸控制增强的栅电极特别有用。

33. 发明授权

US06498067B1 Integrated approach for controlling top dielectric loss during spacer etching 有权
标题翻译：在间隔蚀刻期间控制顶部介电损耗的集成方法
公开(公告)号：US06498067B1
公开(公告)日：2002-12-24
申请号：US10139021
申请日：2002-05-02
申请人： Baw-Ching Perng , Ming-Huang Tsai , Ju-Wang Hsu , Hun-Jan Tao
发明人： Baw-Ching Perng , Ming-Huang Tsai , Ju-Wang Hsu , Hun-Jan Tao
IPC分类号： H01L21336
CPC分类号： H01L29/665 , H01L29/6656
摘要： A process for forming a composite insulator spacer on the sides of a MOSFET gate structure, has been developed. The process features formation of additional insulator spacer shapes on top portions of sides of a gate structure in which an initial insulator spacer had been removed during an over etch cycle used for definition of the initial insulator spacer. The re-establishment of insulator spacer shapes provides a composite insulator spacer offering reduced risk of gate to substrate leakage or shorts, that can occur during a subsequent salicide procedure from the presence of metal silicide stringers or ribbons formed on, and residing on the composite insulator spacer.
摘要翻译：已经开发了在MOSFET栅极结构的侧面上形成复合绝缘体间隔物的工艺。该工艺特征是在栅极结构的侧面的顶部部分上形成额外的绝缘体间隔物形状，其中在用于限定初始绝缘体间隔物的过蚀刻循环期间已经去除了初始绝缘体间隔物。重新建立绝缘体间隔物形状提供了一种复合绝缘体间隔物，其降低了栅极与衬底泄漏或短路的风险，这可能在随后的自对准硅化物过程中发生，从存在金属硅化物桁条或形成在复合绝缘体上的带状物间隔

34. 发明授权

US06472335B1 Methods of adhesion promoter between low-K layer and underlying insulating layer 有权
标题翻译：低K层和下层绝缘层之间的粘附促进剂的方法
公开(公告)号：US06472335B1
公开(公告)日：2002-10-29
申请号：US09175019
申请日：1998-10-19
申请人： Chia-Shiung Tsai , Yao-Yi Cheng , Hun-Jan Tao
发明人： Chia-Shiung Tsai , Yao-Yi Cheng , Hun-Jan Tao
IPC分类号： H01L2131
CPC分类号： H01L21/0214 , H01L21/02118 , H01L21/022 , H01L21/02343 , H01L21/31111 , H01L21/312 , H01L21/3122 , H01L21/3124 , H01L21/3144 , H01L21/31629 , H01L21/3185 , H01L21/76801 , Y10S438/906 , Y10S438/958 , Y10S438/964
摘要： The present invention provides a method improving the adhesion between inter metal dielectric (IMD) layers by performing a HF dip etch to treat the surface of an oxide, silicon nitride or Silicon oxynitride insulating layer before an overlying low-K layer is formed. The present invention provides a method of fabricating a low-K IMD layer 20 over an oxide, Silicon oxynitride (SiON), or nitride IMD layer 14 with improved adhesion. First, a 1st inter metal dielectric (IMD) layer 14 is formed over a substrate. Next, the invention's novel HF dip etch is performed on the 1st IMD layer 14 to form a treated surface 16. Next, a 2nd BMD layer composed of a low-K material is formed over the rough surface 16 of the 1st IMD layer 14. The treated surface 16 improves the adhesion between a 1st IMD layer oxide (oxide, SiN or SiON) and a low k layer. Subsequent photoresist strip steps do not cause the 1st IMI layer 14 and the 2nd IMD layer 20 (low-K dielectric) to peel.
摘要翻译：本发明提供一种通过在形成上覆低K层之前进行HF浸渍蚀刻来处理氧化物，氮化硅或氮氧化硅绝缘层的表面来改善金属间电介质（IMD）层之间的粘合力的方法。本发明提供了一种在氧化物，氮氧化硅（SiON）或氮化物IMD层14上制备低K IMD层20的方法，其具有改善的粘合性。首先，在衬底上形成第一金属间介电层（IMD）层14。接下来，在第一IMD层14上进行本发明的新型HF浸渍蚀刻以形成处理表面16.接下来，在第一IMD层14的粗糙表面16上形成由低K材料构成的第二BMD层。经处理的表面16改善了第一IMD层氧化物（氧化物，SiN或SiON）和低k层之间的粘合性。随后的光刻胶条步骤不会导致第一IMI层14和第二IMD层20（低K电介质）剥离。

35. 发明授权

US06444566B1 Method of making borderless contact having a sion buffer layer 有权
标题翻译：制造无边界接触的方法，具有隔离缓冲层
公开(公告)号：US06444566B1
公开(公告)日：2002-09-03
申请号：US09845481
申请日：2001-04-30
申请人： Ming Huan Tsai , Jyh Huei Chen , Chu Yun Fu , Hun Jan Tao
发明人： Ming Huan Tsai , Jyh Huei Chen , Chu Yun Fu , Hun Jan Tao
IPC分类号： H01L214763
CPC分类号： H01L21/76897 , H01L21/76802 , H01L21/76832 , H01L21/76834
摘要： Borderless contacts are used in integrated circuits in order to conserve chip real estate. As part of the process for manufacturing borderless contacts, an etch-stopping layer of silicon nitride is first laid over the area that is to be contacted. Investigation has now shown that this can lead to damage to the silicon at the edges of the via. The present invention eliminates this damage by introducing a buffer layer between the silicon surface and said sidon nitride layer. Suitable materials for the buffer layer that have been found to be infective include silicon oxide and silicon oxynitride with the latter offering some ditional advantages over the former. Experimental data confirming the effectiveness of the buffer layer are provided, together with a process for its manufacture.
摘要翻译：无边界接触用于集成电路，以节省芯片的不动产。作为制造无边界接触的工艺的一部分，首先将氮化硅的蚀刻停止层铺设在要接触的区域上。现在调查显示，这可能导致在通孔边缘的硅损坏。本发明通过在硅表面和所述侧氮化物层之间引入缓冲层来消除这种损害。已经发现感染的缓冲层的合适材料包括氧化硅和氮氧化硅，后者提供了比前者更多的优点。提供确认缓冲层有效性的实验数据及其制造方法。

36. 发明授权

US06410424B1 Process flow to optimize profile of ultra small size photo resist free contact 有权
标题翻译：工艺流程优化超小尺寸光刻胶的自由接触
公开(公告)号：US06410424B1
公开(公告)日：2002-06-25
申请号：US09837599
申请日：2001-04-19
申请人： Ming-Huan Tsai , Chung-Long Chang , Chii-Ming Wu , Hun-Jan Tao
发明人： Ming-Huan Tsai , Chung-Long Chang , Chii-Ming Wu , Hun-Jan Tao
IPC分类号： H01L214763
CPC分类号： H01L21/76804 , H01L21/76802 , H01L21/76814 , H01L21/76829 , H01L21/76831 , Y10S438/975
摘要： A new processing sequence is provided for the creation of openings in layers of dielectric. Over a semiconductor surface are successively deposited an etch stop layer, a layer of dielectric and a hard mask layer. An opening is etched in the hard mask layer, the main opening is etched through the layer of dielectric and the etch stop layer. The surface is wet cleaned, after which a thin layer of silicon oxide is CVD deposited over the inside surfaces of the created opening. This thin layer of CVD oxide is subjected to argon sputter, providing of the critical dimensions of the upper region of the opening. Then the process continues with the deposition of the barrier metal, the filling of the opening with a conducting material to create the metal plug and the polishing of the surface of the deposited conducting material.
摘要翻译：提供了一种新的处理顺序，用于在电介质层中产生开口。在半导体表面上依次沉积蚀刻停止层，电介质层和硬掩模层。在硬掩模层中蚀刻开口，通过电介质层和蚀刻停止层蚀刻主开口。表面被湿清洗，之后在所产生的开口的内表面上CVD沉积薄层的氧化硅。对CVD氧化物薄层进行氩溅射，提供开口上部区域的临界尺寸。然后，该过程继续阻挡金属的沉积，用导电材料填充开口以产生金属塞和抛光沉积的导电材料的表面。

37. 发明授权

US6165881A Method of forming salicide poly gate with thin gate oxide and ultra narrow gate width 有权
标题翻译：形成具有薄栅极氧化物和超窄栅极宽度的自对准多晶硅栅极的方法
公开(公告)号：US6165881A
公开(公告)日：2000-12-26
申请号：US177185
申请日：1998-10-23
申请人： Hun-Jan Tao , Chia-Shiung Tsai
发明人： Hun-Jan Tao , Chia-Shiung Tsai
IPC分类号： H01L21/027 , H01L21/311 , H01L21/336 , H01L21/4763
CPC分类号： H01L29/665 , H01L21/0276 , H01L21/31116
摘要： I A method is achieved for removing a hardmask from a feature on a semiconductor wafer. The method comprises the following phases: depositing a buffer layer overall; etching back the buffer layer in an etching apparatus to expose the hardmask; etching the hardmask in the etching apparatus; and etching of the remaining buffer layer in the etching apparatus.
摘要翻译： I实现了从半导体晶片上的特征去除硬掩模的方法。该方法包括以下阶段：整体沉积缓冲层; 在蚀刻装置中蚀刻缓冲层以暴露硬掩模; 在蚀刻装置中蚀刻硬掩模; 并蚀刻在蚀刻装置中的剩余缓冲层。

38. 发明授权

US6130167A Method of preventing corrosion of a metal structure exposed in a non-fully landed via 有权
标题翻译：防止在非完全着陆的通孔中暴露的金属结构的腐蚀的方法
公开(公告)号：US6130167A
公开(公告)日：2000-10-10
申请号：US270593
申请日：1999-03-18
申请人： Hun-Jan Tao , Shu-Chin Yang , Chao-Cheng Chen
发明人： Hun-Jan Tao , Shu-Chin Yang , Chao-Cheng Chen
IPC分类号： H01L21/02 , H01L21/311 , H01L21/3213 , H01L21/768 , H01L21/308
CPC分类号： H01L21/02071 , H01L21/31133 , H01L21/31138 , H01L21/76814 , H01L21/76888 , H01L21/31116
摘要： A process used to prevent attack of an aluminum based structure, exposed in a non-fully landed via hole, from solvents used during the wet stripping cycle, performed to remove the via hole defining photoresist shape, has been developed. The process features the formation of a protective aluminum oxide layer, on the exposed side of the aluminum based structure, via use of a plasma treatment, performed in an H.sub.2 O/N.sub.2 ambient. The H.sub.2 O/N.sub.2 plasma treatment procedure is performed after a dry plasma, photoresist stripping step, but prior to a final wet photoresist stripping step. The aluminum oxide layer offers protection of the exposed regions of the aluminum structure, located in the non-fully landed via hole, from reaction or corrosion, that can result from exposure of aluminum to the solvents used in the final wet photoresist stripping cycle.
摘要翻译：已经开发了一种用于防止暴露在非完全着陆的通孔中的铝基结构从在湿式剥离循环期间使用的溶剂的侵蚀的过程，以去除限定光致抗蚀剂形状的通孔。该方法的特征在于在基于铝的结构的暴露侧上通过使用在H 2 O / N 2环境中进行的等离子体处理形成保护性氧化铝层。 H 2 O / N 2等离子体处理程序在干等离子体，光致抗蚀剂剥离步骤之后，但在最后的湿光致抗蚀剂剥离步骤之前进行。氧化铝层提供保护位于非完全着陆的通孔中的铝结构的暴露区域不受反应或腐蚀的影响，这可能是由于将铝暴露于最终湿光致抗蚀剂剥离循环中使用的溶剂而导致的。

39. 发明授权

US6129091A Method for cleaning silicon wafers with deep trenches 失效
标题翻译：用深沟槽清洗硅晶片的方法
公开(公告)号：US6129091A
公开(公告)日：2000-10-10
申请号：US725804
申请日：1996-10-04
申请人： Kuei-Ying Lee , Hun-Jan Tao , Chia-Shiung Tsai
发明人： Kuei-Ying Lee , Hun-Jan Tao , Chia-Shiung Tsai
IPC分类号： H01L21/00 , B08B3/08 , B08B3/12
CPC分类号： H01L21/67028
摘要： Current aqueous methods for removal of polymeric materials from the sidewalls of trenches etched into silicon wafers by reactive-ion-etching are inadequate for treating deep trenches having high aspect ratios. Spin-dry operations performed after the aqueous etching are incapable of completely removing rinse water and ionic species from these deep trenches, thereby leaving pockets of liquid. Subsequent evaporation of these pockets results in the concentration and eventual precipitation of residual ionic species creating watermarks. A two stage cleaning method is described in which the first stage dissolves the sidewall polymer and the second stage draws ionic species strongly chemisorbed onto the silicon surfaces into solution. A key feature of the method is that the wafer surface is not permitted to dry until after the final rinse.
摘要翻译：目前的用于通过反应离子蚀刻从蚀刻到硅晶片的沟槽的侧壁上去除聚合材料的水性方法不足以处理具有高纵横比的深沟槽。在水蚀刻之后执行的旋转干燥操作不能从这些深沟槽中完全去除漂洗水和离子物质，从而留下一些液体。随后蒸发这些口袋导致产生水印的残留离子物质的浓度和最终沉淀。描述了两阶段清洗方法，其中第一阶段溶解侧壁聚合物，第二阶段将离子物质强吸附在硅表面上成溶液。该方法的一个关键特征是晶片表面不允许干燥直到最后冲洗。

40. 发明授权

US6037266A Method for patterning a polysilicon gate with a thin gate oxide in a polysilicon etcher 有权
标题翻译：在多晶硅蚀刻剂中用薄栅极氧化物图案化多晶硅栅极的方法
公开(公告)号：US6037266A
公开(公告)日：2000-03-14
申请号：US161567
申请日：1998-09-28
申请人： Hun-Jan Tao , Chia-Shiung Tsai
发明人： Hun-Jan Tao , Chia-Shiung Tsai
IPC分类号： H01L21/3213 , H01L21/00
CPC分类号： H01L21/32137
摘要： A method of patterning a polysilicon gate using an oxide hard mask using a novel 4 step insitu etch process. All 4 etch steps are performed insitu in a polysilicon high density plasma (TCP--transformer coupled plasma) etcher. A multi-layered semiconductor structure 35 (FIG. 1) is formed comprising: a substrate 10, a gate oxide layer 14, a polysilicon layer 18, a hard mask layer 22, and a bottom anti-reflective coating (BARC) layer 26 and a resist layer 30. The 4 step insitu etch process comprises:a) in STEP 1, etching the bottom anti-reflective coating (BARC) layer by flowing HBr and O.sub.2 gasses, and applying a first TCP Power and a first Bias power;b) in STEP 2, etching the hard mask by flowing a flouorocarbon gas; and applying a second TCP Power and second Bias power;c) in STEP 3--stripping the bottom anti-reflective coating (BARC) layer by flowing oxygen and applying a third TCP Power and a third Bias power;d) in STEP 4--etching the polysilicon layer by flowing chlorine species, oxygen species; Helium species and bromine gas species and applying a fourth TCP Power and a fourth Bias power.
摘要翻译：使用新的4步蚀刻工艺使用氧化物硬掩模图案化多晶硅栅极的方法。所有4个蚀刻步骤都在多晶硅高密度等离子体（TCP-变压器耦合等离子体）蚀刻器中进行。形成多层半导体结构35（图1），包括：基板10，栅极氧化物层14，多晶硅层18，硬掩模层22和底部抗反射涂层（BARC）层26和 4步蚀刻工艺包括：a）在步骤1中，通过流过HBr和O2气体并施加第一TCP功率和第一偏压功率蚀刻底部抗反射涂层（BARC）层; b）在步骤2中，通过流动氟碳化物气体来蚀刻硬掩模; 以及施加第二TCP功率和第二偏置功率; c）在步骤3中 - 通过流动氧气并施加第三TCP功率和第三偏压功率来剥离底部抗反射涂层（BARC）层; d）在步骤4中，通过流动氯物质，氧物种蚀刻多晶硅层; 氦物种和溴气物种，并应用第四个TCP电源和第四个偏置电源。

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