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31. 发明授权

US07561464B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US07561464B2
公开(公告)日：2009-07-14
申请号：US12106919
申请日：2008-04-21
申请人： Haruki Toda
发明人： Haruki Toda
IPC分类号： G11C16/04
CPC分类号： G11C16/28 , G11C7/06 , G11C11/5642 , G11C16/0483 , G11C16/3445 , G11C16/3459
摘要： A semiconductor memory device includes: first and second cell arrays each having a plurality of memory cells; and a sense amplifier circuit for reading out data of the first and second cell arrays, wherein plural information cells and at least one reference cell are set in each of the first and second cell arrays, one of four data levels L0, L1, L2 and L3 (where, L0
摘要翻译：半导体存储器件包括：第一和第二单元阵列，每个具有多个存储单元; 以及读出放大器电路，用于读出第一和第二单元阵列的数据，其中在第一和第二单元阵列中的每一个中设置多个信息单元和至少一个参考单元，四个数据电平L0，L1，L2和 L3（其中，L0

32. 发明授权

US07529130B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07529130B2
公开(公告)日：2009-05-05
申请号：US11389252
申请日：2006-03-27
申请人： Haruki Toda
发明人： Haruki Toda
IPC分类号： G11C16/06
CPC分类号： G11C11/5642 , G11C7/06 , G11C16/0483 , G11C16/28 , G11C2211/5631 , G11C2211/5634
摘要： A semiconductor memory device includes: a memory cell array with electrically rewritable and non-volatile memory cells arranged therein; and a sense amplifier circuit configured to read out data of the memory cell array, wherein a plurality of information cells, in each of which one of M(M≧2) physical quantity levels is written, and at least one reference cell, in which a reference physical quantity level is written, are defined in the memory cell array, and the sense amplifier circuit detects a cell current difference between the information cell and the reference cell selected simultaneously in the memory cell array to sense data defined by the M physical quantity levels of the information cell.
摘要翻译：半导体存储器件包括：具有布置在其中的电可重写和非易失性存储单元的存储单元阵列; 以及读出放大器电路，被配置为读出存储单元阵列的数据，其中写入了M（M> = 2）个物理量级别中的一个的多个信息单元和至少一个参考单元，在存储单元阵列中定义参考物理量级别，并且读出放大器电路检测在存储单元阵列中同时选择的信息单元和参考单元之间的单元电流差，以感测由M个物理信息单元的数量级别。

33. 发明申请

US20090109729A1 RESISTANCE CHANGE MEMORY DEVICE AND METHOD FOR ERASING THE SAME 审中-公开
标题翻译：电阻变化存储器件及其擦除方法
公开(公告)号：US20090109729A1
公开(公告)日：2009-04-30
申请号：US12257029
申请日：2008-10-23
申请人： Haruki TODA
发明人： Haruki TODA
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C13/0069 , G11C13/0007 , G11C13/0097 , G11C2213/32
摘要： A resistance change memory device including a cell array with memory cells arranged therein to store a resistance value as data in a non-volatile manner, and an erase circuit configured to set the memory cells in the cell array in a reset state prior to data writing, wherein the erase circuit includes: an erase current generating circuit configured to output erase current of the cell array; multiple switch devices so disposed on current paths between the erase current generating circuit and the respective divided areas defined in the cell array as to supply the erase current to the divided areas; and a control circuit configured to sequentially turn on the switch devices.
摘要翻译：一种电阻变化存储器件，包括具有其中布置有存储单元的单元阵列，以非易失性方式存储电阻值作为数据;以及擦除电路，被配置为在数据写入之前将单元阵列中的存储单元设置为复位状态，其中所述擦除电路包括：擦除电流产生电路，被配置为输出所述单元阵列的擦除电流; 多个开关器件设置在擦除电流产生电路和限定在单元阵列中的各个分割区域之间的电流路径上，以便将擦除电流提供给分割区域; 以及控制电路，被配置为顺序地打开所述开关装置。

34. 发明授权

US07495965B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US07495965B2
公开(公告)日：2009-02-24
申请号：US11750052
申请日：2007-05-17
申请人： Toshihiro Suzuki , Toshiaki Edahiro , Haruki Toda
发明人： Toshihiro Suzuki , Toshiaki Edahiro , Haruki Toda
IPC分类号： G11C16/06
CPC分类号： G11C16/0483 , G11C16/08 , G11C16/24
摘要： A voltage switching circuit used in a row decoder includes: PMOS transistor P2 and high-voltage NMOS transistor D3 connected in series between VRDEC and TG; PMOS transistor P1 and high-voltage NMOS transistor D2 connected in series between VRDEC and NA; NMOS transistor N2 and high-voltage NMOS transistor D6 connected in series between TG and Vss to be driven by decode output Ab; and NMOS transistor N1 and high-voltage NMOS transistor D5 connected in series between NA and Vss to be driven by decode output Aa. Gates and drains of P1 and P2 are cross-coupled. Gates of D3 and D2 are coupled to TG and NA, respectively.
摘要翻译：在行解码器中使用的电压切换电路包括：串联在VRDEC和TG之间的PMOS晶体管P2和高压NMOS晶体管D3; 串联在VRDEC和NA之间的PMOS晶体管P1和高电压NMOS晶体管D2; 串联在TG和Vss之间的NMOS晶体管N2和高电压NMOS晶体管D6由解码输出Ab驱动; 并且在NA和Vss之间串联连接的NMOS晶体管N1和高电压NMOS晶体管D5由解码输出Aa驱动。 P1和P2的门和排水管交叉耦合。 D3和D2的门分别耦合到TG和NA。

35. 发明授权

US07394680B2 Resistance change memory device having a variable resistance element with a recording layer electrode served as a cation source in a write or erase mode 有权
标题翻译：具有记录层电极的可变电阻元件的电阻变化存储器件在写入或擦除模式下用作阳离子源
公开(公告)号：US07394680B2
公开(公告)日：2008-07-01
申请号：US11761391
申请日：2007-06-12
申请人： Haruki Toda , Koichi Kubo
发明人： Haruki Toda , Koichi Kubo
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C13/0004 , G11C13/0011 , G11C13/0014 , G11C13/0016 , G11C13/004 , G11C2013/0042 , G11C2213/31 , G11C2213/32 , G11C2213/55 , G11C2213/56 , G11C2213/71 , G11C2213/72
摘要： A resistance change memory device including: a semiconductor substrate; at least one cell array formed above the semiconductor substrate to have a stack structure of a variable resistance element and an access element, the variable resistance element storing a high resistance state or a low resistance state in a non-volatile manner, the access element having such an off-state resistance value in a certain voltage range that is ten times or more as high as that in a select state; and a read/write circuit formed on the semiconductor substrate, wherein the variable resistance element includes: a recording layer formed of a composite compound containing at least one transition element and a cavity site for housing a cation ion; and electrodes formed on the opposite sides of the recording layer, one of the electrodes serving as a cation source in a write or erase mode for supplying a cation to the recording layer to be housed in the cavity site.
摘要翻译：一种电阻变化存储器件，包括：半导体衬底; 至少一个单元阵列形成在所述半导体衬底上方以具有可变电阻元件和存取元件的堆叠结构，所述可变电阻元件以非易失性方式存储高电阻状态或低电阻状态，所述存取元件具有在选择状态下为十倍以上的一定电压范围内的截止电阻值; 以及形成在所述半导体基板上的读/写电路，其中所述可变电阻元件包括：由包含至少一个过渡元件的复合化合物和用于容纳阳离子离子的空腔位置形成的记录层; 以及形成在记录层的相对侧上的电极，其中一个电极用作写入或擦除模式中的阳离子源，用于将阳离子供应到要容纳在腔部位中的记录层。

36. 发明申请

US20080112211A1 PHASE CHANGING MEMORY DEVICE 有权
标题翻译：相变存储器件
公开(公告)号：US20080112211A1
公开(公告)日：2008-05-15
申请号：US11970154
申请日：2008-01-07
申请人： Haruki TODA
发明人： Haruki TODA
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C13/0004 , G11C8/08 , G11C11/36 , G11C13/0007 , G11C13/0028 , G11C13/004 , G11C13/0069 , G11C2013/0042 , G11C2013/009 , G11C2213/31 , G11C2213/71 , G11C2213/72 , H01L27/2409 , H01L27/2481 , H01L45/06 , H01L45/1233 , H01L45/1675
摘要： A phase change memory device includes a substrate, a plurality of cell arrays stacked above the substrate and each including a matrix layout of a plurality of memory cells, each the memory cell storing therein as data a resistance value determinable by a phase change, a write circuit configured to write a pair cell constituted by two neighboring memory cells within the plurality of cell arrays in such a manner as to write one of the pair cell into a high resistance value state and write the other into a low resistance value state, and a read circuit configured to read complementary resistance value states of the pair cell as a one bit of data.
摘要翻译：相变存储器件包括衬底，堆叠在衬底上的多个单元阵列，每个单元阵列包括多个存储器单元的矩阵布局，每个存储器单元作为数据存储为可由相变所确定的电阻值，写入电路，被配置为以多个单元阵列中的两个相邻存储单元构成的对单元，以将该单元格中的一个写入高电阻值状态，并将另一个单元写入低电阻值状态;以及读取电路被配置为读取对单元的互补电阻值状态作为一位数据。

37. 发明申请

US20070285966A1 RESISTANCE CHANGE MEMORY DEVICE 有权
标题翻译：电阻变化存储器件
公开(公告)号：US20070285966A1
公开(公告)日：2007-12-13
申请号：US11761391
申请日：2007-06-12
申请人： Haruki Toda , Koichi Kubo
发明人： Haruki Toda , Koichi Kubo
IPC分类号： G11C11/36
CPC分类号： G11C13/0007 , G11C13/0004 , G11C13/0011 , G11C13/0014 , G11C13/0016 , G11C13/004 , G11C2013/0042 , G11C2213/31 , G11C2213/32 , G11C2213/55 , G11C2213/56 , G11C2213/71 , G11C2213/72
摘要： A resistance change memory device including: a semiconductor substrate; at least one cell array formed above the semiconductor substrate to have a stack structure of a variable resistance element and an access element, the variable resistance element storing a high resistance state or a low resistance state in a non-volatile manner, the access element having such an off-state resistance value in a certain voltage range that is ten times or more as high as that in a select state; and a read/write circuit formed on the semiconductor substrate, wherein the variable resistance element includes: a recording layer formed of a composite compound containing at least one transition element and a cavity site for housing a cation ion; and electrodes formed on the opposite sides of the recording layer, one of the electrodes serving as a cation source in a write or erase mode for supplying a cation to the recording layer to be housed in the cavity site therein.
摘要翻译：一种电阻变化存储器件，包括：半导体衬底; 至少一个单元阵列形成在所述半导体衬底上方以具有可变电阻元件和存取元件的堆叠结构，所述可变电阻元件以非易失性方式存储高电阻状态或低电阻状态，所述存取元件具有在选择状态下为十倍以上的一定电压范围内的截止电阻值; 以及形成在所述半导体基板上的读/写电路，其中所述可变电阻元件包括：由包含至少一个过渡元件的复合化合物和用于容纳阳离子离子的空腔位置形成的记录层; 以及形成在记录层的相对侧上的电极，其中一个电极用作写入或擦除模式中的阳离子源，用于将阳离子供应到要容纳在其中的空腔位置的记录层。

38. 发明申请

US20070285963A1 RESISTANCE CHANGE MEMORY DEVICE 有权
标题翻译：电阻变化存储器件
公开(公告)号：US20070285963A1
公开(公告)日：2007-12-13
申请号：US11761282
申请日：2007-06-11
申请人： Haruki Toda , Koichi Kubo
发明人： Haruki Toda , Koichi Kubo
IPC分类号： G11C11/36
CPC分类号： G11C5/02 , G11C7/18 , G11C13/0004 , G11C13/0007 , G11C2213/31 , G11C2213/71 , G11C2213/72 , H01L27/2409 , H01L27/2481 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/1253 , H01L45/126 , H01L45/147
摘要： A resistance change memory device including: a semiconductor substrate; cell arrays stacked above the substrate, each having memory cells, bit lines and word lines; a read/write circuit formed on the semiconductor substrate; first and second vertical wirings disposed to connect the bit lines to the read/write circuit; and third vertical wirings disposed the word lines to the read/write circuit. The memory cell includes a variable resistance element for storing as information a resistance value, which has a recording layer composed of a composite compound containing at least two types of cation elements, at least one type of the cation element being a transition element having “d” orbit, in which electrons are incompletely filled, the shortest distance between adjacent cation elements being 0.32 nm or less.
摘要翻译：一种电阻变化存储器件，包括：半导体衬底; 单元阵列堆叠在衬底上，每个阵列具有存储单元，位线和字线; 形成在半导体衬底上的读/写电路; 布置成将位线连接到读/写电路的第一和第二垂直布线; 并且第三垂直布线将字线布置到读/写电路。存储单元包括用于存储作为信息的电阻值的可变电阻元件，电阻值具有由包含至少两种阳离子元素的复合化合物组成的记录层，至少一种类型的阳离子元素是具有“d “轨道，其中电子不完全填充，相邻阳离子元素之间的最短距离为0.32nm或更小。

39. 发明申请

US20070268750A1 SEMICONDUCTOR MEMORY DEVICE 失效
标题翻译：半导体存储器件
公开(公告)号：US20070268750A1
公开(公告)日：2007-11-22
申请号：US11750052
申请日：2007-05-17
申请人： Toshihiro SUZUKI , Toshiaki Edahiro , Haruki Toda
发明人： Toshihiro SUZUKI , Toshiaki Edahiro , Haruki Toda
IPC分类号： G11C11/34 , G11C16/04 , G11C16/06
CPC分类号： G11C16/0483 , G11C16/08 , G11C16/24
摘要： A voltage switching circuit used in a row decoder includes: PMOS transistor P2 and high-voltage NMOS transistor D3 connected in series between VRDEC and TG; PMOS transistor P1 and high-voltage NMOS transistor D2 connected in series between VRDEC and NA; NMOS transistor N2 and high-voltage NMOS transistor D6 connected in series between TG and Vss to be driven by decode output Ab; and NMOS transistor N1 and high-voltage NMOS transistor D5 connected in series between NA and Vss to be driven by decode output Aa. Gates and drains of P1 and P2 are cross-coupled. Gates of D3 and D2 are coupled to TG and NA, respectively.
摘要翻译：在行解码器中使用的电压切换电路包括：串联连接在VRDEC和TG之间的PMOS晶体管P 2和高电压NMOS晶体管D 3; 在VRDEC和NA之间串联连接的PMOS晶体管P 1和高电压NMOS晶体管D 2; 串联在TG和Vss之间的NMOS晶体管N 2和高电压NMOS晶体管D 6由解码输出Ab驱动; 并且在NA和Vss之间串联连接的NMOS晶体管N 1和高电压NMOS晶体管D 5由解码输出Aa驱动。 P 1和P 2的闸门和排水沟交叉耦合。 D 3和D 2的门分别耦合到TG和NA。

40. 发明申请

US20070220400A1 SEMICONDUCTOR MEMORY DEVICE 失效
标题翻译：半导体存储器件
公开(公告)号：US20070220400A1
公开(公告)日：2007-09-20
申请号：US11674342
申请日：2007-02-13
申请人： Haruki TODA , Toshiaki EDAHIRO
发明人： Haruki TODA , Toshiaki EDAHIRO
IPC分类号： G11C29/00
CPC分类号： G06F11/1068 , G11C16/0483
摘要： A memory device includes an error detection and correction system with an error correcting code over Galois field GF(2n), which has an operation circuit configured to execute addition/subtraction with modulo 2n−1, wherein the operation circuit includes first and second operation parts for performing addition/subtraction with modulo M and modulo N (where, M and N are integers, which are prime with each other as being obtained by factorizing 2n−1), the first and second operation parts being for performing addition/subtraction simultaneously in parallel with each other to output an operation result of the addition/subtraction with modulo 2n−1, and wherein the first and second operation parts each includes an adder circuit.
摘要翻译：存储器件包括具有伽罗瓦域GF（2）上的纠错码的错误检测和校正系统，其具有被配置为执行模2加法/减法的运算电路， / SUP> -1，其中运算电路包括第一和第二操作部分，用于以模M和模N执行加/减（其中，M和N是整数，它们是通过因子分解2 ^{n -1），第一和第二操作部分用于同时并行地进行加/减运算以输出模2加法/减法的运算结果， 1，并且其中第一和第二操作部分各自包括加法器电路。}

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