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1. 发明申请

US20070220400A1 SEMICONDUCTOR MEMORY DEVICE 失效
标题翻译：半导体存储器件
公开(公告)号：US20070220400A1
公开(公告)日：2007-09-20
申请号：US11674342
申请日：2007-02-13
申请人： Haruki TODA , Toshiaki EDAHIRO
发明人： Haruki TODA , Toshiaki EDAHIRO
IPC分类号： G11C29/00
CPC分类号： G06F11/1068 , G11C16/0483
摘要： A memory device includes an error detection and correction system with an error correcting code over Galois field GF(2n), which has an operation circuit configured to execute addition/subtraction with modulo 2n−1, wherein the operation circuit includes first and second operation parts for performing addition/subtraction with modulo M and modulo N (where, M and N are integers, which are prime with each other as being obtained by factorizing 2n−1), the first and second operation parts being for performing addition/subtraction simultaneously in parallel with each other to output an operation result of the addition/subtraction with modulo 2n−1, and wherein the first and second operation parts each includes an adder circuit.
摘要翻译：存储器件包括具有伽罗瓦域GF（2）上的纠错码的错误检测和校正系统，其具有被配置为执行模2加法/减法的运算电路， / SUP> -1，其中运算电路包括第一和第二操作部分，用于以模M和模N执行加/减（其中，M和N是整数，它们是通过因子分解2 ^{n -1），第一和第二操作部分用于同时并行地进行加/减运算以输出模2加法/减法的运算结果， 1，并且其中第一和第二操作部分各自包括加法器电路。}

2. 发明申请

US20080080243A1 SEMICONDUCTOR MEMORY DEVICE 失效
标题翻译：半导体存储器件
公开(公告)号：US20080080243A1
公开(公告)日：2008-04-03
申请号：US11864089
申请日：2007-09-28
申请人： Toshiaki EDAHIRO , Toshihiro SUZUKI , Haruki TODA
发明人： Toshiaki EDAHIRO , Toshihiro SUZUKI , Haruki TODA
IPC分类号： G11C16/04
CPC分类号： G11C11/5642 , G11C2211/5641
摘要： There is provided a semiconductor memory device with NAND strings arranged therein, the NAND string having a plurality of electrically rewritable and non-volatile memory cells connected in series, including: a first data area; and a second data area, which is smaller in capacitance than the first data area and random accessible at a higher rate than the first data area.
摘要翻译：提供了一种其中布置有NAND串的半导体存储器件，该NAND串具有串联连接的多个电可重写和非易失性存储单元，包括：第一数据区; 以及第二数据区域，其电容小于第一数据区域，并且以比第一数据区域更高的速率随机访问。

3. 发明申请

US20070266291A1 SEMICONDUCTOR MEMORY DEVICE 审中-公开
标题翻译：半导体存储器件
公开(公告)号：US20070266291A1
公开(公告)日：2007-11-15
申请号：US11691636
申请日：2007-03-27
申请人： Haruki TODA , Toshiaki Edahiro
发明人： Haruki TODA , Toshiaki Edahiro
IPC分类号： G06F11/00 , H03M13/00
CPC分类号： H03M13/152 , G06F11/1068 , H03M13/1575
摘要： A semiconductor memory device including an error detection and correction system, wherein the error detection and correction system has a first operation mode for correcting one number-bit (for example 2) errors and a second operation mode for correcting another number-bit (for example 1) error(s), which are exchangeable to be set with a main portion of the system used in common.
摘要翻译：一种包括错误检测和校正系统的半导体存储器件，其中错误检测和校正系统具有用于校正一个数位（例如2个）错误的第一操作模式和用于校正另一个数位（例如， 1）错误，可以交换为与共同使用的系统的主要部分进行设置。

4. 发明申请

US20100165702A1 THREE DIMENSIONAL PROGRAMMABLE RESISTANCE MEMORY DEVICE WITH A READ/WRITE CIRCUIT STACKED UNDER A MEMORY CELL ARRAY 有权
标题翻译：具有在存储单元阵列下堆叠的读/写电路的三维可编程电阻存储器件
公开(公告)号：US20100165702A1
公开(公告)日：2010-07-01
申请号：US12559178
申请日：2009-09-14
申请人： Haruki TODA
发明人： Haruki TODA
IPC分类号： G11C11/34
CPC分类号： G11C13/0011 , G11C13/0069 , G11C2013/009 , G11C2213/15 , G11C2213/71 , G11C2213/72 , H01L27/2409 , H01L27/2481 , H01L45/085 , H01L45/1233 , H01L45/142 , H01L45/143
摘要： A programmable resistance memory device includes a semiconductor substrate, at least one cell array, in which memory cells are arranged formed above the semiconductor substrate. Each of the memory cells has a stack structure of a programmable resistance element and an access element, the programmable resistance element storing a high resistance state or a low resistance state determined due to the polarity of voltage application in a non-volatile manner. The access element has such a resistance value in an off-state in a certain voltage range that is ten time or more as high as that in a select state. A read/write circuit is formed on a semiconductor substrate as underlying the cell array for data reading and data writing in communication with the cell array.
摘要翻译：可编程电阻存储器件包括半导体衬底，至少一个单元阵列，其中存在存储单元布置在半导体衬底上方。每个存储单元具有可编程电阻元件和存取元件的堆叠结构，可编程电阻元件存储由于电压施加的极性以非易失性方式而确定的高电阻状态或低电阻状态。存取元件在与选择状态相同的10倍以上的一定电压范围内处于断开状态的电阻值。读/写电路形成在半导体衬底上，作为用于与单元阵列通信的数据读取和数据写入的单元阵列。

5. 发明申请

US20090003047A1 RESISTANCE CHANGE MEMORY DEVICE 有权
标题翻译：电阻变化存储器件
公开(公告)号：US20090003047A1
公开(公告)日：2009-01-01
申请号：US12128343
申请日：2008-05-28
申请人： Haruki TODA
发明人： Haruki TODA
IPC分类号： G11C11/00
CPC分类号： G11C13/00 , G11C13/0023 , G11C13/0026 , G11C13/004 , G11C2013/0054 , G11C2213/71 , G11C2213/72
摘要： A resistance change memory device includes: a semiconductor substrate; a cell array so formed on the substrate as to have resistance-change memory cells three-dimensionally stacked and arranged; and a sense amplifier array formed on the substrate under the cell array, wherein the cell array includes first and second cell array blocks arranged in a bit line direction, and first and second bit lines are selected from the first and second cell array blocks, respectively, to constitute a pair and coupled to differential input nodes in the sense amplifier array.
摘要翻译：电阻变化存储器件包括：半导体衬底; 在基板上形成为具有三维层叠并配置的电阻变化存储单元的单元阵列; 以及形成在所述单元阵列下方的所述基板上的读出放大器阵列，其中，所述单元阵列包括以位线方向排列的第一和第二单元阵列块，并且分别从所述第一和第二单元阵列块中选择第一和第二位线，以构成一对并耦合到读出放大器阵列中的差分输入节点。

6. 发明申请

US20130250652A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME 有权
标题翻译：半导体存储器件及其控制方法
公开(公告)号：US20130250652A1
公开(公告)日：2013-09-26
申请号：US13597740
申请日：2012-08-29
申请人： Haruki TODA
发明人： Haruki TODA
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C13/0011 , G11C13/0023 , G11C13/004 , G11C13/0097 , G11C2213/71 , G11C2213/73
摘要： According to an embodiment, a semiconductor memory device comprises: a memory cell array configured having a plurality of memory cell mats, the memory cell mats including a plurality of first lines, second lines, and memory cells, and the memory cell mats being stacked such that the first and second lines are shared alternately by each of the memory cell mats; and a peripheral circuit. Each of the memory cells has a variable resistance characteristic and a current rectifying characteristic. An orientation from an anode toward a cathode of all the memory cells is identical. The peripheral circuit applies to one of the first line and the second line connected to an anode side of the selected memory cell a selected bit line voltage, and applies to the other a selected word line voltage.
摘要翻译：根据实施例，半导体存储器件包括：配置有多个存储单元垫的存储单元阵列，所述存储单元阵列包括多个第一行，第二行和存储单元，并且存储单元阵列被堆叠第一和第二行由每个存储单元垫交替共享; 和外围电路。每个存储单元具有可变电阻特性和电流整流特性。从所有存储器单元的阳极到阴极的取向是相同的。外围电路适用于与所选存储单元的阳极侧连接的选定位线电压的第一线路和第二线路中的一条线路，并且向另一条线路电压施加。

7. 发明申请

US20130170280A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20130170280A1
公开(公告)日：2013-07-04
申请号：US13586170
申请日：2012-08-15
申请人： Haruki TODA
发明人： Haruki TODA
IPC分类号： G11C11/00
CPC分类号： G11C13/0002 , G11C13/0011 , G11C13/0069 , G11C2013/0073 , G11C2213/15 , G11C2213/71 , G11C2213/77
摘要： A semiconductor memory device according to the embodiment comprises memory cells each having asymmetrical voltage-current characteristics, wherein the memory cell has a first state, and a second state and a third state of higher resistances than that in the first state, wherein the memory cell, (1) in the second state, makes a transition to the first state on application of a first voltage of the first polarity, (2) in the first state, makes a transition to the second state on application of a second voltage of the second polarity, (3) in the first state, makes a transition to the third state on application of a third voltage of the second polarity (the third voltage
摘要翻译：根据实施例的半导体存储器件包括各自具有不对称电压 - 电流特性的存储单元，其中存储单元具有第一状态，以及比第一状态高的电阻的第二状态和第三状态，其中存储单元，（1）在第二状态下，在施加第一极性的第一电压时转变到第一状态，（2）在第一状态下，在施加第二电压的第二电压时转变到第二状态第二极性，（3）在第一状态下，在施加第二极性（第三电压<第二电压）的第三电压时转变到第三状态，以及（4）在第三状态下进行转变施加第一极性的第四电压（第四电压<第一电压）到第一状态。

8. 发明申请

US20120195101A1 RESISTANCE-CHANGING MEMORY DEVICE 有权
标题翻译：电阻变化存储器件
公开(公告)号：US20120195101A1
公开(公告)日：2012-08-02
申请号：US13446137
申请日：2012-04-13
申请人： Haruki TODA
发明人： Haruki TODA
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C11/56 , G11C13/0033 , G11C13/004 , G11C16/3431 , G11C2013/0047 , G11C2013/0054 , G11C2213/72
摘要： A resistance-changing memory device has a cell array having memory cells, each of which stores as data a reversibly settable resistance value, a sense amplifier for reading data from a selected memory cell in the cell array, and a voltage generator circuit which generates, after having read data of the selected memory cell, a voltage pulse for convergence of a resistive state of this selected memory cell in accordance with the read data.
摘要翻译：电阻变化存储器件具有存储单元的单元阵列，每个存储单元存储数据作为可逆设置的电阻值，用于从单元阵列中的选定存储单元读取数据的读出放大器，以及电压发生器电路，在读取所选择的存储单元的数据之后，根据读取的数据，产生用于收敛该选择的存储单元的电阻状态的电压脉冲。

9. 发明申请

US20110205790A1 PHASE-CHANGE MEMORY DEVICE 有权
标题翻译：相变存储器件
公开(公告)号：US20110205790A1
公开(公告)日：2011-08-25
申请号：US13099735
申请日：2011-05-03
申请人： Haruki TODA
发明人： Haruki TODA
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C11/56 , G11C11/5678 , G11C13/0004 , G11C13/003 , G11C13/004 , G11C2013/0054 , G11C2013/009 , G11C2213/71 , G11C2213/72 , G11C2213/78 , G11C2213/79 , H01L27/2409 , H01L27/2472 , H01L27/2481 , H01L45/06 , H01L45/1233
摘要： A phase-change memory device has a plurality of first wiring lines WL extending in parallel to each other, a plurality of second wiring lines BL which are disposed to cross the first wiring lines WL while being separated or isolated therefrom, and memory cells MC which are disposed at respective cross points of the first wiring lines WL and the second wiring lines BL and each of which has one end connected to a first wiring line WL and the other end connected to a second wiring line BL. The memory cell MC has a variable resistive element VR which stores as information a resistance value determined due to phase change between crystalline and amorphous states thereof, and a Schottky diode SD which is connected in series to the variable resistive element VR.
摘要翻译：相变存储器件具有彼此平行延伸的多个第一布线WL，多个第二布线BL布置成与第一布线WL交叉而被分离或隔离，并且存储单元MC 被布置在第一布线WL和第二布线BL的各交叉点，并且每个布线的一端连接到第一布线WL，另一端连接到第二布线BL。存储单元MC具有可变电阻元件VR，其存储由于其结晶态和非晶态之间的相变而确定的电阻值和与可变电阻元件VR串联连接的肖特基二极管SD的信息。

10. 发明申请

US20110202815A1 ERROR DETECTION AND CORRECTION SYSTEM 有权
标题翻译：错误检测和校正系统
公开(公告)号：US20110202815A1
公开(公告)日：2011-08-18
申请号：US13011278
申请日：2011-01-21
申请人： Haruki TODA
发明人： Haruki TODA
IPC分类号： H03M13/09 , H03M13/07
CPC分类号： H03M13/1545 , H03M13/152 , H03M13/6502
摘要： An error detection and correction system in accordance with an embodiment comprises: an encoding unit; a syndrome calculating unit; a syndrome element calculating unit; an error search unit; and an error correction unit, read and write of a memory cell array being assumed to be performed concurrently for m bits, and error detection and correction being assumed to be performed in data units of M bits (where M is an integer multiple of m), and an encoding unit and a syndrome calculating unit sharing a time-division decoder for performing data bit selection according to respective tables of check bit generation and syndrome generation, the time-division decoder being operative to repeat multiple cycles of m bit concurrent data input.
摘要翻译：根据实施例的错误检测和校正系统包括：编码单元; 综合征计算单元; 综合征元素计算单元; 错误搜索单元; 以及错误校正单元，假定为m位同时执行的存储单元阵列的读和写，并且假定以M位的数据单元（其中M是m的整数倍）执行错误检测和校正，以及编码单元和校正子计算单元，其共享用于根据校验位产生和校正子产生的各个表执行数据位选择的时分解码器，该时分解码器可操作以重复多个m位并发数据输入周期。

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