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31. 发明授权

US5831866A Method and apparatus for removing timing hazards in a circuit design 失效
公开(公告)号：US5831866A
公开(公告)日：1998-11-03
申请号：US980419
申请日：1997-11-26
申请人： Luc Burgun , Olivier LePape , Frederic Reblewski
发明人： Luc Burgun , Olivier LePape , Frederic Reblewski
IPC分类号： G06F17/50
CPC分类号： G06F17/5027 , G06F17/505
摘要： A computer system is programmed with logic for automatically removing timing hazards from a circuit design. More specifically, the computer system is programmed with logic for automatically detecting and resolving clock gating as well as clock division timing hazards from the circuit design. In one embodiment, the computer system is further programmed with logic for logically organize timing hazards into levels, after the clock gating timing hazards have been resolved, and then resolving clock division timing hazards recursively. In one adaptation, the computer system is a component of a hardware emulation system.

32. 发明授权

US08346530B2 Logic design modeling and interconnection 有权
标题翻译：逻辑设计建模与互连
公开(公告)号：US08346530B2
公开(公告)日：2013-01-01
申请号：US12605622
申请日：2009-10-26
申请人： Frederic Reblewski
发明人： Frederic Reblewski
IPC分类号： G06F17/50 , H03K19/20
CPC分类号： G06F17/5022
摘要： A dynamic reconfigurable interconnect network architecture in a logic simulation system that interconnects a plurality of simulation engines together, providing a high degree of interconnectivity in an efficient manner. The logic simulation system may create and manage linkable sub-programs for execution by a simulation engine. The logic simulation system may schedule various tasks in a design to be simulated, including horizontal and vertical partitioning of the design and determination of an order in which events such as clock edges and asynchronous signals are to be implemented by a logic simulation system.
摘要翻译：在逻辑仿真系统中的动态可重配置互连网络架构，其将多个模拟引擎相互连接在一起，以有效的方式提供高度的互连性。逻辑仿真系统可以创建和管理可链接的子程序以供仿真引擎执行。逻辑仿真系统可以在要仿真的设计中调度各种任务，包括设计的水平和垂直划分以及由逻辑模拟系统实现时钟边缘和异步信号等事件的顺序的确定。

33. 发明授权

US07305633B2 Distributed configuration of integrated circuits in an emulation system 有权
标题翻译：仿真系统中集成电路的分布式配置
公开(公告)号：US07305633B2
公开(公告)日：2007-12-04
申请号：US10736908
申请日：2003-12-17
申请人： Frederic Josso , Xavier Montagne , Frederic Reblewski
发明人： Frederic Josso , Xavier Montagne , Frederic Reblewski
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5027
摘要： Data processing resources are distributively provided to an emulation system to locally and correspondingly configure emulation integrated circuits. In certain embodiments the data processing resources also perform emulation functions. In one embodiment, the distributed data processing resources are disposed on logic boards having emulation ICs that include the reconfigurable logic resources. In another embodiment, data processing resources receive commands transmitted from a workstation executing electronic design automation (EDA) software. In other embodiments, at least some of the distributed data processing resources are disposed on the emulation ICs. The board and IC disposed distributed data processing resources cooperatively perform the configuration and emulation functions as described.
摘要翻译：数据处理资源分布式提供给仿真系统，以本地和相应地配置仿真集成电路。在某些实施例中，数据处理资源也执行仿真功能。在一个实施例中，分布式数据处理资源被布置在具有包括可重构逻辑资源的仿真IC的逻辑板上。在另一个实施例中，数据处理资源接收从执行电子设计自动化（EDA）软件的工作站发送的命令。在其他实施例中，分布式数据处理资源中的至少一些被布置在仿真IC上。配置分布式数据处理资源的电路板和IC协同执行如上所述的配置和仿真功能。

34. 发明申请

US20070194807A1 Packet-oriented communication in reconfigurable circuit(s) 有权
标题翻译：可重配置电路中的面向分组的通信
公开(公告)号：US20070194807A1
公开(公告)日：2007-08-23
申请号：US11358338
申请日：2006-02-21
申请人： Frederic Reblewski , Cesar Douady
发明人： Frederic Reblewski , Cesar Douady
IPC分类号： H03K19/173
CPC分类号： H03K19/17736 , G06F15/7867 , H04L47/10 , H04L47/39 , H04L49/15 , H04L49/3009
摘要： A reconfigurable circuit having communication resources configured to facilitate selective packet-oriented communications among reconfigurable resources is described herein.
摘要翻译：具有被配置为促进可重配置资源之间的选择性分组定向通信的通信资源的可重新配置电路在此被描述。

35. 发明申请

US20070168718A1 Reconfigurable system with corruption detection and recovery 有权
标题翻译：具有腐败检测和恢复的可重构系统
公开(公告)号：US20070168718A1
公开(公告)日：2007-07-19
申请号：US11268933
申请日：2005-11-08
申请人： Frederic Reblewski , Olivier Lepape
发明人： Frederic Reblewski , Olivier Lepape
IPC分类号： G06F11/00
CPC分类号： H03K19/1776 , G06F11/1438 , H03K19/17764
摘要： A system and method for detecting corrupted configuration data stored in a configuration memory of a reconfigurable circuit are described herein.
摘要翻译：本文描述了用于检测存储在可重构电路的配置存储器中的损坏的配置数据的系统和方法。

36. 发明申请

US20070118783A1 Runtime reconfiguration of reconfigurable circuits 有权
标题翻译：可重构电路的运行时重新配置
公开(公告)号：US20070118783A1
公开(公告)日：2007-05-24
申请号：US11285988
申请日：2005-11-23
申请人： Frederic Reblewski
发明人： Frederic Reblewski
IPC分类号： G01R31/28
CPC分类号： G11C29/12 , G01R31/31707 , G06F11/27 , G11C29/72 , G11C2029/0409 , H03K19/17764
摘要： A reconfigurable circuit having primary function blocks with runtime built-in self-test (BIST) circuitry, one or more redundant function blocks and runtime reconfiguration logic is described herein.
摘要翻译：具有运行时内置自检（BIST）电路的主要功能块，一个或多个冗余功能块和运行时重新配置逻辑的可重构电路在此被描述。

37. 发明授权

US06934674B1 Clock generation and distribution in an emulation system 有权
标题翻译：仿真系统中的时钟生成和分配
公开(公告)号：US06934674B1
公开(公告)日：2005-08-23
申请号：US09404923
申请日：1999-09-24
申请人： Francois Douezy , Frederic Reblewski , Jean Barbier
发明人： Francois Douezy , Frederic Reblewski , Jean Barbier
IPC分类号： G06F11/22 , G06F1/04 , G06F1/08 , G06F1/10 , H03K5/135 , G06F9/455
CPC分类号： H03K5/135
摘要： A method and apparatus for clock generation and distribution in an emulation system is described. The present invention provides a method and apparatus for generating a derived clock signal with a circuit having a look up table. A counter circuit counts clock cycles and provides an index into the look up table. A frequency divider circuit may be used between the counter circuit and a base clock signal to provide an intermediate clock signal with a frequency that is less than the frequency of the base clock signal. In one embodiment, a selection circuit is provided to select between the base clock signal and an external clock signal.
摘要翻译：描述了仿真系统中的时钟产生和分配的方法和装置。本发明提供了一种用具有查找表的电路产生导出的时钟信号的方法和装置。计数器电路对时钟周期进行计数，并向查找表提供索引。可以在计数器电路和基本时钟信号之间使用分频器电路，以提供具有小于基本时钟信号的频率的频率的中间时钟信号。在一个实施例中，提供选择电路以在基本时钟信号和外部时钟信号之间进行选择。

38. 发明授权

US06717433B2 Reconfigurable integrated circuit with integrated debugging facilities and scalable programmable interconnect 有权
标题翻译：具有集成调试功能和可扩展可编程互连的可重构集成电路
公开(公告)号：US06717433B2
公开(公告)日：2004-04-06
申请号：US10086813
申请日：2002-02-28
申请人： Jean Barbier , Olivier LePape , Frederic Reblewski
发明人： Jean Barbier , Olivier LePape , Frederic Reblewski
IPC分类号： H03K1900
CPC分类号： G01R31/31705 , G01R31/318519 , G01R31/318544 , H03K19/17728 , H03K19/17736 , H03K19/1774 , H03K19/17748 , H03K19/17764 , H03K19/17772
摘要： A number of enhanced logic elements (LEs) are provided to form a reconfigurable integrated circuit (IC). Each enhanced LE comprises a multiple input-single output truth table, and a complementary pair of master-slave latches having a data, a set and a reset input. Each enhanced LE further comprises a plurality of multiplexers and buffers, and control logic. Additionally, the improved IC may further comprises a scalable network of crossbars, a context bus, a scan register, and/or a plurality of trigger circuitry. As a result, each LE may be individually initialized, its signal state frozen momentarily, the frozen state be read, trace data be output, and trigger inputs be conditionally generated, making the IC particularly suitable for circuit design emulation. Furthermore, the enhanced LEs may be used for “level sensitive” as well as “edge sensitive” circuit design emulations.
摘要翻译：提供了许多增强型逻辑元件（LE）以形成可重构集成电路（IC）。每个增强LE包括多输入单输出真值表，以及具有数据，集合和复位输入的互补对主控从锁存器。每个增强型LE还包括多个复用器和缓冲器以及控制逻辑。此外，改进的IC还可以包括交叉开关的可伸缩网络，上下文总线，扫描寄存器和/或多个触发电路。结果，每个LE可以单独初始化，其信号状态瞬间冻结，读取冻结状态，输出跟踪数据，有条件地产生触发输入，使得IC特别适用于电路设计仿真。此外，增强型LE可用于“电平敏感”以及“边缘敏感”电路设计仿真。

39. 发明授权

US06594810B1 Reconfigurable integrated circuit with a scalable architecture 有权
标题翻译：具有可扩展架构的可重构集成电路
公开(公告)号：US06594810B1
公开(公告)日：2003-07-15
申请号：US09971349
申请日：2001-10-04
申请人： Frederic Reblewski , Olivier Lepape
发明人： Frederic Reblewski , Olivier Lepape
IPC分类号： G06F1750
CPC分类号： H04Q3/68 , G06F15/7867 , H04Q2213/1302 , H04Q2213/1304 , H04Q2213/13109 , H04Q2213/13322
摘要： An integrated circuit (IC) includes a number of function blocks (FB), of which at least one is re-configurable. Each of the FBs may be a reconfigurable function or a non-reconfigurable function or recursively expanded with additional “nested” function blocks. The IC further includes a number of input pins, a number of output pins, and a number of crossbar devices. The elements, at least at the IC level, are coupled in a manner such that all input signals are provided to the FBs through a first subset of the crossbar devices, all internal signals are routed from one FB to another FB through a second subset of crossbar devices, and all output signals are routed from the FBs to the output pins through a third subset of crossbar devices. To increase routability and speed each of the crossbar device output has a single fanout. Additionally, each of the crossbar devices may provide only one input to each other crossbar device.
摘要翻译：集成电路（IC）包括多个功能块（FB），其中至少一个可重新配置。每个FB可以是可重新配置的功能或不可重新配置的功能，或者用附加的“嵌套”功能块递归地展开。 IC还包括多个输入引脚，多个输出引脚和多个交叉开关器件。至少在IC级别的元件以这样的方式耦合，使得所有输入信号通过交叉开关器件的第一子集提供给FB，所有内部信号通过第二子集的第二子集从一个FB路由到另一个FB 交叉开关器件，并且所有输出信号通过第三子交叉开关器件从FB路由到输出引脚。为了提高路由性和速度，每个交叉开关设备输出都有一个扇出。另外，每个横杠装置可以仅向每个其他横杆装置提供一个输入。

40. 发明授权

US06473726B1 Method and apparatus for concurrent emulation of multiple circuit designs on an emulation system 有权
标题翻译：用于在仿真系统上同时仿真多个电路设计的方法和装置
公开(公告)号：US06473726B1
公开(公告)日：2002-10-29
申请号：US09405659
申请日：1999-09-24
申请人： Frederic Reblewski
发明人： Frederic Reblewski
IPC分类号： G06F9455
CPC分类号： G06F17/5027
摘要： An emulation system equipped to emulate multiple circuit designs concurrently is disclosed. The emulation system includes an emulator having reconfigurable emulation resources for emulating circuit designs, and a host system programmed with programming instructions that operate to generate coordinated configuration information for a number of circuit designs to enable the reconfigurable emulation resources to be configured in a coordinated manner to allow the circuit designs to be emulated concurrently.
摘要翻译：公开了一种同时仿真多个电路设计的仿真系统。该仿真系统包括具有用于仿真电路设计的可重构仿真资源的仿真器，以及用编程指令编程的主机系统，该程序指令用于为多个电路设计生成协调配置信息，以使可重新配置的仿真资源以协调的方式配置允许电路设计同时仿真。

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