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31. 发明申请

US20100333056A1 TEMPERATURE-CONTROLLED 3-DIMENSIONAL BUS PLACEMENT 有权
标题翻译：温度控制三维总线布置
公开(公告)号：US20100333056A1
公开(公告)日：2010-12-30
申请号：US12493599
申请日：2009-06-29
申请人： Philip G. Emma , Eren Kursun , Jude A. Rivers
发明人： Philip G. Emma , Eren Kursun , Jude A. Rivers
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： Block placement within each device-containing layer is optimized under the constraint of a simultaneous optimization of interlayer connectivity between the device-containing layer and immediately adjacent device-containing layers. For each functional block within the device-containing layer, lateral heat flow is calculated to laterally adjacent functional blocks. If the lateral heat flow is less than a threshold value for a pair of adjacent functional blocks, placement of the functional blocks and/or interlayer interconnect structure array therebetween or modification of the interlayer interconnect structure array is performed. This routine is repeated for all adjacent pairs of functional blocks in each of the device-containing layers. Subsequently, block placement within each device-containing layer may be optimized under the constraint of a simultaneous optimization of interlayer connectivity across all device-containing layers. This method provides a design having sufficient lateral heat flow in each of the device-containing layers in a semiconductor chip.
摘要翻译：在包含装置的层和紧邻相邻的装置层之间的层间连通性的同时优化的限制下，在每个含有装置的层内的块放置被优化。对于含有装置的层内的每个功能块，横向热流被计算为横向相邻的功能块。如果侧向热流小于一对相邻功能块的阈值，则在其间布置功能块和/或层间互连结构阵列或者修改层间互连结构阵列。对于每个含设备的层中的所有相邻的功能块对，重复此例程。随后，可以在跨所有含有装置的层的层间连接的同时优化的约束下优化在每个包含装置的层内的块放置。该方法提供了在半导体芯片中的每个含有器件的层中具有足够的横向热流的设计。

32. 发明授权

US09390989B2 Enhanced modularity in heterogeneous 3D stacks 有权
标题翻译：在异构3D堆栈中增强模块化
公开(公告)号：US09390989B2
公开(公告)日：2016-07-12
申请号：US13535694
申请日：2012-06-28
申请人： Philip G. Emma , Eren Kursun , Jude A. Rivers
发明人： Philip G. Emma , Eren Kursun , Jude A. Rivers
IPC分类号： G06F17/50 , H01L23/14 , H05K3/46 , H01L23/13 , H01L23/538 , H01L25/065 , H01L25/18 , H05K3/30 , H01L21/48
CPC分类号： H01L23/147 , H01L21/4803 , H01L23/13 , H01L23/5382 , H01L23/5389 , H01L25/0652 , H01L25/18 , H01L2225/06575 , H01L2225/06589 , H01L2924/0002 , H01L2924/15311 , H05K3/30 , H05K3/465 , Y10T29/49128 , Y10T29/4913 , Y10T29/49137 , Y10T29/49146 , H01L2924/00
摘要： A computer program product for generating and implementing a three-dimensional (3D) computer processing chip stack plan. The computer readable program code includes computer readable program code configured for receiving system requirements from a plurality of clients, identifying common processing structures and technologies from the system requirements, and assigning the common processing structures and technologies to at least one layer in the 3D computer processing chip stack plan. The computer readable program code is also configured for identifying uncommon processing structures and technologies from the system requirements and assigning the uncommon processing structures and technologies to a host layer in the 3D computer processing chip stack plan. The computer readable program code is further configured for determining placement and wiring of the uncommon structures on the host layer, storing placement information in the plan, and transmitting the plan to manufacturing equipment. The manufacturing equipment forms the 3D computer processing chip stack.
摘要翻译：一种用于生成和实现三维（3D）计算机处理芯片堆栈计划的计算机程序产品。计算机可读程序代码包括被配置为从多个客户端接收系统需求的计算机可读程序代码，从系统要求中识别公共处理结构和技术，以及将公共处理结构和技术分配给3D计算机处理中的至少一个层芯片堆栈计划。计算机可读程序代码还被配置用于根据系统要求识别不常见的处理结构和技术，并将不常见的处理结构和技术分配给3D计算机处理芯片堆栈计划中的主机层。计算机可读程序代码还被配置用于确定主机层上的不常见结构的布置和布线，将布置信息存储在计划中，并将该计划传送到制造设备。制造设备构成3D计算机处理芯片堆栈。

33. 发明授权

US08959224B2 Network data packet processing 有权
标题翻译：网络数据包处理
公开(公告)号：US08959224B2
公开(公告)日：2015-02-17
申请号：US13299045
申请日：2011-11-17
申请人： Claude Basso , Jean L. Calvignac , Hubertus Franke , Eren Kursun
发明人： Claude Basso , Jean L. Calvignac , Hubertus Franke , Eren Kursun
IPC分类号： G06F15/173 , G06F9/46 , G06F1/32 , G06F9/50
CPC分类号： G06F1/3209 , G06F9/5094 , Y02D10/22
摘要： A method and apparatus for processing of data packets by a data processing component comprising a plurality of processing resources. A metric value for a current configuration of the processing resources that are processing the data packets is identified. A new configuration of the processing resources is selected using the metric value. The current configuration of the processing resources is changed to the new configuration and data packets are distributed to the new configuration for processing as the data packets are received.
摘要翻译：一种由包括多个处理资源的数据处理组件处理数据分组的方法和装置。识别处理数据分组的处理资源的当前配置的度量值。使用度量值选择处理资源的新配置。处理资源的当前配置被改变为新的配置，并且数据分组被分配到新配置，以便在接收到数据分组时进行处理。

34. 发明申请

US20140333413A1 Systems And Methods For High Fidelity Multi-Modal Out-Of-Band Biometric Authentication 有权
标题翻译：用于高保真多模态带外生物识别的系统和方法
公开(公告)号：US20140333413A1
公开(公告)日：2014-11-13
申请号：US13908618
申请日：2013-06-03
申请人： Eren Kursun
发明人： Eren Kursun
IPC分类号： G06K9/00
CPC分类号： G06K9/00892
摘要： Systems and methods for high fidelity multi-modal out-of-band biometric authentication are disclosed. According to one embodiment, a method for multi-mode biometric authentication may include (1) receiving, at a computer application executed by an electronic device, a first input from a first input device on the electronic device; (2) receiving, at the computer application, a second data from a second input device on the electronic device; (3) receiving, at the computer application, a third input from a third input device on the electronic device; and (4) communicating, by the computer application and to a server, the first input, the second input, and the third input. The first input, second input and third input may be received within a predetermined time period, such as five seconds.
摘要翻译：公开了用于高保真多模式带外生物认证的系统和方法。根据一个实施例，一种用于多模式生物认证的方法可以包括（1）在由电子设备执行的计算机应用处接收来自电子设备上的第一输入设备的第一输入; （2）在计算机应用中从电子设备上的第二输入设备接收第二数据; （3）在计算机应用中从电子设备上的第三输入设备接收第三输入; 和（4）由计算机应用程序和服务器将第一输入，第二输入和第三输入进行通信。第一输入，第二输入和第三输入可以在预定时间段内接收，例如五秒。

35. 发明授权

US08549363B2 Reliability and performance of a system-on-a-chip by predictive wear-out based activation of functional components 失效
标题翻译：通过基于功能组件的预先磨损的激活来实现片上系统的可靠性和性能
公开(公告)号：US08549363B2
公开(公告)日：2013-10-01
申请号：US12727967
申请日：2010-03-19
申请人： Chen-Yong Cher , Paul W. Coteus , Alan Gara , Eren Kursun , David P. Paulsen , Brian A. Schuelke , John E. Sheets, II , Shurong Tian
发明人： Chen-Yong Cher , Paul W. Coteus , Alan Gara , Eren Kursun , David P. Paulsen , Brian A. Schuelke , John E. Sheets, II , Shurong Tian
IPC分类号： G06F11/30
CPC分类号： G06F17/5045 , G01R31/31725
摘要： A processor-implemented method for determining aging of a processing unit in a processor the method comprising: calculating an effective aging profile for the processing unit wherein the effective aging profile quantifies the effects of aging on the processing unit; combining the effective aging profile with process variation data, actual workload data and operating conditions data for the processing unit; and determining aging through an aging sensor of the processing unit using the effective aging profile, the process variation data, the actual workload data, architectural characteristics and redundancy data, and the operating conditions data for the processing unit.
摘要翻译：一种用于确定处理器中处理单元的老化的处理器实现的方法，该方法包括：计算处理单元的有效老化简档，其中有效老化简档量化老化对处理单元的影响; 将有效的老化轮廓与处理单元的过程变化数据，实际工作负载数据和操作条件数据相结合; 以及通过所述处理单元的老化传感器使用所述有效老化简档，所述过程变化数据，所述实际工作负载数据，架构特征和冗余数据以及所述处理单元的操作条件数据来确定老化。

36. 发明申请

US20130254526A1 EFFECT TRANSLATION AND ASSESSMENT AMONG MICROARCHITECTURE COMPONENTS 有权
标题翻译：微观组成部分的有效翻译和评估
公开(公告)号：US20130254526A1
公开(公告)日：2013-09-26
申请号：US13429587
申请日：2012-03-26
申请人： Bulent Abali , Michael S. Floyd , Eren Kursun
发明人： Bulent Abali , Michael S. Floyd , Eren Kursun
IPC分类号： G06F9/06
CPC分类号： G06F11/3024 , G06F11/3058 , G06F11/3062 , G06F11/3409 , G06F11/3433 , G06F11/348 , G06F2209/501 , G06F2209/508
摘要： Awareness of the relationships among the operating parameters for an individual core and among cores allows dynamic and intelligent management of the multi-core system. The relationships among operating parameters and cores, which can be somewhat opaque, are established with design-time simulations, and adapted with run time data collected from operation of the multi-core system. The relationships are expressed with functions that translate between operating parameters, between different cores, and between operating parameters of different cores. These functions are embodied in circuitry built into the multi-core system. The circuitry will be referred to hereinafter as a translator unit. The translator unit traverses the complex relational dependencies among multiple operating parameters and multiple cores, and determines an outcome with respect to one or more constraints corresponding to those operating parameters and cores.
摘要翻译：意识到单个核心和核心的运行参数之间的关系允许多核系统的动态和智能管理。可以通过设计时模拟建立操作参数和核心之间的关系，这些关系可能有些不透明，并且适用于从多核系统运行收集的运行时数据。这些关系用转换操作参数，不同内核之间以及不同内核的操作参数之间的函数表示。这些功能体现在内置于多核系统中的电路中。电路在下文中将被称为翻译单元。翻译器单元遍历多个操作参数和多个核心之间的复杂关系依赖关系，并且确定与这些操作参数和核心相对应的一个或多个约束的结果。

37. 发明授权

US08543959B2 Bonding controller guided assessment and optimization for chip-to-chip stacking 有权
标题翻译：键合控制器引导评估和优化，用于芯片到芯片堆叠
公开(公告)号：US08543959B2
公开(公告)日：2013-09-24
申请号：US13087464
申请日：2011-04-15
申请人： Gary Dale Carpenter , Alan James Drake , Eren Kursun
发明人： Gary Dale Carpenter , Alan James Drake , Eren Kursun
IPC分类号： G06F17/50
CPC分类号： H01L25/0657 , H01L25/50 , H01L2225/06513 , H01L2225/06541 , H01L2225/06565 , H01L2924/0002 , H01L2924/00
摘要： A method, system, and computer program product for performance-based chip-to-chip stacking are provided in the illustrative embodiments. A first candidate chip is selected from a set of candidate chips for stacking, each candidate chip in the set of candidate chips including an integrated circuit. A part of a 3D performance determinant is activated in the first candidate chip. A value of a performance parameter is measured for a set of operating conditions. A stacked performance value is computed for the first candidate chip using the value. A subset of the set of candidate chips is stacked in a stack, the subset including the first candidate chip, such that a combined value of the performance parameter for the subset when stacked in a first order is within a defined range of values for the performance parameter.
摘要翻译：在说明性实施例中提供了用于基于性能的芯片到芯片堆叠的方法，系统和计算机程序产品。从用于堆叠的候选芯片的集合中选择第一候选芯片，所述候选芯片组中的每个候选芯片包括集成电路。在第一候选芯片中激活3D性能决定因素的一部分。对于一组操作条件测量性能参数的值。使用该值计算第一候选芯片的堆叠性能值。所述候选芯片组的子集被堆叠在堆叠中，所述子集包括第一候选芯片，使得当以第一顺序堆叠时子集的性能参数的组合值在所述性能的值的确定范围内参数。

38. 发明授权

US08542030B2 Three-dimensional (3D) stacked integrated circuit testing 有权
标题翻译：三维（3D）堆叠集成电路测试
公开(公告)号：US08542030B2
公开(公告)日：2013-09-24
申请号：US12942662
申请日：2010-11-09
申请人： Chen-Yong Cher , Eren Kursun , Gary W. Maier , Raphael Peter Robertazzi
发明人： Chen-Yong Cher , Eren Kursun , Gary W. Maier , Raphael Peter Robertazzi
IPC分类号： G01R31/26
CPC分类号： G01R31/2817 , G01R31/287
摘要： Testing of a three-dimensional (3D) integrated circuit includes defining a first group of parts by a region and/or layer on the 3D integrated circuit. The testing further includes applying a first intensity of stress test conditions to the first group of parts. The testing also includes defining a second group of parts by a region and/or layer on the 3D integrated circuit that is different from the first group of parts. The testing further includes and applying a second intensity of stress test conditions to the second group of parts. The second intensity of stress test conditions is greater than the first intensity and is determined by sensitivities identified for each of the first and second group of parts. A determination is made whether the 3D integrated circuit passed the testing based upon results of application of the first and second intensities of stress test conditions.
摘要翻译：三维（3D）集成电路的测试包括通过3D集成电路上的区域和/或层定义第一组部分。测试还包括将第一强度的应力测试条件应用于第一组零件。测试还包括通过与第一组部件不同的3D集成电路上的区域和/或层定义第二组部件。测试进一步包括并将第二强度的应力测试条件应用于第二组零件。应力测试条件的第二强度大于第一强度，并且由针对第一组和第二组部件确定的灵敏度确定。根据第一和第二强度应力测试条件的应用结果，确定3D集成电路是否通过了测试。

39. 发明授权

US08473762B2 Power delivery in a heterogeneous 3-D stacked apparatus 有权
标题翻译：在异种3-D堆叠设备中的功率输送
公开(公告)号：US08473762B2
公开(公告)日：2013-06-25
申请号：US13552091
申请日：2012-07-18
申请人： Robert H. Dennard , Eren Kursun
发明人： Robert H. Dennard , Eren Kursun
IPC分类号： G06F1/00 , G06F1/26 , H01L23/02 , H01L23/52 , H02J1/10 , B23K11/24
CPC分类号： H01L25/18 , H01L23/642 , H01L25/0657 , H01L2224/16145 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , Y10T307/50
摘要： A heterogeneous three-dimensional (3-D) stacked apparatus is provided that includes multiple layers arranged in a stacked configuration with a lower layer configured to receive a board-level voltage and one or more upper layers stacked above the lower layer. The heterogeneous 3-D stacked apparatus also includes multiple tiles per layer, where each tile is designed to receive a separately regulated voltage. The heterogeneous 3-D stacked apparatus additionally includes at least one layer in the one or more upper layers with voltage converters providing the separately regulated voltage converted from the board-level voltage.
摘要翻译：提供了一种不均匀的三维（3-D）层叠装置，其包括以堆叠配置布置的多个层，其中下层被配置为接收板级电压，以及堆叠在下层上方的一个或多个上层。异质三维层叠装置还包括每层多个瓦片，其中每个瓦片被设计成接收单独调节的电压。异质三层堆叠装置还包括在一个或多个上层中的至少一个层，其中电压转换器提供从板级电压转换的单独调节的电压。

40. 发明授权

US08424006B2 Task assignment on heterogeneous three-dimensional/stacked microarchitectures 失效
标题翻译：异构三维/堆叠微架构上的任务分配
公开(公告)号：US08424006B2
公开(公告)日：2013-04-16
申请号：US12793231
申请日：2010-06-03
申请人： Hans M. Jacobson , Eren Kursun
发明人： Hans M. Jacobson , Eren Kursun
IPC分类号： G06F9/46
CPC分类号： G06F1/206 , G06F1/3203 , G06F9/5094 , Y02D10/22
摘要： A method of enhancing performance of a three-dimensional microarchitecture includes determining a computational demand for performing a task, selecting an optimization criteria for the task, identifying at least one computational resource of the microarchitecture configured to meet the computational demand for performing the task, and calculating an evaluation criteria for the at least one computational resource based on the computational demand for performing the task. The evaluation criteria defines an ability of the computational resource to meet the optimization criteria. The method also includes assigning the task to the computational resource based on the evaluation criteria of the computational resource in order to proactively avoid creating a hot spot on the three-dimensional microarchitecture.
摘要翻译：提高三维微体系结构的性能的方法包括确定执行任务的计算需求，选择任务的优化标准，识别配置为满足执行任务的计算需求的微体系结构的至少一个计算资源，以及基于用于执行所述任务的计算需求来计算所述至少一个计算资源的评估标准。评估标准定义了计算资源满足优化标准的能力。该方法还包括基于计算资源的评估标准将任务分配给计算资源，以便主动避免在三维微体系结构上产生热点。

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