专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明授权

US08765587B2 Method of manufacturing non-volatile memory devices 有权
标题翻译：制造非易失性存储器件的方法
公开(公告)号：US08765587B2
公开(公告)日：2014-07-01
申请号：US13398235
申请日：2012-02-16
申请人： Su Hyun Lim , Seung Cheol Lee
发明人： Su Hyun Lim , Seung Cheol Lee
IPC分类号： H01L21/3205 , H01L21/302
CPC分类号： H01L27/11521 , H01L21/02057 , H01L21/3065 , H01L21/3086 , H01L21/76224
摘要： A method of manufacturing non-volatile memory devices includes forming a gate insulating layer and a first conductive layer over a semiconductor substrate, etching the first conductive layer and the gate insulating layer to expose part of the semiconductor substrate, forming trenches at a target depth of the semiconductor substrate by repeatedly performing a dry etch process for etching the exposed semiconductor substrate and a cleaning process for removing residues generated in the dry etch process, forming isolation layers within the trenches, forming a dielectric layer on a surface of the entire structure in which the isolation layers are formed, and forming a second conductive layer on the dielectric layer.
摘要翻译：一种制造非易失性存储器件的方法包括在半导体衬底上形成栅极绝缘层和第一导电层，蚀刻第一导电层和栅极绝缘层以暴露部分半导体衬底，在目标深度处形成沟槽通过重复执行用于蚀刻暴露的半导体衬底的干蚀刻工艺的半导体衬底和用于去除在干蚀刻工艺中产生的残留物的清洁工艺，在沟槽内形成隔离层，在整个结构的表面上形成介电层，其中形成隔离层，并在电介质层上形成第二导电层。

32. 发明授权

US08760934B2 3-D structured non-volatile memory device and method of manufacturing the same 有权
标题翻译： 3-D结构化非易失性存储器件及其制造方法
公开(公告)号：US08760934B2
公开(公告)日：2014-06-24
申请号：US13397024
申请日：2012-02-15
申请人： Hack Seob Shin , Sang Hyun Oh
发明人： Hack Seob Shin , Sang Hyun Oh
IPC分类号： G11C16/04
CPC分类号： H01L27/11582
摘要： A non-volatile memory device includes channel structures that each extend in a first direction, wherein the channel structures each include channel layers and interlayer dielectric layers that are alternately stacked; source structure extending in a second direction crossing the first direction and connected to ends of the channel structures, wherein the source structure includes source lines and interlayer dielectric layers that are alternately stacked; and word lines extending in the second direction and formed to surround the channel structures.
摘要翻译：非易失性存储器件包括各自沿第一方向延伸的通道结构，其中沟道结构各自包括交替层叠的沟道层和层间电介质层; 源结构在与第一方向交叉的第二方向上延伸并连接到沟道结构的端部，其中源结构包括交替层叠的源极线和层间电介质层; 以及在第二方向上延伸并形成为围绕通道结构的字线。

33. 发明授权

US08760181B2 Semiconductor system and device for identifying stacked chips and method thereof 有权
标题翻译：用于识别堆叠芯片的半导体系统和装置及其方法
公开(公告)号：US08760181B2
公开(公告)日：2014-06-24
申请号：US12914424
申请日：2010-10-28
申请人： Sang-Jin Byeon , Jong-Chern Lee
发明人： Sang-Jin Byeon , Jong-Chern Lee
IPC分类号： G01R31/36 , G11C5/02
CPC分类号： G11C11/4072 , G06F2213/0038 , G11C7/10 , G11C8/12 , G11C11/4076 , G11C16/20
摘要： A semiconductor system for identifying stacked chips includes a first semiconductor chip and a plurality of second semiconductor chips. The first semiconductor chip generates a plurality of counter codes by using an internal clock or an external input clock and transmits slave address signals and the counter codes through a through-chip via. The second semiconductor chips are given corresponding identifications (IDs) by latching the counter codes for a predetermined delay time, compare the latched counter codes with the slave address signals, and communicate data with the first semiconductor chip through the through-chip via according to the comparison result.
摘要翻译：用于识别堆叠芯片的半导体系统包括第一半导体芯片和多个第二半导体芯片。第一半导体芯片通过使用内部时钟或外部输入时钟产生多个计数器代码，并且通过片上通孔发送从地址信号和计数器代码。通过在预定的延迟时间内锁存计数器代码来对第二半导体芯片进行相应的标识（ID），将锁存的计数器代码与从地址信号进行比较，并根据通过芯片通过与第一半导体芯片通信数据比较结果。

34. 发明授权

US08759736B2 Column circuit and pixel binning circuit for image sensor 有权
标题翻译：图像传感器的列电路和像素合并电路
公开(公告)号：US08759736B2
公开(公告)日：2014-06-24
申请号：US12943255
申请日：2010-11-10
申请人： Si-Wook Yoo
发明人： Si-Wook Yoo
IPC分类号： H01L27/00
CPC分类号： H04N5/347 , H01L27/14609 , H04N5/3742
摘要： A column circuit for an image sensor includes a first column read circuit configured to read data of a first column line, and a second column read circuit configured to read data of a second column line, wherein, during a binning mode, data from two or more pixels are outputted through the first column line and stored in the first column read circuit in a first phase, data from two or more pixels are outputted through the second column line and stored in the second column read circuit in a second phase, and charges are shared between the first column read circuit and the second column read circuit in a third phase.
摘要翻译：用于图像传感器的列电路包括被配置为读取第一列线的数据的第一列读取电路和被配置为读取第二列线的数据的第二列读取电路，其中，在合并模式期间，来自两个或通过第一列线输出更多的像素并在第一相位中存储在第一列读取电路中，来自两个或更多个像素的数据通过第二列线输出，并在第二阶段中存储在第二列读取电路中，并且在第三阶段中在第一列读取电路和第二列读取电路之间共享。

35. 发明授权

US08738955B2 Semiconductor device and semiconductor system including the same 有权
标题翻译：半导体器件和包括其的半导体系统
公开(公告)号：US08738955B2
公开(公告)日：2014-05-27
申请号：US12977542
申请日：2010-12-23
申请人： Jung-Hoon Park
发明人： Jung-Hoon Park
IPC分类号： G06F11/14
CPC分类号： G06F11/14 , G11C29/02 , G11C29/023 , G11C29/028
摘要： A semiconductor device includes an internal circuit configured to perform a specified operation in response to a predetermined command; a normal data input/output section configured to input/output a normal data synchronized with a center of a source clock, in response to data input/output commands; and a data recovery information signal input/output block configured to receive and store a data recovery information signal synchronized with an edge of the source clock and having a predetermined pattern, in response to either a command of the data input/output commands or the predetermined command upon entry to a data recovery operating mode, and to output the data recovery information signal after the passage of a predetermined time period.
摘要翻译：半导体器件包括：内部电路，被配置为响应于预定命令执行指定的操作; 响应于数据输入/输出命令，被配置为输入/输出与源时钟的中心同步的正常数据的正常数据输入/输出部分; 以及数据恢复信息信号输入/输出块，被配置为响应于数据输入/输出命令的命令或预定的数据输入/输出命令，接收并存储与源时钟的边缘同步且具有预定模式的数据恢复信息信号在进入数据恢复操作模式时进行命令，并且在经过预定时间段之后输出数据恢复信息信号。

36. 发明授权

US08709931B2 Fuse part in semiconductor device and method for forming the same 有权
标题翻译：半导体装置中的保险丝部件及其形成方法
公开(公告)号：US08709931B2
公开(公告)日：2014-04-29
申请号：US13325851
申请日：2011-12-14
申请人： Byung-Duk Lee
发明人： Byung-Duk Lee
IPC分类号： H01L21/44
CPC分类号： H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： A fuse part in a semiconductor device has a plurality of fuse lines extended along a first direction with a given width along a second direction. The fuse part includes a first conductive pattern having a space part formed in a fuse line region over a substrate, wherein portions of the first conductive pattern are spaced apart by the space part along the first direction. The fuse part includes a first insulation pattern formed over the space part, the first insulation pattern having a width smaller than a width of the first conductive pattern along the second direction and a thickness greater than a thickness of the first conductive pattern, and a second conductive pattern formed over the first insulation pattern, the second conductive pattern having a width greater than the width of the first insulation pattern along the second direction.
摘要翻译：半导体器件中的熔丝部分具有沿第一方向延伸的多条熔丝，沿着第二方向具有给定的宽度。熔丝部分包括第一导电图案，其具有形成在衬底上的熔丝线区域中的空间部分，其中第一导电图案的部分沿着第一方向由空间部分间隔开。熔丝部分包括形成在空间部分上的第一绝缘图案，第一绝缘图案的宽度小于第一导电图案沿着第二方向的宽度，并且厚度大于第一导电图案的厚度，第二绝缘图案导电图案形成在第一绝缘图案上，第二导电图案的宽度大于沿着第二方向的第一绝缘图案的宽度。

37. 发明授权

US08665664B2 Semiconductor memory device, memory system including the same, and method for adjusting timing between internal clock and command 有权
标题翻译：半导体存储器件，包括其的存储器系统以及用于调整内部时钟和命令之间的时序的方法
公开(公告)号：US08665664B2
公开(公告)日：2014-03-04
申请号：US12833048
申请日：2010-07-09
申请人： Jinyeong Moon , Sang-Sic Yoon
发明人： Jinyeong Moon , Sang-Sic Yoon
IPC分类号： G11C8/18
CPC分类号： G11C7/22 , G11C7/1051 , G11C7/1066 , G11C7/222 , G11C2207/2254
摘要： A method for adjusting a timing between an internal clock and a command in a gear down mode of a memory device includes detecting a sync pulse at rising and falling edges of the internal clock, and adjusting between the internal clock of the memory device and the command according to the detection result.
摘要翻译：一种用于调整存储器件的减速模式下的内部时钟和命令之间的定时的方法，包括：检测内部时钟的上升沿和下降沿的同步脉冲，以及在存储器件的内部时钟与指令之间进行调整根据检测结果。

38. 发明授权

US08659943B2 Nonvolatile memory device, method for fabricating the same, and method for operating the same 失效
标题翻译：非易失性存储器件及其制造方法及其操作方法
公开(公告)号：US08659943B2
公开(公告)日：2014-02-25
申请号：US13333924
申请日：2011-12-21
申请人： Nam-Jae Lee
发明人： Nam-Jae Lee
IPC分类号： G11C11/34
CPC分类号： H01L29/788 , G11C16/0483 , G11C16/10 , H01L27/11524 , H01L29/66825
摘要： A nonvolatile memory device includes bit and source lines alternately arranged parallel to each other and even strings and odd strings alternately arranged between the bit lines and the source lines and each including drain selection transistors, memory transistors, and a source selection transistor. The drain selection transistors include a first drain selection transistor with the same structure as the memory transistors and a second drain selection transistor with the same structure as the source selection transistor. The nonvolatile memory device further includes an even drain selection line connected to the first drain selection transistors of the even strings and the second drain selection transistors of the odd strings and an odd drain selection line connected to the second drain selection transistors of the even strings and the first drain selection transistors of the odd strings.
摘要翻译：非易失性存储器件包括彼此平行交替布置的位线和源极线，以及交替地布置在位线和源极线之间的偶数串和奇数串，并且每个包括漏极选择晶体管，存储晶体管和源极选择晶体管。漏极选择晶体管包括具有与存储晶体管相同结构的第一漏极选择晶体管和具有与源极选择晶体管相同结构的第二漏极选择晶体管。非易失性存储器件还包括连接到偶数串的第一漏极选择晶体管和奇数串的第二漏极选择晶体管和连接到偶数串的第二漏极选择晶体管的奇数漏极选择线的偶极漏极选择线，以及奇数串的第一个漏极选择晶体管。

39. 发明授权

US08654599B2 Bit line precharge circuit and a semiconductor memory apparatus using the same 失效
标题翻译：位线预充电电路和使用其的半导体存储装置
公开(公告)号：US08654599B2
公开(公告)日：2014-02-18
申请号：US13441291
申请日：2012-04-06
申请人： Hyung Sik Won
发明人： Hyung Sik Won
IPC分类号： G11C7/02
CPC分类号： G11C7/12 , G11C7/22
摘要： A bit line precharge circuit includes a precharge signal generation unit configured to generate first and second precharge signals that are enabled at different timing points by receiving a bit line equalizing signal; a first precharge unit configured to connect a pair of bit lines to each other in response to the first precharge signal and supply a bit line precharge voltage to the pair of bit lines; and a second precharge unit configured to supply the bit line precharge voltage to the bit line in response to the second precharge signal.
摘要翻译：位线预充电电路包括：预充电信号生成单元，被配置为产生通过接收位线均衡信号而在不同的定时点使能的第一和第二预充电信号; 第一预充电单元，被配置为响应于所述第一预充电信号将一对位线彼此连接，并且向所述一对位线提供位线预充电电压; 以及第二预充电单元，被配置为响应于所述第二预充电信号而将所述位线预充电电压提供给所述位线。

40. 发明授权

US08653575B2 Semiconductor device having vertical gate including active pillar 有权
标题翻译：具有包括有源柱的垂直栅极的半导体器件
公开(公告)号：US08653575B2
公开(公告)日：2014-02-18
申请号：US13176321
申请日：2011-07-05
申请人： Young-Kyun Jung
发明人： Young-Kyun Jung
IPC分类号： H01L27/108
CPC分类号： H01L29/66666 , H01L27/10876 , H01L27/10885 , H01L29/7827
摘要： A method for fabricating a semiconductor device includes forming buried bit lines separated from each other by a trench in a substrate, forming a plurality of first pillar holes that expose a top surface of the substrate, forming first active pillars buried in the first pillar holes, forming a gate conductive layer over entire surface of a resultant structure including the first active pillars, forming a gate electrode by etching the gate conducting layer to cover the first active pillars, forming a plurality of second pillar holes that expose the first active pillars by partially etching the gate electrode, and forming second active pillars buried in the second pillar holes and connected to the first active pillars.
摘要翻译：一种制造半导体器件的方法包括：通过衬底中的沟槽形成彼此分离的掩埋位线，形成暴露衬底顶表面的多个第一柱孔，形成埋在第一柱孔中的第一活性柱，在包括第一活性柱的所得结构的整个表面上形成栅极导电层，通过蚀刻栅极导电层以覆盖第一有源支柱形成栅极电极，形成多个第二柱状孔，其部分地暴露第一活性柱蚀刻栅电极，以及形成埋在第二柱孔中并连接到第一活动柱的第二活性柱。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式