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31. 发明申请

US20040103377A1 Optimization of cell subtypes in a hierarchical design flow 失效
标题翻译：在分层设计流程中优化细胞亚型
公开(公告)号：US20040103377A1
公开(公告)日：2004-05-27
申请号：US10620330
申请日：2003-07-14
申请人： Fulcrum Microsystems, Inc.
发明人： Frederik Eaton , Peter Beerel
IPC分类号： G06F017/50
CPC分类号： G06F17/5059 , G06F17/505 , G06F17/5068
摘要： Methods and apparatus are described for facilitating physical synthesis of a circuit design. The circuit design includes a plurality cell instances organized hierarchically. Each cell instance corresponds schematically to one of a plurality of cell types. Transistors in each of the cell instances is sized with reference to an objective function thereby resulting in a first plurality of cell subtypes for each cell type. Each cell subtype corresponding to a particular cell type differs from all other cell subtypes corresponding to the particular cell type by at least one transistor dimension. Selected ones of the subtypes for at least one of the cell types are merged thereby resulting in a second plurality of subtypes for the at least one of the cell types. The second plurality of subtypes being fewer than the first plurality of subtypes. The merging of the selected subtypes achieves a balance between the objective function and a cost associated with maintaining the selected subtypes distinct.
摘要翻译：描述了用于促进电路设计的物理合成的方法和装置。电路设计包括分层组织的多个小区实例。每个单元实例示意性地对应于多个单元类型之一。每个细胞实例中的晶体管参考目标函数来定尺寸，从而导致每个细胞类型的第一多个细胞亚型。对应于特定细胞类型的每个细胞亚型与通过至少一个晶体管尺寸对应于特定细胞类型的所有其它细胞亚型不同。合并至少一种细胞类型的选择的子类型，从而导致用于至少一种细胞类型的第二多个亚型。所述第二多个亚型比所述第一多个亚型少。所选子类型的合并实现了目标函数与维持选定子类型不同的成本之间的平衡。

32. 发明授权

US08448105B2 Clustering and fanout optimizations of asynchronous circuits 有权
标题翻译：异步电路的聚类和扇出优化
公开(公告)号：US08448105B2
公开(公告)日：2013-05-21
申请号：US12429772
申请日：2009-04-24
申请人： Georgios Dimou , Peter A. Beerel , Andrew Lines
发明人： Georgios Dimou , Peter A. Beerel , Andrew Lines
IPC分类号： G06F17/50
CPC分类号： G06F9/3869 , G06F17/5059
摘要： Techniques are described for generating asynchronous circuits from any arbitrary HDL representation of a synchronous circuit by automatically clustering the synthesized gates into pipeline stages that are then slack-matched to meet performance goals while minimizing area. Automatic pipelining can be provided in which the throughput of the overall design is not limited to the clock frequency or the level of pipelining in the original RTL specification. The techniques are applicable to many asynchronous design styles. A model and infrastructure can be designed that guides clustering to avoid the introduction of deadlocks and achieve a target circuit performance. Slack matching models can be used to take advantage of fanout optimizations of buffer trees that improve the quality of the results.
摘要翻译：描述了用于通过将合成门自动聚集到流水线阶段中以从同步电路的任何任意HDL表示生成异步电路的技术，该流水线阶段随机松弛匹配以满足性能目标同时最小化面积。可以提供自动流水线，其中总体设计的吞吐量不限于原始RTL规范中的时钟频率或流水线级别。这些技术适用于许多异步设计风格。可以设计一个模型和基础设施，指导群集，以避免引入死锁并实现目标电路性能。松弛匹配模型可用于利用提升结果质量的缓冲树的优化。

33. 发明申请

US20110080916A1 CONFIGURABLE FRAME PROCESSING PIPELINE IN A PACKET SWITCH 有权
标题翻译：一个分组开关中的可配置的框架加工管道
公开(公告)号：US20110080916A1
公开(公告)日：2011-04-07
申请号：US12575175
申请日：2009-10-07
申请人： Michael Davies , Robert Southworth
发明人： Michael Davies , Robert Southworth
IPC分类号： H04L12/56
CPC分类号： H04L49/1546 , H04L49/3009 , H04L49/3063 , H04L49/9094
摘要： Highly configurable frame processing pipelines are enabled in packet switches in an efficient manner which satisfies stringent area and power requirements. Frame processing pipelines are described that enable dynamic processing of different types of frames on a per frame basis.
摘要翻译：以高效的方式在分组交换机中启用高度可配置的帧处理流水线，满足严格的区域和功率要求。描述了帧处理管线，其能够以每帧为基础来动态处理不同类型的帧。

34. 发明申请

US20100325370A1 SHARED-MEMORY SWITCH FABRIC ARCHITECTURE 审中-公开
标题翻译：共享开关织物结构
公开(公告)号：US20100325370A1
公开(公告)日：2010-12-23
申请号：US12862539
申请日：2010-08-24
申请人： Uri Cummings , Andrew Lines , Patrick Pelletier , Robert Southworth
发明人： Uri Cummings , Andrew Lines , Patrick Pelletier , Robert Southworth
IPC分类号： G06F12/02
CPC分类号： G11C7/1048 , G11C7/1075 , H04L49/101 , H04L49/103 , H04L49/351
摘要： A shared memory is described having a plurality of receive ports and a plurality of transmit ports characterized by a first data rate. A memory includes a plurality of memory banks organized in rows and columns. Operation of the memory array is characterized by a second data rate. Non-blocking receive crossbar circuitry is operable to connect any of the receive ports with any of the memory banks. Non-blocking transmit crossbar circuitry is operable to connect any of the memory banks with any of the transmit ports. Buffering is operable to decouple operation of the receive and transmit ports at the first data rate from operation of the memory array at the second data rate. Scheduling circuitry is configured to control interaction of the ports, crossbar circuitry, and memory array to effect storage and retrieval of frames of data in the shared memory by sequentially querying the plurality of ports for the frames of data, and arbitrating among a subset of the ports having the frames of data to assign starting locations in the memory banks such that the shared memory is fully provisioned for all of the ports simultaneously operating at the maximum port data rate.
摘要翻译：描述了具有多个接收端口和以第一数据速率为特征的多个发送端口的共享存储器。存储器包括以行和列组织的多个存储器组。存储器阵列的操作的特征在于第二数据速率。非阻塞接收交叉开关电路可操作以将任何接收端口与任何存储器组连接。非阻塞发射交叉开关电路可操作以将任何存储体与任何发射端口连接。缓冲可操作以使第一数据速率处的接收和发送端口的操作与第二数据速率下的存储器阵列的操作分离。调度电路被配置为控制端口，交叉开关电路和存储器阵列的交互，以通过对多个端口顺序地查询数据帧来实现对共享存储器中的数据帧的存储和检索，并且在具有数据帧的端口，以分配存储器组中的起始位置，使得共享存储器被完全配置为以最大端口数据速率同时工作的所有端口。

35. 发明授权

US07698535B2 Asynchronous multiple-order issue system architecture 失效
标题翻译：异步多阶问题系统架构
公开(公告)号：US07698535B2
公开(公告)日：2010-04-13
申请号：US10667152
申请日：2003-09-16
申请人： Andrew Lines , Robert Southworth , Uri Cummings
发明人： Andrew Lines , Robert Southworth , Uri Cummings
IPC分类号： G06F9/38
CPC分类号： G06F9/3836 , G06F9/3851 , G06F9/3857 , G06F9/3885
摘要： An asynchronous circuit is described for processing units of data having a program order associated therewith. The circuit includes an N-way-issue resource comprising N parallel pipelines. Each pipeline is operable to transmit a subset of the units of data in a first-in-first-out manner. The asynchronous circuit is operable to sequentially control transmission of the units of data in the pipelines such that the program order is maintained.
摘要翻译：描述了用于处理具有与其相关联的程序顺序的数据单元的异步电路。该电路包括N路并行流水线的N路发行资源。每个流水线可操作地以先进先出的方式传输数据单元的子集。异步电路可操作以顺序地控制管道中的数据单元的传输，从而保持程序顺序。

36. 发明授权

US07584449B2 Logic synthesis of multi-level domino asynchronous pipelines 失效
标题翻译：多级多米诺异步管道逻辑综合
公开(公告)号：US07584449B2
公开(公告)日：2009-09-01
申请号：US11271323
申请日：2005-11-10
申请人： Peter Beerel , Andrew Lines , Michael Davies
发明人： Peter Beerel , Andrew Lines , Michael Davies
IPC分类号： G06F17/50
CPC分类号： G06F17/5059
摘要： Methods and apparatus are described for optimizing a circuit design. A gate level circuit description corresponding to the circuit design is generated. The gate level circuit description includes a plurality of pipelines across a plurality of levels. Using a linear programming technique, a minimal number of buffers is added to selected ones of the pipelines such that a performance constraint is satisfied.
摘要翻译：描述了用于优化电路设计的方法和装置。产生对应于电路设计的门级电路描述。门级电路描述包括跨越多个级别的多条管道。使用线性编程技术，将最少数量的缓冲区添加到选定的管道中，使得满足性能约束。

37. 发明申请

US20080259798A1 FLOW AND CONGESTION CONTROL IN SWITCH ARCHITECTURES FOR MULTI-HOP, MEMORY EFFICIENT FABRICS 有权
标题翻译：多用途记忆效能织物开关结构中的流量控制与控制
公开(公告)号：US20080259798A1
公开(公告)日：2008-10-23
申请号：US11737511
申请日：2007-04-19
申请人： Zhi-Hern Loh , Michael Davies , Uri Cummings
发明人： Zhi-Hern Loh , Michael Davies , Uri Cummings
IPC分类号： G08C15/00
CPC分类号： H04L47/10 , H04L45/302 , H04L47/11 , H04L47/125 , H04L49/103 , H04L49/205 , H04L49/254 , H04L49/508
摘要： A shared memory switch and switch fabric architecture are described which employ partitions of the shared memory to implement multiple, independent virtual congestion domains, thereby allowing congestion to be handled for different classes of traffic independently.
摘要翻译：描述共享存储器交换机和交换矩阵体系结构，其使用共享存储器的分区来实现多个独立的虚拟拥塞域，从而允许独立地针对不同类别的业务处理拥塞。

38. 发明授权

US07283557B2 Asynchronous crossbar with deterministic or arbitrated control 有权
公开(公告)号：US07283557B2
公开(公告)日：2007-10-16
申请号：US10136025
申请日：2002-04-30
申请人： Uri Cummings , Andrew Lines
发明人： Uri Cummings , Andrew Lines
IPC分类号： H04J3/02
CPC分类号： H04Q3/0004
摘要： Methods and apparatus are described relating to a crossbar which is operable to route data from any of a first number of input channels to any of a second number of output channels according to routing control information. Each combination of an input channel and an output channel corresponds to one of a plurality of links. The crossbar circuitry is operable to route the data in a deterministic manner on each of the links thereby preserving a partial ordering represented by the routing control information. Events on different links are uncorrelated.

39. 发明授权

US07274709B2 Asynchronous crossbar with deterministic or arbitrated control 有权
公开(公告)号：US07274709B2
公开(公告)日：2007-09-25
申请号：US10237358
申请日：2002-09-06
申请人： Uri Cummings , Andrew Lines
发明人： Uri Cummings , Andrew Lines
IPC分类号： H04J3/02
CPC分类号： H04Q3/0004
摘要： Methods and apparatus are described relating to a crossbar which is operable to route data from any of a first number of input channels to any of a second number of output channels according to routing control information. Each combination of an input channel and an output channel corresponds to one of a plurality of links. The crossbar circuitry is operable to route the data in a deterministic manner on each of the links thereby preserving a partial ordering represented by the routing control information. Events on different links are uncorrelated.

40. 发明授权

US07239669B2 Asynchronous system-on-a-chip interconnect 有权
标题翻译：异步片上系统互连
公开(公告)号：US07239669B2
公开(公告)日：2007-07-03
申请号：US10634597
申请日：2003-08-04
申请人： Uri Cummings , Andrew Lines
发明人： Uri Cummings , Andrew Lines
IPC分类号： H04L27/04
CPC分类号： G06F13/423 , G06F1/12 , G06F2213/0038 , H04L7/005 , H04L7/02 , H04L49/101 , H04L2012/5674 , H04Q3/0004 , H04Q2213/13034 , H04Q2213/13214 , H04Q2213/13322 , H04Q2213/13361 , H04Q2213/13362
摘要： Methods and apparatus are described relating to a system-on-a-chip which includes a plurality of synchronous modules, each synchronous module having an associated clock domain characterized by a data rate, the data rates comprising a plurality of different data rates. The system-on-a-chip also includes a plurality of clock domain converters. Each clock domain converter is coupled to a corresponding one of the synchronous modules, and is operable to convert data between the clock domain of the corresponding synchronous module and an asynchronous domain characterized by transmission of data according to an asynchronous handshake protocol. An asynchronous crossbar is coupled to the plurality of clock domain converters, and is operable in the asynchronous domain to implement a first-in-first-out (FIFO) channel between any two of the clock domain converters, thereby facilitating communication between any two of the synchronous modules.
摘要翻译：描述了涉及包括多个同步模块的片上系统的方法和装置，每个同步模块具有由数据速率表征的相关联的时钟域，数据速率包括多个不同的数据速率。片上系统还包括多个时钟域转换器。每个时钟域转换器被耦合到对应的一个同步模块，并且可操作以在对应的同步模块的时钟域和根据异步握手协议的数据传输特征的异步域之间转换数据。异步交叉开关耦合到多个时钟域转换器，并且可在异步域中操作以实现任何两个时钟域转换器之间的先进先出（FIFO）通道，从而促进任何两个时钟域转换器之间的通信同步模块。

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