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21. 发明授权

US11271568B2 Frequency divider circuit, communication circuit, and integrated circuit 有权
公开(公告)号：US11271568B2
公开(公告)日：2022-03-08
申请号：US17118331
申请日：2020-12-10
申请人： SOCIONEXT INC.
发明人： Hideki Kano
IPC分类号： H03K23/00 , H03K19/17736 , H03K19/096 , H03K21/02 , H03K21/10 , H03K23/58 , H03K23/60
摘要： A frequency divider circuit includes: a first latch circuit that including: a pair of input transistors each having a gate thereof configured to connect to a signal line to which a first voltage is supplied; and a pair of output nodes, and configured to receive a single-phase clock signal; and a second latch circuit of SR-type, the second latch circuit having a set input thereof and a reset input thereof configured to connect to the pair of output nodes of the first latch circuit, and configured to output differential clock signals of which frequency is half a frequency of the single-phase clock signal. The first latch circuit is configured to perform amplification and reset operations alternately repeatedly in response to the single-phase clock signal.

22. 发明授权

US11146273B2 Electronic device and electronic product 有权
公开(公告)号：US11146273B2
公开(公告)日：2021-10-12
申请号：US17180887
申请日：2021-02-22
申请人： Realtek Semiconductor Corp.
发明人： Chia-Chun Hung , Chih-Wei Ho , Chin-Wen Wang , Liang-Hui Li , Yi-Cheng Chen
IPC分类号： H03K23/00 , H03K23/42 , H03K23/58 , H03K21/38 , H03K21/40
摘要： The present invention provides an electronic device including a wireless communication module, a counter and a processing circuit. The wireless communication module is configured to receive a first packet and a second packet from another electronic device, wherein the first packet includes a first counter value, the second packet includes a second counter value, and the first counter value and the second counter value correspond to two adjacent edges of an original signal of another electronic device, respectively. The processing circuit is configured to obtain a third counter value from the counter when the first packet is received, and obtain a fourth counter value from the counter when the second packet is received; and the processing circuit further generates an output signal that is substantially the same as the original signal according to the first counter value, the second counter value, the third counter value and the fourth counter value.

23. 发明授权

US10812086B2 N-bit counter and frequency divider 有权
公开(公告)号：US10812086B2
公开(公告)日：2020-10-20
申请号：US16585006
申请日：2019-09-27
申请人： REALTEK SEMICONDUCTOR CORPORATION
发明人： Jyi-Sy Lo
IPC分类号： H03K23/58 , H03K21/38 , H03K23/66
摘要： Disclosed is an N-bit counter including: an N-bit counting circuit starting counting from an initial value to generate a count value composed of N bits, and being loaded with the initial value to restart counting from the initial value when a reload signal changes from a first reload level to a second reload level; a reload signal generating circuit having the reload signal change from the first reload level to the second reload level when the logical conjunction of K bit(s) among the N bits changes from a first value to a second value; and a reset circuit having a reset signal change from a first reset level to a second reset level so as to have the reload signal change from the second reload level to the first reload level and thereby allow the N-bit counting circuit to restart counting.

24. 发明申请

US20200313659A1 CELL OF TRANSMISSION GATE FREE CIRCUIT AND INTEGRATED CIRCUIT LAYOUT INCLUDING THE SAME 审中-公开
公开(公告)号：US20200313659A1
公开(公告)日：2020-10-01
申请号：US16900854
申请日：2020-06-12
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
发明人： Ta-Pen GUO , Chi-Lin LIU , Shang-Chih HSIEH , Jerry Chang-Jui KAO , Li-Chun TIEN , Lee-Chung LU
IPC分类号： H03K3/0233 , H03K23/58 , H03K19/094 , H03K3/01 , H01L27/02 , H03K3/356 , H03K3/3562 , H01L27/118 , H01L27/092
摘要： A semiconductor standard cell of a flip-flop circuit includes semiconductor fins extending substantially parallel to each other along a first direction, electrically conductive wirings disposed on a first level and extending substantially parallel to each other along the first direction, and gate electrode layers extending substantially parallel to a second direction substantially perpendicular to the first direction and formed on a second level different from the first level. The flip-flop circuit includes transistors made of the semiconductor fins and the gate electrode layers, receives a data input signal, stores the data input signal, and outputs a data output signal indicative of the stored data in response to a clock signal, the clock signal is the only clock signal received by the semiconductor standard cell, and the data input signal, the clock signal, and the data output signal are transmitted among the transistors through at least the electrically conductive wirings.

25. 发明申请

US20200153441A1 N-bit counter and frequency divider 审中-公开
公开(公告)号：US20200153441A1
公开(公告)日：2020-05-14
申请号：US16585006
申请日：2019-09-27
申请人： REALTEK SEMICONDUCTOR CORPORATION
发明人： JYI-SY LO
IPC分类号： H03K23/58 , H03K23/66 , H03K21/38
摘要： Disclosed is an N-bit counter including: an N-bit counting circuit starting counting from an initial value to generate a count value composed of N bits, and being loaded with the initial value to restart counting from the initial value when a reload signal changes from a first reload level to a second reload level; a reload signal generating circuit having the reload signal change from the first reload level to the second reload level when the logical conjunction of K bit(s) among the N bits changes from a first value to a second value; and a reset circuit having a reset signal change from a first reset level to a second reset level so as to have the reload signal change from the second reload level to the first reload level and thereby allow the N-bit counting circuit to restart counting.

26. 发明授权

US09705507B1 Fixed frequency divider circuit 有权
公开(公告)号：US09705507B1
公开(公告)日：2017-07-11
申请号：US15158622
申请日：2016-05-19
申请人： Texas Instruments Incorporated
发明人： Dinesh Jain
IPC分类号： H03K21/00 , H03K21/02 , H03K5/05 , H03K23/58
CPC分类号： H03K21/026 , H03K5/05 , H03K23/58
摘要： Disclosed examples include frequency divider circuits to divide a high frequency first clock signal to generate an output clock signal at a lower frequency, including a delay circuit to provide a delayed clock signal, a divider circuit to provide a divided clock signal, a sub-sampling circuit to sub-sample the first clock signal with the divided clock signal, and a feedback circuit to set the delay value of the adjustable delay circuit according to the sub-sampled output signal.

27. 发明授权

US09294099B2 Hybrid synchronous/asynchronous counter 有权
标题翻译：混合同步/异步计数器
公开(公告)号：US09294099B2
公开(公告)日：2016-03-22
申请号：US14141458
申请日：2013-12-27
申请人： Rohit Goyal , Deepak Kumar Behera , Naman Gupta
发明人： Rohit Goyal , Deepak Kumar Behera , Naman Gupta
IPC分类号： H03K21/00 , H03K23/58 , H03K19/00 , H03K21/10 , H03K21/12
CPC分类号： H03K23/588 , H03K19/0008 , H03K21/10 , H03K21/12 , H03K23/58
摘要： A hybrid counter generates a multi-bit hybrid counter value. The hybrid counter includes two or more asynchronous counters, each configured to generate a subset of the bits of the multi-bit hybrid counter value. The asynchronous counters are interconnected by a logic gate and a clock gating circuit. The logic gate generates an asynchronous logic value based on the bits generated by the previous asynchronous counters. The clock gating circuit re-times the asynchronous logic value to generate a synchronous logic value that is used to toggle the next asynchronous counter. The hybrid counter functions more accurately than conventional asynchronous counters and with less power than conventional synchronous counters.
摘要翻译：混合计数器产生多位混合计数器值。混合计数器包括两个或多个异步计数器，每个异步计数器被配置为生成多比特混合计数器值的比特的子集。异步计数器由逻辑门和时钟门控电路互连。逻辑门根据以前的异步计数器产生的位产生异步逻辑值。时钟门控电路重新计时异步逻辑值以产生用于切换下一个异步计数器的同步逻辑值。混合计数器的功能比传统的异步计数器更精确，功耗比传统的同步计数器少。

28. 发明申请

US20140306740A1 TIME-INTERLEAVED MULTI-MODULUS FREQUENCY DIVIDER 有权
标题翻译：时间间隔多模式频率分频器
公开(公告)号：US20140306740A1
公开(公告)日：2014-10-16
申请号：US13479471
申请日：2012-05-24
申请人： Matthew C. Guyton
发明人： Matthew C. Guyton
IPC分类号： H03K23/58 , H03K23/66
CPC分类号： H03K23/58 , H03K23/667
摘要： Described are a multi-modulus frequency divider and event counter that are based on time-interleaved signals generated from a received signal. For the frequency divider, each time-interleaved clock signal generated from a received clock signal is provided to a bit counter and the output signal from each bit counter is provided to a multiplexer. A multiplexer selection module controls over time which one of the output signals from the bit counters is presented at the output of the multiplexer. The transition frequency of the bits in the time-interleaved clock signals allows various circuit components such as the bit counters to be implemented as CMOS components. Thus the frequency divider is more power-efficient than conventional frequency divider circuits operating at high clock frequencies.
摘要翻译：描述了基于从接收信号产生的时间交织信号的多模式分频器和事件计数器。对于分频器，从接收的时钟信号产生的每个时间交织的时钟信号被提供给位计数器，并且来自每个位计数器的输出信号被提供给多路复用器。多路复用器选择模块控制来自位计数器的输出信号中的哪一个在时间上在多路复用器的输出处呈现。时间交织的时钟信号中的位的转换频率允许诸如位计数器之类的各种电路部件被实现为CMOS部件。因此，分频器比在高时钟频率下工作的常规分频器电路更省电。

29. 发明授权

US08847637B1 Time-interleaved multi-modulus frequency divider 有权
标题翻译：时间交错多模分频器
公开(公告)号：US08847637B1
公开(公告)日：2014-09-30
申请号：US13479471
申请日：2012-05-24
申请人： Matthew C. Guyton
发明人： Matthew C. Guyton
IPC分类号： H03K21/00 , H03K23/00 , H03K25/00 , H03K23/66 , H03K23/58
CPC分类号： H03K23/58 , H03K23/667
摘要： Described are a multi-modulus frequency divider and event counter that are based on time-interleaved signals generated from a received signal. For the frequency divider, each time-interleaved clock signal generated from a received clock signal is provided to a bit counter and the output signal from each bit counter is provided to a multiplexer. A multiplexer selection module controls over time which one of the output signals from the bit counters is presented at the output of the multiplexer. The transition frequency of the bits in the time-interleaved clock signals allows various circuit components such as the bit counters to be implemented as CMOS components. Thus the frequency divider is more power-efficient than conventional frequency divider circuits operating at high clock frequencies.
摘要翻译：描述了基于从接收信号产生的时间交织信号的多模式分频器和事件计数器。对于分频器，从接收的时钟信号产生的每个时间交织的时钟信号被提供给位计数器，并且来自每个位计数器的输出信号被提供给多路复用器。多路复用器选择模块控制来自位计数器的输出信号中的哪一个在时间上在多路复用器的输出处呈现。时间交织的时钟信号中的位的转换频率允许诸如位计数器之类的各种电路部件被实现为CMOS部件。因此，分频器比在高时钟频率下工作的常规分频器电路更省电。

30. 发明授权

US5874949A Horizontal synchronizing signal frequency measuring instrument for multi-synchronism type display unit 失效
标题翻译：水平同步信号频率测量仪用于多同步型显示单元
公开(公告)号：US5874949A
公开(公告)日：1999-02-23
申请号：US839950
申请日：1997-04-24
申请人： Shinya Furukawa
发明人： Shinya Furukawa
IPC分类号： G04F10/04 , G09G1/00 , G09G1/16 , G09G5/00 , H03K23/58 , H03K23/66 , H04N3/27 , H04N5/04 , H04N17/04
CPC分类号： G09G1/16 , H04N17/04
摘要： The invention provides a horizontal synchronizing signal frequency measuring instrument which can measure a horizontal synchronizing signal frequency with a higher degree of accuracy. The horizontal synchronizing signal frequency measuring instrument includes a first counter for counting a reference clock signal, a second counter of the preset type for counting a horizontal synchronizing signal, and a control section operable to detect an edge of the vertical synchronizing signal, set a first preset value to the second counter, detect that a count value of pulses by the second counter reaches a first preset value, renders a count control signal active, reset and start the first and second counters, detect that the count value by the second counter reaches the second preset value, render the count control signal inactive and calculate a frequency of the horizontal synchronizing signal from the count value of the first counter, the second preset value and a frequency of the reference clock signal. The first counter counts the reference clock signal within a counting enabled period which is controlled by the count control signal.
摘要翻译：本发明提供一种水平同步信号频率测量仪器，可以以更高的精度测量水平同步信号频率。水平同步信号频率测量仪包括用于对参考时钟信号进行计数的第一计数器，用于计数水平同步信号的预置类型的第二计数器，以及用于检测垂直同步信号的边沿的控制部分，检测到第二计数器的脉冲计数值达到第一预设值，使计数控制信号有效，复位并启动第一和第二计数器，检测第二计数器到达的计数值第二预设值使计数控制信号无效，并根据第一计数器的计数值，第二预设值和参考时钟信号的频率计算水平同步信号的频率。第一计数器在由计数控制信号控制的计数使能周期内对参考时钟信号进行计数。

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