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21. 发明授权

US5450340A Implementation techniques of self-checking arithmetic operators and data paths based on double-rail and parity codes 失效
标题翻译：基于双轨和奇偶码的自检算术运算符和数据路径的实现技术
公开(公告)号：US5450340A
公开(公告)日：1995-09-12
申请号：US167822
申请日：1993-12-17
申请人： Michael Nicolaidis
发明人： Michael Nicolaidis
IPC分类号： G06F7/00 , G06F11/08 , G06F11/10 , G06F7/49
CPC分类号： G06F11/085 , G06F11/10 , G06F7/00
摘要： A data processing system wherein data are parity encoded for failure checking includes a logic operator generating predetermined signals responsive to input signals via first signal paths including results and carry signals, and a complement generator for generating complements of the predetermined signals responsive to the input signals received through second signal paths which are distinct from the first signal paths. In addition, the data processing system includes a double-rail checker receiving the predetermined signals from the logic operator and the complements from the generating means and for checking the logic operator responsive to the predetermined signals and the compliments and producing an output bit. The data processing system also includes a parity predictor for predicting and generating a parity bit of the results of the logic operator responsive to the output bit of the double-rail checker.
摘要翻译： PCT No.PCT / GR93 / 00007 Sec。 371日期：1993年12月17日 102（e）日期1993年12月17日PCT 1993年4月14日PCT PCT。公开号WO93 / 21576 日期：1993年10月28日。数据处理系统，其中用于故障检查的奇偶校验编码的数据处理系统包括逻辑运算符，其通过包括结果和进位信号的第一信号路径响应于输入信号产生预定信号，以及补码发生器，用于产生预定响应于通过与第一信号路径不同的第二信号路径接收的输入信号的信号。此外，数据处理系统包括双轨检查器，其接收来自逻辑运算器的预定信号和来自生成装置的补码，以及响应于预定信号和补码并产生输出位来检查逻辑运算器。数据处理系统还包括奇偶校验预测器，用于响应于双轨检查器的输出位，预测并产生逻辑运算器的结果的奇偶校验位。

22. 发明授权

US5017817A Basic circuitry particularly for construction of multivalued logic systems 失效
标题翻译：特别用于构建多值逻辑系统的基本电路
公开(公告)号：US5017817A
公开(公告)日：1991-05-21
申请号：US297034
申请日：1989-01-13
申请人： Takeshi Yamakawa
发明人： Takeshi Yamakawa
IPC分类号： G05F3/26 , G06F7/49 , G06F7/544 , H03K17/30 , H03K17/687 , H03K17/693 , H03K19/08 , H03K19/094 , H03K19/21 , H03M5/20
CPC分类号： G06F7/49 , G05F3/262 , G06F7/544 , H03K17/302 , H03K17/687 , H03K17/693 , H03K19/0813 , H03K19/09425 , H03K19/215 , H03M5/20
摘要： Disclosed are basic circuits operable in a current mode in multivalued logic circuit systems, analog circuit systems and the like. Examples of the basic circuits are a successor, quantizer, adder, subtractor, divider, multiplier, decoder, literal circuit, equivalence circuit, bilateral T-gate, complement literal circuit and h operator circuit. These basic circuits are realized by using floating threshold switching circuits, floating window switching circuits, threshold SPDT switching circuits, and the like.

23. 发明授权

US4803649A Modulo-2-adder for the logic-linking of three input signals 失效
标题翻译：用于三个输入信号的逻辑链接的模2加法器
公开(公告)号：US4803649A
公开(公告)日：1989-02-07
申请号：US26736
申请日：1987-03-17
申请人： Heinz-Peter Holzapfel , Karlheinrich Horninger
发明人： Heinz-Peter Holzapfel , Karlheinrich Horninger
IPC分类号： G06F7/49 , G06F7/50 , G06F7/501 , H03K19/21
CPC分类号： G06F7/5016 , H03K19/215
摘要： Three-value modulo-2-adders consist of four circuit components (SC1, SC2, SC3, SC4) and an analysis circuit (AW). The first circuit component (SC1) generates an intermediate signal corresponding to the first binary value ("1") when two of the input signals (A, B, C) each assume the other binary value ("0"). The second circuit component (SC2) generates an intermediate signal (ZS2) corresponding to the other binary value when two input signals each assume the first binary value. The intermediate value emitted from the output of the third circuit component (SC3) is binary "0" when all three input signals assume the binary value "1". The fourth circuit component (SC4) emits the binary value "1" when all the input signals have the binary value "0". The analysis circuit (AW1) switches through the first or second intermediate signal to the output when the third intermediate signal has the value binary "1" and the fourth intermediate signal has the value binary "0", otherwise the third or fourth intermediate signal is switched through in inverted form to the output.
摘要翻译：三值模2加法器由四个电路组件（SC1，SC2，SC3，SC4）和分析电路（AW）组成。当两个输入信号（A，B，C）各自承担另一个二进制值（“0”）时，第一电路部件（SC1）产生对应于第一二进制值（“1”）的中间信号。当两个输入信号各自承担第一二进制值时，第二电路部件（SC2）产生对应于另一个二进制值的中间信号（ZS2）。当所有三个输入信号都采用二进制值“1”时，从第三电路部件（SC3）的输出发射的中间值是二进制“0”。当所有输入信号具有二进制值“0”时，第四电路部件（SC4）发出二进制值“1”。当第三中间信号具有二进制值“1”且第四中间信号具有值二进制“0”时，分析电路（AW1）将第一或第二中间信号切换到输出，否则第三或第四中间信号为以倒置形式切换到输出。

24. 发明授权

US4722069A Nonrestoring divider 失效
标题翻译：非恢复分频器
公开(公告)号：US4722069A
公开(公告)日：1988-01-26
申请号：US719014
申请日：1985-04-02
申请人： Masayuki Ikeda
发明人： Masayuki Ikeda
IPC分类号： G06F7/49 , G06F7/52 , G06F7/535
CPC分类号： G06F7/535 , G06F7/49 , G06F7/5375
摘要： A divider apparatus includes a divisor register for storing a divisor, a partial remainder register for storing a dividend or a partial remainder, a predictor for predicting a partial quotient, a multiplier for multiplying the content of the divisor register, and a first adder for subtracting the output of the multiplier from the content of the partial remainder register and for calculating the partial remainder. The divider apparatus further includes a second adder for determining the difference between the upper digits of the multiplier and the upper digits of the partial remainder register, a first predictor for predicting the partial quotient from the output of the first adder and the upper digits of the divisor register, a second predictor for predicting the partial quotient in the third cycle from a corrected output of the second adder and the digits of the divisor register, a carry predictor for determining the carry to be propagated to the second adder from remaining digits of the multiplier and remaining digits of the partial remainder register, and a selector for selecting one of outputs of the first predicting circuit and the second predictor in dependence upon the output of the carry predictor.
摘要翻译：分频器装置包括用于存储除数的除数寄存器，用于存储除数或部分余数的部分余数寄存器，用于预测部分商的预测器，用于乘除除数寄存器的内容的乘法器和用于减去除法器的第一加法器从部分余数寄存器的内容中输出乘法器并计算部分余数。分频装置还包括第二加法器，用于确定乘法器的高位数与部分余数寄存器的高位数之间的差;第一预测器，用于根据第一加法器的输出预测部分商和第除数寄存器，用于从第二加法器的校正输出和除数寄存器的数字预测第三周期中的部分商的第二预测器，用于从第二加法器的剩余数字确定要传播到第二加法器的进位的进位预测器乘法器和剩余数字的部分余数寄存器，以及选择器，用于根据进位预测器的输出来选择第一预测电路和第二预测器的输出之一。

25. 发明授权

US4628472A Binary multiplier using ternary code 失效
标题翻译：使用三进制码的二进制乘法器
公开(公告)号：US4628472A
公开(公告)日：1986-12-09
申请号：US553488
申请日：1983-11-18
申请人： Thierry Fensch
发明人： Thierry Fensch
IPC分类号： G06F7/533 , G06F7/48 , G06F7/49 , G06F7/506 , G06F7/508 , G06F7/53 , G06F7/52
CPC分类号： G06F7/4824
摘要： The invention provides a high-speed binary multiplier.The binary digits x.sub.i of the multiplicand X and y.sub.j of the multiplier Y (in two complement form) are converted by respective coders into coefficients a.sub.i and b.sub.j such thatX=a.sub.m-1 2.sup.m-1 + . . . a.sub.1 2.sup.1 +a.sub.oY=b.sub.n-1 2.sup.n-1 + . . . b.sub.1 2.sup.1 +b.sub.owhere a.sub.i and b.sub.j can only assume three values 0,1 or -1 and where two consecutive coefficients a.sub.i and a.sub.i-1 and b.sub.j or b.sub.j-1 cannot both be non zero. a.sub.i and b.sub.j are each represented by a pair of binary logic signals (r.sub.i,u.sub.i) or (s.sub.j,v.sub.j). The signals (s.sub.j,v.sub.j) serve for controlling a routing circuit which further receives as signals to be routed the signals (r.sub.i,u.sub.i) for directing these signals, depending on the values of coefficients b.sub.j, to the appropriate inputs of an adder stage operating without carry-over propagation. The outputs of this adder are reconverted into binary form by a decoder.
摘要翻译：本发明提供了一种高速二进制乘法器。乘法器X的二进制数xi和乘法器Y的二进制（两种补码形式）由相应的编码器转换为系数ai和bj，使得X = am-12m-1 +。。。 a121 + ao Y = bn-12n-1 +。。。 b121 + bo其中ai和bj只能假设三个值0,1或-1，其中两个连续系数ai和ai-1以及bj或bj-1都不能都为非零。 ai和bj分别由一对二进制逻辑信号（ri，ui）或（sj，vj）表示。信号（sj，vj）用于控制路由电路，该路由电路进一步作为要路由的信号接收信号（ri，ui），用于根据系数bj的值将这些信号引导到加法器级操作的适当输入端无遗留传播。该加法器的输出由解码器转换成二进制形式。

26. 发明授权

US4390962A Latched multivalued full adder 失效
标题翻译：锁存多值全加器
公开(公告)号：US4390962A
公开(公告)日：1983-06-28
申请号：US133836
申请日：1980-03-25
申请人： Karl W. Current
发明人： Karl W. Current
IPC分类号： G06F7/49
CPC分类号： G06F7/49
摘要： A synchronous latched multivalued full adder for processing a first input current having any one of a plurality of multivalues, including a quantizer for receiving current, for generating a sum logical output current and a carry logical output current being a quantization of the received current, and for regenerating the received current from the sum and carry logical output current as an output, an input line for directing the input current to the quantizer as the received current, a feedback line for directing the regenerated current back to the quantizer as the received current, and a clock controlled switching device for coupling the input line to the quantizer while decoupling the feedback line from the quantizer during a setup mode and for decoupling the input line from the quantizer while coupling the feedback line to the quantizer during a hold mode.
摘要翻译：一种同步锁存多值全加器，用于处理具有多个多值中的任何一个的第一输入电流，包括用于接收电流的量化器，用于产生和逻辑输出电流和作为接收电流的量化的进位逻辑输出电流;以及用于从所述和再生所接收的电流并输入作为输出的逻辑输出电流;用于将所述输入电流指向所述量化器作为接收电流的输入线;用于将所述再生电流引导回所述量化器作为接收电流的反馈线，以及时钟控制的开关装置，用于在输入线路与量化器之间耦合，同时在建立模式期间将反馈线与量化器解耦，并且在保持模式期间将反馈线与量化器耦合到量化器。

27. 发明授权

US3222506A Variable radix adder and subtractor 失效
标题翻译：可变基数加法器和减法器
公开(公告)号：US3222506A
公开(公告)日：1965-12-07
申请号：US15283161
申请日：1961-11-16
申请人： IBM
发明人： MEADE ROBERT M
IPC分类号： G06F7/49
CPC分类号： G06F7/49

28. 发明授权

US3159740A Universal radix adder 失效
标题翻译：通用加法器
公开(公告)号：US3159740A
公开(公告)日：1964-12-01
申请号：US16401762
申请日：1962-01-03
申请人： IBM
发明人： BROCE THOMAS C
IPC分类号： G06F7/49
CPC分类号： G06F7/49

29. 发明授权

US12045582B2 Multi-dimensional FFT computation pipelined hardware architecture using Radix-3 and Radix-2 有权
公开(公告)号：US12045582B2
公开(公告)日：2024-07-23
申请号：US17351699
申请日：2021-06-18
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Pankaj Gupta , Karthik Subburaj , Sujaata Ramalingam , Karthik Ramasubramanian , Indu Prathapan
IPC分类号： G06F7/49 , G06F7/501 , G06F17/14
CPC分类号： G06F7/49 , G06F7/501 , G06F17/142
摘要： A Radix-3 butterfly circuit includes a first FIFO input configured to couple to a first FIFO. The circuit includes a first adder and first subtractor coupled to the first FIFO input, and a second FIFO input configured to couple to a second FIFO. The circuit includes a second adder and second subtractor coupled to the second FIFO input, and an input terminal coupled to the first adder and first subtractor. The circuit includes a first scaler coupled to the second adder and a first multiplexer, and a second scaler coupled to a third adder and second multiplexer. The circuit includes a third scaler coupled to a third subtractor and third multiplexer. An output of the first multiplexer is coupled to a complex multiplier. An output of the second multiplexer is coupled to a second FIFO output. An output of the third multiplexer is coupled to a first FIFO output.

30. 发明公开

US20240184523A1 METHODS AND APPARATUS TO PERFORM MIXED RADIX FAST FOURIER TRANSFORM (FFT) CALCULATIONS ON GRAPHICS PROCESSING UNITS (GPUs) 审中-公开
公开(公告)号：US20240184523A1
公开(公告)日：2024-06-06
申请号：US18553185
申请日：2021-06-24
申请人： Intel Corporation
发明人： Bin Wang , Bo Peng , Xiaoyun Wang
IPC分类号： G06F7/49
CPC分类号： G06F7/49
摘要： Methods, apparatus, systems, and articles of manufacture are disclosed for mixed radix fast Fourier transform (FFT) calculations of graphics processing units (GPUs). An example apparatus disclosed herein includes at least one memory, machine readable instructions in the apparatus, and at least one processor circuitry to execute the machine readable instructions to at least factorize input data to identify one or more radix-r blocks for the parallel mixed radix calculation, perform at least one of a decimal-to-base or a base-to-base conversion of the input data prior to a bit reverse routine, the bit reverse routine to yield an output data set, cause a lookup table to be loaded into a memory structure based on a lookup table length, the lookup table populated with the output data set, and perform the parallel mixed radix calculation of the one or more radix-r blocks using the lookup table loaded into the memory structure.

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