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1. 发明授权

US4803649A Modulo-2-adder for the logic-linking of three input signals 失效
标题翻译：用于三个输入信号的逻辑链接的模2加法器
公开(公告)号：US4803649A
公开(公告)日：1989-02-07
申请号：US26736
申请日：1987-03-17
申请人： Heinz-Peter Holzapfel , Karlheinrich Horninger
发明人： Heinz-Peter Holzapfel , Karlheinrich Horninger
IPC分类号： G06F7/49 , G06F7/50 , G06F7/501 , H03K19/21
CPC分类号： G06F7/5016 , H03K19/215
摘要： Three-value modulo-2-adders consist of four circuit components (SC1, SC2, SC3, SC4) and an analysis circuit (AW). The first circuit component (SC1) generates an intermediate signal corresponding to the first binary value ("1") when two of the input signals (A, B, C) each assume the other binary value ("0"). The second circuit component (SC2) generates an intermediate signal (ZS2) corresponding to the other binary value when two input signals each assume the first binary value. The intermediate value emitted from the output of the third circuit component (SC3) is binary "0" when all three input signals assume the binary value "1". The fourth circuit component (SC4) emits the binary value "1" when all the input signals have the binary value "0". The analysis circuit (AW1) switches through the first or second intermediate signal to the output when the third intermediate signal has the value binary "1" and the fourth intermediate signal has the value binary "0", otherwise the third or fourth intermediate signal is switched through in inverted form to the output.
摘要翻译：三值模2加法器由四个电路组件（SC1，SC2，SC3，SC4）和分析电路（AW）组成。当两个输入信号（A，B，C）各自承担另一个二进制值（“0”）时，第一电路部件（SC1）产生对应于第一二进制值（“1”）的中间信号。当两个输入信号各自承担第一二进制值时，第二电路部件（SC2）产生对应于另一个二进制值的中间信号（ZS2）。当所有三个输入信号都采用二进制值“1”时，从第三电路部件（SC3）的输出发射的中间值是二进制“0”。当所有输入信号具有二进制值“0”时，第四电路部件（SC4）发出二进制值“1”。当第三中间信号具有二进制值“1”且第四中间信号具有值二进制“0”时，分析电路（AW1）将第一或第二中间信号切换到输出，否则第三或第四中间信号为以倒置形式切换到输出。

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