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21. 发明授权

US10193586B1 Direct conversion receiver with correction for second order distortion in RF mixer 有权
公开(公告)号：US10193586B1
公开(公告)日：2019-01-29
申请号：US15859443
申请日：2017-12-30
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Jagannathan Venkataraman , Eeshan Miglani
IPC分类号： H04B1/10 , H04B1/16 , H03D7/12 , H03F3/45 , H03K3/017 , H03M1/12 , H03F3/19
摘要： A direct conversion radio frequency receiver comprising: a clock generator to provide a first clock signal and a second clock signal; a first node; a second node; a zero-intermediate frequency (zero-IF) mixer coupled to the first and second nodes, clocked by the first and second clock signals, and comprising a first transimpedance amplifier and a second transimpedance amplifier to provide a direct-conversion voltage; a current injector, coupled to the first and second nodes, configurable to inject into the first and second nodes a common mode current or a differential mode current; and a controller, coupled to the zero-IF mixer and the current injector, to adjust at least one of the first and second transimpedance amplifiers based on the direct-conversion voltage when the current injector is to inject the common mode current.

22. 发明授权

US10171034B2 Phase-rotated harmonic-rejection mixer apparatus 有权
公开(公告)号：US10171034B2
公开(公告)日：2019-01-01
申请号：US15462923
申请日：2017-03-20
申请人： MEDIATEK INC.
发明人： Chien-Wei Tseng , Ian Tseng , Ming-Da Tsai , Yangjian Chen , Chien-Cheng Lin
IPC分类号： H03D7/12 , H03D7/16
摘要： A harmonic-rejection mixer apparatus includes a mixing circuit and a combining circuit. The mixing circuit receives mixes an input signal and a first local oscillator (LO) signal to generate a first output signal, and mixes the same input signal and a second LO signal to generate a second output signal, wherein the first LO signal and the second LO signal have a same frequency but different phases. The combining circuit combines the first output signal and the second output signal, wherein harmonic rejection is at least achieved by combination of the first output signal and the second output signal.

23. 发明授权

US10122321B2 Frequency conversion device with dual local oscillators and satellite payload comprising such a device 有权
公开(公告)号：US10122321B2
公开(公告)日：2018-11-06
申请号：US15676647
申请日：2017-08-14
申请人： THALES
发明人： Patrice Ulian , Juliette Vallon-Altairac , Jean-Brice Juraver
IPC分类号： H03D7/16 , B64G1/42 , H03D7/12 , H04B7/185
摘要： A frequency conversion device, intended for installation on board a satellite, comprises an active assembly comprising at least one first radiofrequency processing chain comprising a first mixer, a first local oscillator operating at a first frequency and linked to the first mixer, at least one second radiofrequency processing chain comprising a second mixer, and a second local oscillator operating at a second frequency and linked to the second mixer and a current or voltage converter for supplying power to the active assembly.

24. 发明授权

US10094705B2 Apparatus and method for processing output signal of analog-to-digital converter 有权
公开(公告)号：US10094705B2
公开(公告)日：2018-10-09
申请号：US15540494
申请日：2015-12-29
申请人： SOLiD, INC.
发明人： Hyoungho Kim , Kwangnam Seo , Doyoon Kim
IPC分类号： H03M1/66 , G01G23/10 , G01G3/14 , G06F3/05 , H03D7/14 , H03D7/12 , H04L27/26 , H03M1/74 , H04L25/03 , H04B1/04
摘要： According to an aspect of the inventive concept, there is provided an apparatus for processing an output signal of an analog-digital converter, includes: a first frequency conversion unit for converting a frequency of the output signal of the analog-digital converter so that a band where spurious components exist moves to a band where direct current components exist in the output signal of the analog-digital converter; a spurious component blocking unit for eliminating, from an output signal of the first frequency conversion unit, spurious components which have moved to the band where direct current components exist; and a second frequency conversion unit for restoring a frequency of an output signal of the spurious component blocking unit to the original frequency of the output signal of the analog-digital converter.

25. 发明授权

US10003302B2 Modified tunneling field effect transistors and fabrication methods 有权
公开(公告)号：US10003302B2
公开(公告)日：2018-06-19
申请号：US15496049
申请日：2017-04-25
申请人： GLOBALFOUNDRIES INC.
发明人： Yanxiang Liu , Min-hwa Chi
IPC分类号： H01L29/739 , H03C3/14 , H01L29/78 , H01L29/08 , H01L27/088 , H03D7/12 , H01L29/66 , H01L29/06
CPC分类号： H03C3/145 , H01L27/088 , H01L29/0688 , H01L29/0847 , H01L29/161 , H01L29/66356 , H01L29/66568 , H01L29/66977 , H01L29/7391 , H01L29/78 , H01L29/7848 , H03C3/02 , H03C3/245 , H03D7/125
摘要： Tunneling field effect transistors and fabrication methods thereof are provided, which include: an integrated circuit device which includes a circuit input configured to receive an input voltage and a circuit output configured to deliver an output current. The integrated circuit also includes a circuit element having at least one tunneling field effect transistor (TFET). The circuit element connects the circuit input to the circuit output and is characterized by a V-shaped current-voltage diagram. The V-shaped current-voltage diagram describes the relationship between the input voltage of the circuit input and the output current of the circuit output.

26. 发明授权

US09705522B1 High speed low power digital to analog upconverter 有权
公开(公告)号：US09705522B1
公开(公告)日：2017-07-11
申请号：US15344328
申请日：2016-11-04
申请人： The Boeing Company
发明人： Vincent T. Ng , Sharon S. Ng , Shihchang Wu , Pedro A. Martinez , Nhung T. Araki
IPC分类号： H03M1/66 , H03M1/10 , H03D7/12
CPC分类号： H03M1/66 , H03D7/125 , H03M1/662 , H03M1/808
摘要： Systems and methods according to one or more embodiments are provided for a high speed digital to analog upconverter that provides for converting a plurality of parallel digital data bits to an analog output signal. In one example, a system includes a decoder circuit configured to receive a plurality of decoder input data bits and provide a plurality of decoded parallel digital data bits. The system also includes a mixer circuit configured to combine each of the decoded parallel digital data bits with a conversion clock signal to provide frequency shifted digital data bits, wherein the frequency shifted digital data bits are time misaligned with each other. The system also includes a synchronizer circuit configured to time align the frequency shifted digital data bits. The system further includes a switching network configured to generate an analog output signal in response to the time aligned frequency shifted digital data bits.

27. 发明授权

US09529372B2 Fault-rejecting mixer and applications 有权
标题翻译：故障排除混合器和应用
公开(公告)号：US09529372B2
公开(公告)日：2016-12-27
申请号：US13669807
申请日：2012-11-06
申请人： Volterra Semiconductor Corporation
发明人： Patrice Lethellier
IPC分类号： H03K3/00 , G05F1/46 , H03D7/12 , H03D7/16
CPC分类号： G05F1/46 , H03D7/125 , H03D7/165 , H03D2200/0074
摘要： Mixers are described which allow for information sharing in redundant systems, while providing sufficient isolation between redundant system components to enable fault-tolerant operation.
摘要翻译：描述了混合器，其允许冗余系统中的信息共享，同时在冗余系统组件之间提供足够的隔离以实现容错操作。

28. 发明授权

US09478204B2 Sub-harmonic mixer 有权
标题翻译：次谐波混频器
公开(公告)号：US09478204B2
公开(公告)日：2016-10-25
申请号：US14425921
申请日：2012-09-04
申请人： Mingquan Bao
发明人： Mingquan Bao
IPC分类号： H04M1/00 , G10H1/32 , H03D7/02 , H03D7/12
CPC分类号： G10H1/32 , H03D7/02 , H03D7/12
摘要： A sub-harmonic mixer comprising first and second input ports, and an output port, and arranged to output products of signals applied at the input ports. The sub-harmonic mixer comprises a first stage a second stage arranged in series with each other, with the input ports of the sub-harmonic mixer being input ports of the first stage, and the output port of the sub-harmonic mixer being an output port of the second stage. An output port of the first stage is connected to an input port of the second stage. The first stage is arranged to generate a fundamental product and a first third order intermodulation distortion product in-phase with each other. The second stage is arranged to generate a second third order intermodulation distortion product in anti-phase to the fundamental product generated by the second stage.
摘要翻译：包括第一和第二输入端口的子谐波混合器和输出端口，并被布置成输出在输入端口处施加的信号的产物。子谐波混频器包括第一级，第二级彼此串联布置，子谐波混合器的输入端口是第一级的输入端口，并且子谐波混频器的输出端口是输出端第二阶段港第一级的输出端口连接到第二级的输入端口。第一级被设置为产生彼此同相的基本乘积和第一三阶互调失真乘积。第二级被布置为产生与第二级产生的基本产品相反的第二级三阶互调失真产物。

29. 发明授权

US09397382B2 Logarithmic amplifier with universal demodulation capabilities 有权
标题翻译：具有通用解调功能的对数放大器
公开(公告)号：US09397382B2
公开(公告)日：2016-07-19
申请号：US14214437
申请日：2014-03-14
申请人： DockOn AG
发明人： Forrest Brown , Patrick Rada , Alexandre Dupuy
IPC分类号： H03D11/08 , H01P5/19 , H03D1/08 , H03D11/04 , H01Q7/00 , H01Q21/00 , H03D1/18 , H03D7/02 , H03D7/12 , H03D7/16 , H03F3/191 , H03F1/08 , H03F3/04
CPC分类号： H01P5/19 , H01Q7/00 , H01Q21/0075 , H03D1/08 , H03D1/18 , H03D7/02 , H03D7/12 , H03D7/165 , H03D7/166 , H03D11/04 , H03D11/08 , H03D2200/0043 , H03D2200/0098 , H03F1/08 , H03F3/04 , H03F3/191 , H03F2200/165 , H03F2200/294 , H03G11/04
摘要： A logarithmic amplifier (LDA) is described that includes an amplifier configured to oscillate a modulated input signal, a feedback establishing a 180 degree phase shift between the amplifier input and the output and maintaining oscillation of the input signal, a parallel resonant circuit connected to the amplifier output causing the amplifier to resonate at or around a center frequency, and a controller connected to the amplifier input cyclically terminating oscillation of the input signal each time a pre-determined threshold of current is detected, the controller including a low pass filter configured to generate a second output signal having a repetition frequency. The LDA may be used for AM with or without a PLL and/or a superhetrodyne. The LDA may be implemented as a mixer and used for phase demodulation. The LDA may be used for phase demodulation. The LDA may be used in place of a low noise amplifier.
摘要翻译：描述了对数放大器（LDA），其包括被配置为振荡调制输入信号的放大器，在放大器输入和输出之间建立180度相移并保持输入信号的振荡的反馈，并联谐振电路放大器输出使得放大器在中心频率处或周围谐振，以及连接到放大器输入端的控制器，每当检测到电流的预定阈值时循环地终止输入信号的振荡，则控制器包括低通滤波器，产生具有重复频率的第二输出信号。 LDA可用于具有或不具有PLL和/或超临界的AM。 LDA可以实现为混频器并用于相位解调。 LDA可用于相位解调。可以使用LDA代替低噪声放大器。

30. 发明授权

US09287836B2 Method and apparatus of an input resistance of a passive mixer to broaden the input matching bandwidth of a common source-gate LNA 有权
标题翻译：无源混频器的输入电阻的方法和装置，以扩大公共源极LNA的输入匹配带宽
公开(公告)号：US09287836B2
公开(公告)日：2016-03-15
申请号：US14108312
申请日：2013-12-16
申请人： Tensorcom, Inc.
发明人： Zaw Soe
IPC分类号： H04B1/16 , H03F3/19 , H03F3/387 , H03F1/22 , H03F3/193 , H03D7/12 , H03D7/14 , H03D7/16
CPC分类号： H03F1/42 , H03D7/125 , H03D7/1441 , H03D7/1466 , H03D7/165 , H03F1/223 , H03F3/193 , H03F3/387 , H03F3/45071 , H03F3/45179 , H03F2200/108 , H03F2200/294 , H03F2200/451 , H03F2200/492 , H03F2200/72 , H03F2200/75 , H04L27/38
摘要： A cascode common source and common gate LNAs operating at 60 GHz are introduced and described. The cascode common source LNA is simulated to arrive at an optimum ratio of upper device width to the lower device width. The voltage output of the cascode common source LNA is translated into a current to feed and apply energy to the mixer stage. These input current signals apply the energy associated with the current directly into the switched capacitors in the mixer to minimize the overall power dissipation of the system. The LNA is capacitively coupled to the mixer switches in the I and Q mixers and are enabled and disabled by the clocks generated by the quadrature oscillator. These signals are then amplified by a differential amplifier to generate the sum and difference frequency spectra.
摘要翻译：引入并描述了以60GHz操作的共源共栅和公共栅极LNA。对共源共栅源LNA进行模拟，以达到上部器件宽度与较低器件宽度的最佳比例。共源共栅源LNA的电压输出转换为电流以馈送并将能量施加到混频器级。这些输入电流信号将与电流相关联的能量直接施加到混频器中的开关电容器中，以最小化系统的总功耗。 LNA电容耦合到I和Q混频器中的混频器开关，并由正交振荡器产生的时钟使能和禁止。然后，这些信号被差分放大器放大以产生和和差频谱。

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