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21. 发明申请

US20090111292A1 Surface Mount Technology Pad Layout for Docking Connector Systems 审中-公开
标题翻译：用于对接连接器系统的表面贴装技术垫布局
公开(公告)号：US20090111292A1
公开(公告)日：2009-04-30
申请号：US11931220
申请日：2007-10-31
申请人： William Louis Brodsky , Mark Kenneth Hoffmeyer
发明人： William Louis Brodsky , Mark Kenneth Hoffmeyer
IPC分类号： H01R12/06
CPC分类号： H05K1/111 , H01R12/724 , H01R13/6471 , H01R13/648 , H05K1/0219 , H05K2201/09409 , H05K2201/10189 , Y02P70/611
摘要： A pad array for a surface mount technology board includes a front row ground pad as a single pad, followed by a signal pad. The ground pads internal to the array may be arranged as pairs of pads interconnected to each other, with sandwiching signal pads on the internal portion of the array. To minimize stress on connector wafers of large scale connectors, external rows of ground pads may be enlarged by a predetermined amount in a Y-direction to minimize potential formation of stress risers, while ensuring that electrical spacing requirements to adjacent signal leads may be preserved for optimal signal integrity.
摘要翻译：用于表面贴装技术板的焊盘阵列包括作为单个焊盘的前排接地焊盘，其后是信号焊盘。阵列内部的接地焊盘可以布置为彼此互连的焊盘对，并且在阵列的内部部分上夹有信号焊盘。为了最大限度地减小大尺寸连接器的连接器晶片上的应力，外部排的接地焊盘可以在Y方向上扩大预定量，以最小化应力梯级的潜在形成，同时确保可以保持对相邻信号引线的电气间隔要求，最佳信号完整性。

22. 发明申请

US20080296056A1 Printed circuit board, production method therefor, electronic-component carrier board using printed circuit board, and production method therefor 审中-公开
标题翻译：印刷电路板，其制造方法，使用印刷电路板的电子部件载体板及其制造方法
公开(公告)号：US20080296056A1
公开(公告)日：2008-12-04
申请号：US12079055
申请日：2008-03-24
申请人： Tohru Kinoshita , Toshinobu Kanai
发明人： Tohru Kinoshita , Toshinobu Kanai
IPC分类号： H05K3/10 , H01R12/06
CPC分类号： H05K1/183 , H01L23/13 , H01L23/49816 , H01L23/49822 , H01L25/0657 , H01L2224/0554 , H01L2224/05568 , H01L2224/05573 , H01L2224/16 , H01L2224/16225 , H01L2224/16235 , H01L2225/06517 , H01L2924/00014 , H01L2924/01019 , H01L2924/01078 , H01L2924/01079 , H01L2924/15151 , H01L2924/15153 , H01L2924/1517 , H05K1/186 , H05K3/0044 , H05K3/4652 , H05K3/4697 , H05K2201/09481 , H05K2201/09845 , H05K2201/10515 , H05K2203/0228 , Y10T29/49155 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A printed wiring board has a substrate having a first surface and a second surface on both sides of the substrate. A cavity is provided on the first surface. The cavity caves in towards the second surface. Several bumps are formed in the cavity as protruding towards the first surface. An insulation layer is filled in the cavity. The bumps are isolated from one another by the insulation layer. The top of each bump that protrudes towards the first surface and a zone in the cavity and close to the top are exposed in the cavity without being covered by the insulation layer.
摘要翻译：印刷电路板具有在基板的两侧具有第一表面和第二表面的基板。在第一表面上设置空腔。腔朝向第二表面洞穴。在空腔中形成有朝向第一表面突出的几个凸起。绝缘层填充在空腔中。凸块通过绝缘层彼此隔离。每个凸块的朝向第一表面突出的顶部以及空腔中靠近顶部的区域暴露在空腔中而不被绝缘层覆盖。

23. 发明申请

US20080277153A1 System and Method for Capacitive Coupled VIA Structures in Information Handling System Circuit Boards 审中-公开
标题翻译：信息处理系统电路板中电容耦合VIA结构的系统与方法
公开(公告)号：US20080277153A1
公开(公告)日：2008-11-13
申请号：US11931698
申请日：2007-10-31
申请人： Abeye Teshome , Lan Zhang
发明人： Abeye Teshome , Lan Zhang
IPC分类号： H01R12/06
CPC分类号： H05K1/0216 , H05K1/0263 , H05K1/112 , H05K1/162 , H05K2201/0792 , H05K2201/09309 , H05K2201/10734 , Y10T29/49128 , Y10T29/49169
摘要： Power supplied to an information handling system electronic component through a circuit board has component package inductance parasitic effects compensated by configuring connections to the electronic component to have increased parasitic capacitance. For instance, power and ground vias that connect a processor to power and ground planes of the circuit board are aligned to create a desired parasitic capacitance that reduces the impact of parasitic inductance relating to signal compensation, power delivery and high speed decoupling. The desired distributed capacitance is modeled by altering the radius associated with the equivalent line charge of the power via, the distance associated with the line charges between power and ground vias, and the via barrel length.
摘要翻译：通过电路板提供给信息处理系统电子元件的功率具有通过配置与电子元件的连接以补偿寄生电容的组件封装电感寄生效应。例如，将处理器连接到电路板的电源和接地平面的电源和接地通孔被对准以产生期望的寄生电容，其减少与信号补偿，功率输送和高速解耦有关的寄生电感的影响。期望的分布电容通过改变与功率通孔的等效线电荷相关联的半径，与电源和接地通孔之间的线路电荷相关联的距离以及通孔筒长度来建模。

24. 发明授权

US06984792B2 Dielectric interposer for chip to substrate soldering 失效
标题翻译：用于芯片到基板焊接的介质插入器
公开(公告)号：US06984792B2
公开(公告)日：2006-01-10
申请号：US10427459
申请日：2003-05-01
申请人： Peter J. Brofman , Shaji Farooq , John U. Knickerbocker , Scott I. Langenthal , Sudipta K. Ray , Kathleen A. Stalter
发明人： Peter J. Brofman , Shaji Farooq , John U. Knickerbocker , Scott I. Langenthal , Sudipta K. Ray , Kathleen A. Stalter
IPC分类号： H01R12/06
CPC分类号： H05K3/3436 , H01L23/49827 , H01L2224/05568 , H01L2224/05573 , H01L2224/16 , H01L2924/00014 , H01L2924/09701 , H05K2201/10378 , H05K2201/10424 , H05K2201/10674 , H05K2203/0415 , Y02P70/613 , Y10T29/49144 , Y10T29/49149 , H01L2224/05599
摘要： A pre-thermal reflown dielectric interposer having a plurality of vias traversing through the interposer which correspond to the I/O pads on a chip and substrate. Cone shaped solder elements reside within the vias, whereby these solder elements are cone shaped prior to thermal reflow to permit a reduced force for allowing some non-planarity for joining the chip to the substrate. The interposer may comprise a polyester film, glass, alumina, polyimide, a heat curable polymer or an inorganic powder filler in an organic material. The interposer may also have an adhesive or adhesive layers disposed on the linear surfaces thereof. The present pre-thermal reflown interposer prohibits contact between the solder joints by isolating each of the joints and corresponding bonding pads, as well as preventing over compression of the solder joints by acting as a stand off.
摘要翻译：具有穿过插入件的多个通孔对应于芯片和基板上的I / O焊盘的预热退火介电插入器。锥形焊料元件驻留在通孔内，由此这些焊料元件在热回流之前是锥形的，以允许减小的力以允许用于将芯片连接到衬底的一些非平面性。中间层可以在有机材料中包含聚酯膜，玻璃，氧化铝，聚酰亚胺，热固化聚合物或无机粉末填料。插入器也可以具有设置在其线性表面上的粘合剂或粘合剂层。本发明的预热反射中介层通过隔离每个接头和相应的接合焊盘来防止焊点之间的接触，并且通过作为脱开来防止焊点过度压缩。

25. 发明授权

US06859370B1 Board to board array type connector 失效
标题翻译：板对板阵列式连接器
公开(公告)号：US06859370B1
公开(公告)日：2005-02-22
申请号：US10654044
申请日：2003-09-04
申请人： Chien-Yu Hsu , Yen-Jang Liao , Li-Sen Chen
发明人： Chien-Yu Hsu , Yen-Jang Liao , Li-Sen Chen
IPC分类号： H01R12/00 , H01R12/04 , H01R12/06 , H01R13/24 , H01R13/621 , H05K7/10 , H05K7/12
CPC分类号： H01R12/52 , H01R13/2414 , H01R13/621 , H05K7/1061
摘要： A board to board array type connector comprising an array type connector, an upper supporting cover, a lower supporting cover, a screw with a bolt and a screw nut; during application, the upper supporting cover is on the top of the upper PCB, the upper pressing area/point presses down on the top of the upper PCB, the lower supporting cover is on the bottom of the lower PCB, the lower pressing area/point presses up on the bottom of the lower PCB; the screw with bolt passes through all the through holes and is fastened with the screw nut on the end to assemble the whole set, the stress is distributed equilibrium to the upper and lower pressing area/point, the pressure is evenly over all the connection pins of the array type connector for better electrical conductivity.
摘要翻译：一种板对板阵列型连接器，包括阵列型连接器，上支撑盖，下支撑盖，具有螺栓的螺钉和螺母; 在施工期间，上支撑盖位于上PCB的顶部，上压板区域/点压在上PCB的顶部，下支撑盖位于下PCB板的底部，下压区/ 点压在下PCB的底部; 带螺栓的螺丝穿过所有通孔，并用螺母紧固在一端，组装整套，应力分布平衡到上下压区/点，压力均匀地覆盖所有连接销的阵列型连接器，以获得更好的导电性。

26. 发明授权

US5515604A Methods for making high-density/long-via laminated connectors 失效
标题翻译：制造高密度/长通孔层压连接器的方法
公开(公告)号：US5515604A
公开(公告)日：1996-05-14
申请号：US134374
申请日：1993-10-12
申请人： David A. Horine , David G. Love
发明人： David A. Horine , David G. Love
IPC分类号： H01R12/04 , H01R11/01 , H01R12/06 , H05K3/36
CPC分类号： H01R12/52 , H01R12/57 , Y10T29/49126 , Y10T29/49155 , Y10T29/49224
摘要： A high-density laminated connector having a plurality of rigid dielectric layers laminated together is described. The rigid construction of the connector permits precise dimensions of the connector and, thus, accurate attachment of adjacent interconnect substrates. The dielectric layers include traces which have contact pads or bumps formed at the surfaces of the connector for connection to the traces of one or more adjacent interconnect substrates. The contact pads may comprise soft gold, solder, or various elastomeric materials. The use of soft gold contacts enables the connector to be easily removed from an adjacent interconnect substrate. In other embodiments, the rigid dielectric layers may comprise recesses where the contact pads are placed. This ensures physical alignment of the interconnect substrate and the connector, so that dimensional integrity is maintained when pressure is applied to the connector. The traces within the connector can be of a varied width, pitch, and direction. Thus, right-angle interconnections can be made. Cross-traces can be placed on each individual layer of dielectric and vias made through the dielectric layers to interconnect traces. The trace width can be economically and accurately narrowed to produce high aspect ratios and thus provide high signal density.
摘要翻译：描述了具有层叠在一起的多个刚性介电层的高密度层叠连接器。连接器的刚性结构允许连接器的精确尺寸，从而准确地附接相邻的互连基板。电介质层包括具有形成在连接器表面处的接触焊盘或凸点的迹线，用于连接到一个或多个相邻互连基板的迹线。接触垫可以包括软金，焊料或各种弹性体材料。使用软金触点使连接器能够容易地从相邻的互连基板移除。在其他实施例中，刚性电介质层可以包括其中放置接触垫的凹部。这确保互连基板和连接器的物理对准，使得当对连接器施加压力时维持尺寸完整性。连接器内的迹线可以具有不同的宽度，间距和方向。因此，可以进行直角互连。交叉迹线可以放置在通过介电层制成的介电层和通孔的每个单独层上以互连迹线。迹线宽度可以经济地和精确地缩小以产生高纵横比，从而提供高信号密度。

27. 发明申请

US20110132650A1 High-Speed Ceramic Modules with Hybrid Referencing Scheme for Improved Performance and Reduced Cost 有权
标题翻译：具有混合参考方案的高速陶瓷模块，用于提高性能和降低成本
公开(公告)号：US20110132650A1
公开(公告)日：2011-06-09
申请号：US12630993
申请日：2009-12-04
申请人： Wiren D. Becker , Jinwoo Choi , Tingdong Zhou
发明人： Wiren D. Becker , Jinwoo Choi , Tingdong Zhou
IPC分类号： H01R12/06 , G06F17/50 , H05K3/10
CPC分类号： H01L21/76838 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L23/66 , H01L2924/0002 , H01L2924/09701 , H01L2924/19051 , H01L2924/3011 , H05K1/0253 , H05K3/4629 , H05K2201/09309 , H05K2201/09681 , H05K2201/09727 , H05K2201/10674 , H01L2924/00
摘要： A multi-layered ceramic package comprises: a signal layer with identified chip/device area(s)/site(s) that require a supply of power; and a voltage power (Vdd) layer and a ground (Gnd) layer disposed on opposite sides directly above or below (adjacent to) the signal layer and providing a first reference mesh plane and a second reference mesh plane configured utilizing a hybrid mesh scheme. The hybrid mesh scheme comprises different mesh configurations from among: a full dense mesh in a first area directly above or below the identified chip/device area(s); a half dense mesh in a second area that is above or below the edge(s) of the chip/device area; and a wider mesh pitch in all other areas, and the Vdd traces are aligned to run parallel and adjacent to signal lines in those other areas. Wider traces are provided within the mesh areas that run parallel and adjacent to signal lines.
摘要翻译：多层陶瓷封装包括：具有识别的芯片/设备区域/需要供电电源的位置的信号层; 以及设置在信号层的正上方或下方（相邻）相对侧的电压功率（Vdd）层和接地（Gnd）层，并且提供使用混合网格方案配置的第一参考网格平面和第二参考网格平面。混合网格方案包括以下不同的网格配置：在识别的芯片/设备区域之上或之下的第一区域中的全密度网格; 在芯片/设备区域的边缘的上方或下方的第二区域中的半密度网格; 并且在所有其它区域中具有更宽的网格间距，并且Vdd迹线对准以在其他区域中与信号线平行并相邻地延伸。在与信号线平行且相邻的网格区域内提供更宽的轨迹。

28. 发明申请

US20110079420A1 Ceramic multilayer and method for manufacturing the same 审中-公开
标题翻译：陶瓷多层及其制造方法
公开(公告)号：US20110079420A1
公开(公告)日：2011-04-07
申请号：US12591735
申请日：2009-11-30
申请人： Myung Whun CHANG , Dae Hyeong LEE , Ki Pyo HONG , Jin Waun KIM
发明人： Myung Whun CHANG , Dae Hyeong LEE , Ki Pyo HONG , Jin Waun KIM
IPC分类号： H01R12/06 , H01R43/00
CPC分类号： H05K3/4061 , B32B18/00 , C04B35/645 , C04B2237/343 , C04B2237/348 , C04B2237/62 , C04B2237/68 , H05K3/4629 , H05K2201/0352 , H05K2201/096 , Y10T29/49117 , Y10T29/49204
摘要： The present invention provides a multi-layered ceramic substrate including a first insulating sheet having a first via contact; and a second insulating sheet joined to the first insulating sheet, wherein the second insulating sheet has a second via contact aligned with the first via contact up and down to be joined to the first via contact, wherein the first via contact has a form extended to the inside of the second via contact.
摘要翻译：本发明提供一种多层陶瓷基板，其包括具有第一通孔接点的第一绝缘片; 以及与所述第一绝缘片接合的第二绝缘片，其中所述第二绝缘片具有与所述第一通孔接触件对准的第二通孔接触件，所述第二通孔接触件被上下连接以连接到所述第一通孔接头，其中所述第一通孔接头具有延伸到第二通孔接触件的内部。

29. 发明申请

US20100200888A1 Silicon-Based Sub-Mount for an Opto-Electronic Device 有权
标题翻译：用于光电子器件的硅基子安装
公开(公告)号：US20100200888A1
公开(公告)日：2010-08-12
申请号：US12369993
申请日：2009-02-12
申请人： Jochen Kuhmann , Heike Huscher
发明人： Jochen Kuhmann , Heike Huscher
IPC分类号： H01L33/00 , H01R12/06
CPC分类号： H01L23/13 , H01L23/147 , H01L23/49827 , H01L33/486 , H01L33/62 , H01L2224/48091 , H01L2924/10253 , H01L2924/00012 , H01L2924/00
摘要： A package for an optoelectronic device (e.g., a light emitting device such as a LED) includes a sub-mount including a silicon substrate having a thickness in the range of 350 μm-700 μm. The optoelectronic device is mounted on a die attach pad on the front-side surface of the substrate. Feed-through metallization in one or more via structures electrically couples the die attach pad to a contact pad on the back-side surface of the substrate.
摘要翻译：用于光电器件（例如，诸如LED的发光器件）的封装包括具有厚度在350μm-700μm范围内的硅衬底的子座。光电子器件安装在衬底的正面上的管芯附着焊盘上。一个或多个通孔结构中的直通金属化将管芯附着垫电耦合到衬底的背面表面上的接触焊盘。

30. 发明申请

US20100122842A1 PRINTED CIRCUIT BOARD AND MANUFACTURING METHOD THEREOF 有权
标题翻译：印刷电路板及其制造方法
公开(公告)号：US20100122842A1
公开(公告)日：2010-05-20
申请号：US12428776
申请日：2009-04-23
申请人： Tae-Gui KIM , Young-Hwan Shin , Jae-Soo Lee , Tae-Gon Lee
发明人： Tae-Gui KIM , Young-Hwan Shin , Jae-Soo Lee , Tae-Gon Lee
IPC分类号： H01R12/06 , H05K3/00
CPC分类号： H05K3/0035 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2924/15311 , H01L2924/181 , H05K3/108 , H05K3/243 , H05K3/421 , H05K3/427 , H05K2201/0394 , H05K2201/09481 , H05K2201/09736 , H05K2203/0369 , H01L2924/00014 , H01L2924/00012
摘要： A printed circuit board and a method of manufacturing the printed circuit board are disclosed. The method of manufacturing a printed circuit board including a via, which is configured to electrically connect both sides of an insulator, and a pad part, which is formed in one side of the insulator to be directly in contact with the via, can include forming a seed layer part on one side of the insulator, a portion of the seed layer part being bulged, forming a via hole by processing the other side of the insulator, corresponding to the bulged portion of the seed layer part, forming the via inside the via hole, and forming a plating layer, corresponding to the pad part, on the seed layer part. With the present invention, it is possible to form a pattern having a finer pitch, maintaining a VOP structure and to prevent a lower side of a substrate from being penetrated through when a via hole is processed.
摘要翻译：公开了印刷电路板和印刷电路板的制造方法。制造包括通孔的印刷电路板的制造方法，该印刷电路板被配置为电连接绝缘体的两侧，并且形成在绝缘体的一个侧面中以与通孔直接接触的焊盘部分可以包括成形种子层部分在绝缘体的一侧上，种子层部分的一部分被凸出，通过处理绝缘体的另一侧形成通孔，对应于种子层部分的凸起部分，在该内部形成通孔并且在种子层部分上形成对应于焊盘部分的镀层。利用本发明，可以形成具有更细的间距的图案，保持VOP结构并且防止当加工通孔时衬底的下侧被穿透。

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