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21. 发明申请

US20030214846A1 CLAMPING CIRCUIT FOR THE VPOP VOLTAGE USED TO PROGRAM ANTIFUSES 失效
标题翻译：用于VPOP电压的钳位电路用于程序设计
公开(公告)号：US20030214846A1
公开(公告)日：2003-11-20
申请号：US10147037
申请日：2002-05-17
发明人： Jeffrey Koelling , Timothy B. Cowles
IPC分类号： G11C005/14
CPC分类号： G11C17/18 , G11C5/145
摘要： A booting circuit, used during antifuse programming, that has a clamping circuit designed to prevent a programming voltage from being unnecessarily limited by other components in an integrated circuit. The booting circuit is connected between an external interface, such as a bond pad, and an internal line, and is activated when the programming voltage is being applied directly to the internal line (i.e., not through the external interface). When activated, the clamping circuit allows a suitable and sufficiently high voltage to be applied to the internal line to properly program the antifuses while also clamping the amount of voltage seen at the external interface.
摘要翻译：在反熔丝编程期间使用的引导电路具有钳位电路，其被设计成防止编程电压被集成电路中的其他部件不必要地限制。引导电路连接在外部接口（例如接合焊盘）和内部线路之间，并且当编程电压被直接施加到内部线路（即，不通过外部接口）时被激活。当被激活时，钳位电路允许向内部线路施加适当且足够高的电压，以正确编程反熔丝，同时还夹紧在外部接口处看到的电压量。

22. 发明申请

US20030095462A1 Memory device and method of accessing a memory device 有权
标题翻译：存储器件和访问存储器件的方法
公开(公告)号：US20030095462A1
公开(公告)日：2003-05-22
申请号：US10290365
申请日：2002-11-07
发明人： Andre Schafer , Andrea Zuckerstatter
IPC分类号： G11C005/14
CPC分类号： G11C5/14
摘要： A memory device comprises a memory module, a control unit and a bus connected to the memory module and the control unit. In an accessing operation of the memory module via bus, the control unit applies a first command which causes high power consumption in the memory module, to the memory module via part of the bus only.
摘要翻译：存储器件包括存储器模块，控制单元和连接到存储器模块和控制单元的总线。在通过总线对存储器模块进行访问操作时，控制单元仅通过部分总线将存储模块中的高功耗的第一命令应用于存储器模块。

23. 发明申请

US20020089889A1 Charge pump circuit and operation method of a nonvolatile memory using the same 失效
标题翻译：电荷泵电路及使用其的非易失性存储器的操作方法
公开(公告)号：US20020089889A1
公开(公告)日：2002-07-11
申请号：US09972895
申请日：2001-10-10
发明人： Motoharu Ishii , Kayoko Omoto
IPC分类号： G11C005/14
CPC分类号： G11C16/30 , G11C5/145
摘要： There is a provided a charge pump circuit comprising: a first reverse current prevention circuit connected between an external power supply and a first internal node; a first output node, connected to the first internal node, for outputting a first output potential; a second reverse current prevention circuit connected between a second power supply node receiving ground potential and a second internal node; power supply node for receiving a first power supply potential; a first reverse current prevention means connected between the first power supply node and a first internal node; a first output node, connected to the first internal node, for outputting a first output potential; and power supply generation means, connected between the first internal node and second internal node, for enhancing the potential of the second internal node as compared to that of the first internal node, wherein the power supply generation means is formed on or within a semiconductor substrate, and includes a diode element provided so as to flow a current from the first internal node to the second internal node, and a capacitor having one electrode connected to the first and second nodes, and the other electrode provided with a clock signal, thereby enabling higher outputs on both positive and negative voltages.
摘要翻译：提供了一种电荷泵电路，包括：连接在外部电源和第一内部节点之间的第一反向电流防止电路; 连接到第一内部节点的第一输出节点，用于输出第一输出电位; 连接在接收地电位的第二电源节点和第二内部节点之间的第二反向电流防止电路; 用于接收第一电源电位的电源节点; 连接在第一电源节点和第一内部节点之间的第一反向电流防止装置; 连接到第一内部节点的第一输出节点，用于输出第一输出电位; 以及连接在所述第一内部节点和所述第二内部节点之间的电源产生装置，用于与所述第一内部节点相比增强所述第二内部节点的电位，其中所述电源产生装置形成在半导体衬底上或内部并且包括设置成使电流从第一内部节点流动到第二内部节点的二极管元件，以及具有连接到第一和第二节点的一个电极的电容器，以及设置有时钟信号的另一个电极，从而使能正电压和负电压都有较高的输出。

24. 发明申请

US20020024866A1 Voltage regulator and data path for a memory device 有权
公开(公告)号：US20020024866A1
公开(公告)日：2002-02-28
申请号：US09792537
申请日：2001-02-23
发明人： Brian W. Huber
IPC分类号： G11C005/14
CPC分类号： G11C5/147 , G11C5/145
摘要： One aspect of the present invention is directed to a method and apparatus of boosting the gate voltages for transistors controlling the voltage appearing on output pads of a solid state memory device, with the gate voltages being supplied by a voltage regulator through an output bus to a plurality of output blocks. The demand for gate voltage is periodically determined and, when the demand is high, each line of the bus may be momentarily connected to a voltage source. In addition, additional current is temporarily sourced to the output terminal of the voltage regulator. Another aspect of the present invention is directed to a method and apparatus of producing a control pulse of an extended duration for use in the voltage regulator. A first logic gate receives a plurality of signals each representative of the voltage demand of one of the plurality of output blocks and produces a control pulse of a first duration. A plurality of delay circuits receives the control pulse and produces a plurality of delayed control pulses. A second logic gate receives the control pulse and the plurality of delayed control pulses and produces a control pulse of extended duration. The control pulse of extended duration may be used, for example, for temporarily sourcing additional current to an output terminal of the voltage regulator. According to another aspect of the present invention, a method is disclosed of forcing a voltage regulator into a low power mode. Another aspect of the present invention is directed to a pre-driver or the like which provides variable output drive capability. The pre-driver is comprised of two paths each divided into output stages. A signal is generated in response to determining the relative strength of the n-channel and p-channel transistors in a subsequent output amplifier. The signal is then used to enable certain of the output stages in each of the output paths.

25. 发明申请

US20010028591A1 Semiconductor memory device having normal and standby modes, semiconductor integrated circuit and mobile electronic unit 有权
标题翻译：具有正常和待机模式的半导体存储器件，半导体集成电路和移动电子单元
公开(公告)号：US20010028591A1
公开(公告)日：2001-10-11
申请号：US09814855
申请日：2001-03-23
申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
发明人： Hiroyuki Yamauchi
IPC分类号： G11C005/14
CPC分类号： G11C5/145 , G11C8/08 , G11C11/417
摘要： In a standby mode, a word driver supplies a negative voltage onto its associated word line, and a precharge circuit electrically disconnects its associated pair of bit lines from power supply nodes receiving a supply voltage. In this manner, access transistors, connected to L- or H-level data retention nodes, can have their source-drain voltage lowered to such a level as eliminating a GIDL current. As a result, the amount of current dissipated in the standby mode can be reduced without causing the GIDL current problem.
摘要翻译：在待机模式中，字驱动器向相关联的字线提供负电压，并且预充电电路将其相关联的一对位线与接收电源电压的电源节点电断开。以这种方式，连接到L或H电平数据保持节点的存取晶体管可以使它们的源极 - 漏极电压降低到消除GIDL电流的水平。结果，可以减少在待机模式下耗散的电流量，而不会导致GIDL当前的问题。

26. 发明申请

US20040160840A1 Voltage regulator and data path for a memory device 有权
标题翻译：用于存储器件的稳压器和数据通路
公开(公告)号：US20040160840A1
公开(公告)日：2004-08-19
申请号：US10678722
申请日：2003-10-03
发明人： Brian W. Huber
IPC分类号： G11C005/14 , G11C007/00 , G06F011/34
CPC分类号： G11C5/147 , G11C5/145
摘要： A method of boosting the voltage supplied to an output pad driver through a bus connected to a voltage regulator. The method comprises momentarily connecting the bus directly to a voltage source and temporarily enabling the voltage regulator to source additional current to an output terminal thereof. A method of boosting the gate voltages for transistors controlling the voltage appearing on output pads of a solid state memory device, the gate voltages supplied by a voltage regulator through an output bus. The method comprises periodically determining the demand for gate voltage and, when the demand is high, momentarily connecting each line of the bus to a voltage source, and temporarily enabling the voltage regulator to source additional current to an output terminal thereof.
摘要翻译：一种通过连接到电压调节器的总线来升压提供给输出焊盘驱动器的电压的方法。该方法包括将总线直接连接到电压源，并暂时使电压调节器将额外的电流输出到其输出端。一种用于提高控制固态存储器件的输出焊盘上出现的电压的晶体管的栅极电压的方法，由电压调节器通过输出总线提供的栅极电压。该方法包括周期性地确定对栅极电压的需求，并且当需求高时，暂时将总线的每条线路连接到电压源，并且暂时使电压调节器能够向其输出端子提供额外的电流。

27. 发明申请

US20040130960A1 Bit line control for low power in standby 有权
标题翻译：位线控制为低功耗待机
公开(公告)号：US20040130960A1
公开(公告)日：2004-07-08
申请号：US10337069
申请日：2003-01-06
发明人： Theodore W. Houston , Xiaowei Deng
IPC分类号： G11C005/14
CPC分类号： G11C7/12 , G11C11/417 , G11C2207/2227
摘要： The present invention achieves technical advantages as embodiments of an SRAM cell (20, 30) having the bit line voltage (BLB/BLB) controlled during standby, such as allowing the bit line to float allowing the bit line voltage to be established by balance of leakage currents to the minimum leakage through the bit line. Advantageously, a controller (22, 32) also controls voltages of supplies Vdd, Vss and the n-well (Vnwell) voltage. The controller reduces a voltage differential between the supply voltage Vdd and voltage Vss in the standby mode. In one embodiment, the bit line may be tied to the reference voltage Vss, and a time delay may be introduced to reduce the possibility of using more charge in switching than that saved.
摘要翻译：本发明实现了在待机期间控制位线电压（BLB / BLB）的SRAM单元（20,30）的实施例的技术优点，例如允许位线浮动允许位线电压通过平衡泄漏电流通过位线的最小泄漏。有利地，控制器（22,32）还控制电源Vdd，Vss和n阱（Vnwell）电压的电压。控制器在待机模式下降低电源电压Vdd与电压Vss之间的电压差。在一个实施例中，位线可以被连接到参考电压Vss，并且可以引入时间延迟以减少在切换中使用比所保存的更多电荷的可能性。

28. 发明申请

US20040080987A1 LEAKAGE CONTROL CIRCUIT 有权
标题翻译：泄漏控制电路
公开(公告)号：US20040080987A1
公开(公告)日：2004-04-29
申请号：US10318713
申请日：2002-12-13
申请人： Nanya Technology Corporation
发明人： Chih-Jen Chen
IPC分类号： G11C005/14
CPC分类号： G11C11/417
摘要： A leakage control circuit and DRAM equipped therewith. The leakage control circuit includes a differential amplifier, a first voltage divider, a second voltage divider, MOS transistors, and a charge pump. The first voltage generates a first reference voltage. The second voltage divider generates a second reference voltage. The differential amplifier has a first input receiving the first reference voltage, a second input receiving the second reference voltage, and an output coupled to the input of the charge pump. MOS transistors have drains coupled to the first input of the differential amplifier, gates coupled to the output of the charge pump, and sources coupled to a ground potential.
摘要翻译：泄漏控制电路和配备有它的DRAM。泄漏控制电路包括差分放大器，第一分压器，第二分压器，MOS晶体管和电荷泵。第一电压产生第一参考电压。第二分压器产生第二参考电压。差分放大器具有接收第一参考电压的第一输入端，接收第二参考电压的第二输入端和耦合到电荷泵输入端的输出端。 MOS晶体管具有耦合到差分放大器的第一输入端的漏极，耦合到电荷泵的输出的栅极和耦合到地电势的源极。

29. 发明申请

US20030210601A1 BACK UP POWER EMBODIED NON-VOLATILE MEMORY DEVICE 失效
标题翻译：备份电源非易失性存储器件
公开(公告)号：US20030210601A1
公开(公告)日：2003-11-13
申请号：US10248251
申请日：2002-12-31
发明人： YU-CHUAN LIN , CHUN-CHIEH CHEN , HUNG-JU SHEN , CHIEN-HUA WU , SHENG-LIN CHIU , HUAN-TUNG WANG , HSIN-CHIH HUNG
IPC分类号： G11C005/14
CPC分类号： G11C5/141 , G11C16/30
摘要： A back up power embodied non-volatile memory device comprising a connection port, a power supply unit and a memory system. A host machine provides data and power to the connection port through an external bus. The memory system holds the data received from the connection port temporarily and transfers the data to a non- volatile memory unit inside the memory system. The power supply unit provides necessary power to complete the transfer of temporarily stored data inside the memory system to the non-volatile memory unit to become readable data when host power suddenly fails.
摘要翻译：备用电力体现的非易失性存储器件包括连接端口，电源单元和存储器系统。主机通过外部总线为连接端口提供数据和电源。存储器系统暂时保持从连接端口接收到的数据，并将数据传送到存储器系统内的非易失性存储器单元。当主机电源突然发生故障时，电源单元提供必要的电力来完成将存储器系统内临时存储的数据传送到非易失性存储器单元以变成可读数据。

30. 发明申请

US20030161209A1 Searchline control circuit and power reduction method 失效
公开(公告)号：US20030161209A1
公开(公告)日：2003-08-28
申请号：US10357394
申请日：2003-02-04
发明人： Peter B. Gillingham , Abdullah Ahmed
IPC分类号： G11C005/14
CPC分类号： G11C15/04 , G11C15/043
摘要： A system and method for reduction of power consumed by a searchline buffer and control circuit during a CAM search-and-compare operation. The data buffer circuit samples one bit of a search word and a mask bit for driving a pair of complementary searchlines with the appropriate logic levels. The complementary searchlines are precharged to a mid-point voltage level between the high logic level voltage and the low logic level voltage during a precharge phase. The mid-point voltage level is applied on each searchline by sharing charge from the searchline at the high logic level voltage with the searchline at the low logic level voltage. Additional control logic compares the searchline data of the current search-and-compare operation with the next search-and-compare operation, to inhibit searchline precharging when both searchline data are at the same logic level.

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