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    • 21. 发明授权
    • Multi-stage noise shaping analog-to-digital converter
    • 多级噪声整形模数转换器
    • US09178529B2
    • 2015-11-03
    • US14057153
    • 2013-10-18
    • ANALOG DEVICES TECHNOLOGY
    • Yunzhi DongHajime ShibataWenhua W. YangRichard E. Schreier
    • H03M3/00H03M1/00H03M1/12H04L25/06H04M1/725H03M1/14
    • H03M3/344H03M1/00H03M1/12H03M1/144H03M1/145H03M3/30H03M3/416H04L25/067H04M1/72519
    • The present disclosure describes an improved multi-stage noise shaping (MASH) analog-to-digital converter (ADC) for converting an analog input signal to a digital output signal. In particular, a full delta-sigma (ΔΣ) modulator is provided at the front-end of the MASH ADC, and another full ΔΣ modulator is provided at the back-end of the MASH ADC. The front-end ΔΣ modulator digitizes an analog input signal, and the back-end ΔΣ modulator digitizes an error between the output of the front-end ΔΣ modulator and the (original) analog input signal. In this configuration where the back-end modulator digitizes the error of the (full) front-end modulator, some design constraints of the front-end are relaxed. These design constraints include thermal noise, digital noise cancellation filter complexity (the quantization noise of the front-end is already shaped by the noise transfer function of the front-end), and/or non-linearity.
    • 本公开描述了一种用于将模拟输入信号转换为数字输出信号的改进的多级噪声整形(MASH)模数转换器(ADC)。 特别地,在MASH ADC的前端提供了一个完整的delta-sigma(&Dgr& Sgr)调制器,另一个完整的&Dgr& 调制器设置在MASH ADC的后端。 前端&Dgr&& 调制器将模拟输入信号数字化,后端&Dgr& 调制器数字化前端&Dgr& Sgr的输出之间的误差; 调制器和(原始)模拟输入信号。 在这种配置中,后端调制器将(全)前端调制器的误差数字化,前端的一些设计约束被放宽。 这些设计约束包括热噪声,数字噪声消除滤波器复杂度(前端的量化噪声已经由前端的噪声传递函数形成)和/或非线性。
    • 22. 发明申请
    • REFERENCE BUFFER WITH WIDE TRIM RANGE
    • 参考缓冲区与宽度范围
    • US20150309526A1
    • 2015-10-29
    • US14262274
    • 2014-04-25
    • Analog Devices, Inc.
    • HUSEYIN DINCAhmed Mohamed Abdelatty Ali
    • G05F3/24H03M1/12
    • H03M1/12H03F3/505H03K19/018585H03M1/145H03M1/164H03M1/167H03M1/38
    • Circuits for generating voltage references are common in electronics. For example, these circuits are used in analog-to-digital converters, which convert an analog signal into its digital representation by comparing analog input signals against one or more voltage references provided by those circuits. In many applications, the speed and accuracy of such voltage references are very important. The speed of the voltage references is related to the physical properties of the devices in the circuit. The accuracy of the voltage reference is directly related to the circuit's ability to trim the full-scale voltage output. The present disclosure describes a fast and efficient reference buffer with a wide trim range which is particular suitable for submicron processes and high speed applications. The reference buffer comprises a plurality of diode-connected transistors, which can be selected to turn on or off using a controller to provide a wide trim range.
    • 用于产生电压基准的电路在电子设备中很常见。 例如,这些电路用于模数转换器,其通过将模拟输入信号与由这些电路提供的一个或多个电压参考值相比较来将模拟信号转换成其数字表示。 在许多应用中,这种参考电压的速度和精度非常重要。 电压基准的速度与电路中器件的物理性质有关。 电压参考的精度直接关系到电路修整满量程电压输出的能力。 本公开描述了一种具有宽的修剪范围的快速和有效的参考缓冲器,其特别适用于亚微米工艺和高速应用。 参考缓冲器包括多个二极管连接的晶体管,其可以选择使用控制器导通或关断以提供宽的修整范围。
    • 23. 发明授权
    • A/D converter and method for calibrating the same
    • A / D转换器及其校准方法
    • US08957794B2
    • 2015-02-17
    • US13767233
    • 2013-02-14
    • IMECRenesas Electronics Corporation
    • Bob VerbruggenMasao IriguchiJan Craninckx
    • H03M1/06H03M1/10H03M1/14H03M1/46
    • H03M1/06H03M1/1023H03M1/145H03M1/466
    • An ADC includes sampling means for sampling an input voltage signal, comparator(s) for receiving the sampled signal, and a DAC including circuitry for generating a search signal approximating the input signal and a calibration signal. The search signal and the calibration signal are to be applied to a comparator. The ADC also includes a search logic block for receiving a comparator output signal, for providing input to the DAC for generating the search signal, and for producing a digital output signal. Further, the ADC includes a calibration logic block for producing a control signal to control the circuitry of the DAC and including processing means for observing the output signal, for comparing the output signal with a desired output, and for compensating analog non-idealities of the ADC. The DAC circuitry is adapted for generating the calibration signal in accordance with the control signal and with the sampled input signal.
    • ADC包括用于对输入电压信号进行采样的采样装置,用于接收采样信号的比较器,以及包括用于产生近似输入信号的搜索信号和校准信号的电路的DAC。 搜索信号和校准信号应用于比较器。 ADC还包括用于接收比较器输出信号的搜索逻辑块,用于向DAC提供用于产生搜索信号的输入,以及用于产生数字输出信号。 此外,ADC包括用于产生控制信号以控制DAC的电路的校准逻辑块,并且包括用于观察输出信号的处理装置,用于将输出信号与期望的输出进行比较,并且用于补偿模拟非理想 ADC。 DAC电路适于根据控制信号和采样的输入信号产生校准信号。
    • 24. 发明授权
    • A/D converter
    • A / D转换器
    • US08704694B2
    • 2014-04-22
    • US13697162
    • 2011-05-13
    • Shoji Kawahito
    • Shoji Kawahito
    • H03M1/38
    • H03M1/12H03M1/145H03M1/162H03M1/403H03M1/56H04N5/357H04N5/3575H04N5/378
    • An A/D converter 101 comprises a first cyclic A/D converter circuit 103 and an A/D converter circuit 105. The A/D converter 101 includes a record circuit 107 for storing conversion results from the A/D converter circuits 103, 105. The record circuit 107 includes an upper-bit record circuit 107a and a lower-bit circuit 107b. The cyclic A/D converter circuit 103 receives an analog value SA and generates a first digital value SD1 indicating the analog value SA and a residue value RD. The A/D converter circuit 105 receives the residue value RD and generates a second digital value SD2 having lower M bits indicating the residue value RD. The conversion accuracy in the A/D converter circuit 105 can be lowered to ½L that in the A/D converter circuit 103.
    • A / D转换器101包括第一循环A / D转换器电路103和A / D转换器电路105.A / D转换器101包括用于存储来自A / D转换器电路103,105的转换结果的记录电路107 记录电路107包括高位记录电路107a和下位电路107b。 循环A / D转换电路103接收模拟值SA,并生成表示模拟值SA的第一数字值SD1和残差值RD。 A / D转换电路105接收剩余值RD,并产生具有低M位的第二数字值SD2,表示剩余值RD。 A / D转换电路105的转换精度可以降低到A / D转换电路103中的1/2L。
    • 25. 发明申请
    • Two-stage phase digitizer
    • 两级相位数字化仪
    • US20130214952A1
    • 2013-08-22
    • US13815225
    • 2013-02-11
    • Kofi A.A. MakinwaCaspar Val Vroonhoven
    • Kofi A.A. MakinwaCaspar Val Vroonhoven
    • H03M1/12H03M3/00
    • H03M1/12H03M1/144H03M1/145H03M3/412H03M3/414H03M3/458
    • An analog-to-digital converter (ADC) is described. This ADC converts an analog signal into a digital value using a two-pass digitization process. In a first operation, coarse digitization is performed by an averaging converter based on a set of references. Then, in a second operation, fine digitization is performed by either another averaging converter or the same averaging converter based on a subset of the set of references that is progressively closer to an instantaneous value of the analog signal. For example, the coarse digitization may be performed by a low-resolution ADC stage and the fine digitization may be performed by a sigma-delta ADC, such as a single-bit sigma-delta ADC. Moreover, the other averaging converter may use dynamic element matching to shuffle reference elements used to generate the subset. In this way, the ADC may provide high resolution with reduced nonlinearity and quantization noise.
    • 描述了一种模拟 - 数字转换器(ADC)。 该ADC使用二次数字化处理将模拟信号转换为数字值。 在第一操作中,基于一组参考的平均转换器执行粗略数字化。 然后,在第二操作中,基于逐渐接近模拟信号的瞬时值的参考集合的子集,由另一个平均转换器或相同的平均转换器执行精细数字化。 例如,粗略数字化可以由低分辨率ADC级执行,精细数字化可以由诸如单位Σ-ΔADC之类的Σ-ΔADC来执行。 此外,另一个平均转换器可以使用动态元素匹配来混洗用于生成子集的参考元素。 以这种方式,ADC可以提供具有降低的非线性和量化噪声的高分辨率。
    • 28. 发明授权
    • Analog-to-digital converter on two bits with successive approximations
    • 具有逐次逼近的两位模数转换器
    • US08344926B2
    • 2013-01-01
    • US12913297
    • 2010-10-27
    • Gilbert Decaens
    • Gilbert Decaens
    • H03M1/38
    • H03M1/38H03M1/144H03M1/145
    • The analog-to-digital converter comprises a first stage in which a voltage to be converted is applied to the input of a first comparator. The first comparator delivers a first digital result representative of the comparison between the voltage to be converted and the reference voltage on a first digital output. The first digital output is connected to means for calculating a first intermediate voltage. A second comparator compares the first intermediate voltage with the reference voltage and delivers a second digital result on a second digital output terminal. The digital output terminal is connected to second means for calculating a residual voltage according to the voltage to be converted, the first and second voltages and the first and second digital results.
    • 该模数转换器包括第一级,其中将要转换的电压施加到第一比较器的输入端。 第一个比较器提供第一个数字结果,代表第一个数字输出上要转换的电压与参考电压之间的比较。 第一数字输出连接到用于计算第一中间电压的装置。 第二比较器将第一中间电压与参考电压进行比较,并在第二数字输出端子上传送第二数字结果。 数字输出端子连接到用于根据要转换的电压,第一和第二电压以及第一和第二数字结果计算残余电压的第二装置。
    • 30. 发明授权
    • Solid-state imaging device, method of driving the same, and camera
    • 固态成像装置,驱动方法和相机
    • US08111312B2
    • 2012-02-07
    • US11680778
    • 2007-03-01
    • Hiroki Sato
    • Hiroki Sato
    • H04N5/335H03M1/12H03M1/66
    • H04N5/335H03M1/145H04N5/378
    • A solid-state imaging device includes: a plurality of pixels which are arranged in a matrix; a sequential scanning device that selects each row of pixels; and an analog-to-digital conversion unit having a first analog-to-digital converter that is connected to a vertical signal line to which a pixel signal is supplied from the pixel and performs a first bit-length analog-to-digital conversion on an output signal from the vertical signal line or a pixel output signal obtained by sampling the output signal, and a second analog-to-digital converter that, when the first analog-to-digital converter completes the conversion operation, subtracts an analog signal corresponding to the first bit-length from the pixel output signal and then performs a second bit-length analog-to-digital conversion.
    • 固态成像装置包括:排列成矩阵的多个像素; 选择每行像素的顺序扫描装置; 以及模数转换单元,其具有第一模数转换器,该第一模数转换器连接到从该像素提供像素信号的垂直信号线,并对该像素信号进行第一位长模拟数字转换 来自垂直信号线的输出信号或通过对输出信号进行采样得到的像素输出信号;以及第二模数转换器,当第一模数转换器完成转换操作时,减去相应的模拟信号 从像素输出信号到第一位长,然后执行第二位长度的模数转换。