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21. 发明公开

US20230299780A1 Cloud Assisted Calibration of Analog-to-Digital Converters 审中-公开
公开(公告)号：US20230299780A1
公开(公告)日：2023-09-21
申请号：US18300305
申请日：2023-04-13
申请人： Microsoft Technology Licensing, LLC
发明人： Kenneth Colin DYER
IPC分类号： H03M1/06 , G06N3/04 , H03M1/10 , G06F18/214
CPC分类号： H03M1/0687 , G06F18/214 , G06N3/04 , H03M1/1052
摘要： Embodiments of the present disclosure includes systems and methods for diagnosing and correcting deficiencies in operation of integrated circuits. A set of operational data of an integrated circuit is received by a network via a communication interface. A deficiency in operation of the integrated circuit is diagnosed based on the set of operational data. A correction is generated for improving operation of the integrated circuit based on the deficiency diagnosed. The correction is transmitted over the network via the communication interface to the integrated circuit.

22. 发明申请

US20160291056A1 BAND OVERLAY SEPARATOR 有权
标题翻译：带覆盖分隔器
公开(公告)号：US20160291056A1
公开(公告)日：2016-10-06
申请号：US14674344
申请日：2015-03-31
申请人： Tektronix, Inc.
发明人： John J. Pickerd , Kan Tan
IPC分类号： G01R13/02 , G01R13/22
CPC分类号： G01R13/0218 , G01R13/0272 , G01R13/225 , H03M1/1052 , H03M1/1215
摘要： A test and measurement instrument including a splitter configured to split an input signal into at least two split signals, at least two harmonic mixers configured to mix an associated split signal with an associated harmonic signal to generate an associated mixed signal, at least two digitizers configured to digitize the associated mixed signal, at least two MIMO polyphase filter arrays configured to filter the associated digitized mixed signal of an associated digitizer of the at least two digitizers, at least two pairs of band separation filters configured to receive the associated digitized mixed signals from each of the MIMO polyphase filter arrays and output a low band of the input signal and a high band of the input signal based on a time different between the at least two digitizers and a phase drift of a local oscillator, and a combiner configured to combine the low band of the input signal and the high band of the input signal to form a reconstructed input signal.
摘要翻译：一种包括分配器的测试和测量仪器，其被配置为将输入信号分成至少两个分离信号，至少两个谐波混合器被配置为将相关联的分离信号与相关联的谐波信号混合以产生相关联的混合信号，至少两个数字化器被配置至少两个MIMO多相滤波器阵列被配置为对所述至少两个数字化仪的相关联的数字转换器的相关联的数字化混合信号进行数字化，至少两对频带分离滤波器被配置成从相关联的数字化混合信号中接收相关联的数字化混合信号每个MIMO多相滤波器阵列，并且基于所述至少两个数字转换器之间的时间和本地振荡器的相位漂移而输出所述输入信号的低频带和所述输入信号的高频带，以及被配置为组合的组合器输入信号的低频带和输入信号的高频带，以形成重构的输入信号。

23. 发明授权

US09281834B1 N-path interleaving analog-to-digital converter (ADC) with offset gain and timing mismatch calibration 有权
标题翻译：具有偏移增益和定时不匹配校准的N路径交错模数转换器（ADC）
公开(公告)号：US09281834B1
公开(公告)日：2016-03-08
申请号：US14927077
申请日：2015-10-29
申请人： IQ-Analog Corporation
发明人： Mikko Waltari
IPC分类号： H03M1/10 , H03M1/12
CPC分类号： H03M1/1023 , H03M1/0626 , H03M1/0836 , H03M1/1052 , H03M1/121 , H03M1/1215 , H03M1/1245
摘要： A system and method are provided for calibrating timing mismatch in an n-path time interleaved analog-to-digital converter (ADC). The method digitizes an analog signal with an n-path interleaved ADC, creating an interleaved ADC signal. In a first process, the phase of the interleaved ADC signal is rotated by 90 degrees, creating a rotated signal. This rotation may be accomplished using a finite impulse response (FIR) filter with taps at {0.5, 0, −0.5}, enabled as a derivative filter, or as a Hilbert transformation. In a parallel second process, the interleaved ADC signal is delayed, creating a delayed signal. The rotated signal is multiplied by the delayed signal to create a timing error signal. Using the timing error signal, timing errors are accumulated for the ADC signal paths, and corrections are applied that minimize timing errors in each of the n ADC signal paths.
摘要翻译：提供了一种用于校准n路时间交错模数转换器（ADC）中的定时失配的系统和方法。该方法将模拟信号与n路交错ADC进行数字化，产生交错的ADC信号。在第一过程中，交错的ADC信号的相位旋转90度，产生旋转的信号。该旋转可以使用具有{0.5,0，-0.5}的抽头的有限脉冲响应（FIR）滤波器，作为导数滤波器使能，或作为希尔伯特变换来完成。在并行的第二过程中，交织的ADC信号被延迟，产生延迟的信号。旋转的信号乘以延迟信号以产生定时误差信号。使用定时误差信号，对ADC信号路径累积定时误差，并且施加使n个ADC信号路径中的每一个中的定时误差最小化的校正。

24. 发明授权

US09160310B2 Linearity compensator for removing nonlinear distortion 有权
标题翻译：用于去除非线性失真的线性补偿器
公开(公告)号：US09160310B2
公开(公告)日：2015-10-13
申请号：US13915484
申请日：2013-06-11
申请人： Scott R. Velazquez , Richard J. Velazquez
发明人： Scott R. Velazquez , Richard J. Velazquez
IPC分类号： H03H21/00 , H04L27/26 , H04B1/00 , H04L25/02 , H04L25/14 , H04L27/00
CPC分类号： H03H21/0067 , H03H21/0043 , H03M1/1052 , H04B1/001 , H04L25/02 , H04L25/14 , H04L27/0006 , H04L27/0012 , H04L27/265
摘要： The present invention is an improved linearizer that implements more complex transfer functions to provide the necessary linearization performance with a reasonable amount of signal processing resources. Particularly, the linearizer operates on an analog-to-digital converter and comprises a distortion compensator and one or more factored Volterra compensators, which may include a second-order factored Volterra compensator, a third-order factored Volterra compensator, and additional higher-order factored Volterra compensators. Inclusion of factored Volterra distortion compensators improves linearization processing performance while significantly reducing the computational complexity compared to a traditional Volterra-based compensator.
摘要翻译：本发明是一种改进的线性化器，其实现更复杂的传递函数，以提供具有合理数量的信号处理资源的必要的线性化性能。特别地，线性化器在模数转换器上操作，并且包括失真补偿器和一个或多个因子Volterra补偿器，其可以包括二阶因子Volterra补偿器，三阶因子Volterra补偿器和附加高阶沃尔特拉补偿器。与传统的基于沃尔泰拉的补偿器相比，包含因子Volterra失真补偿器提高了线性化处理性能，同时显着降低了计算复杂度。

25. 发明授权

US08842033B1 Dynamic linearity corrector for digital-to-analog converters 有权
标题翻译：用于数模转换器的动态线性校正器
公开(公告)号：US08842033B1
公开(公告)日：2014-09-23
申请号：US14042359
申请日：2013-09-30
申请人： Agilent Technologies, Inc.
发明人： Valentin Abramzon
IPC分类号： H03M1/66
CPC分类号： H03M1/0626 , H03M1/1052 , H03M1/66
摘要： A predistortion generator includes a sample input, a summing circuit to output predistorted samples to a DAC, and distortion term processors, each including a product generator and a FIR filter in tandem. The distortion term processors include a second-order and/or a third-order distortion term processor. In the second-order distortion term processor, the product generator generates a product of only two samples corresponding to a current sample as a respective second-order distortion term that is filtered by the FIR filter thereof using a respective FIR filter characteristic. In the third-order distortion term processor, the product generator generates a product of only three samples corresponding to the current sample as a respective third-order distortion term that is filtered by the FIR filter thereof using a respective FIR filter characteristic. The FIR filter characteristics of FIR filters are configured to reduce distortion in a designated Nyquist zone.
摘要翻译：预失真发生器包括采样输入，将预失真采样输出到DAC的求和电路，以及每个包括产品发生器和FIR滤波器的失真项处理器。失真项处理器包括二阶和/或三阶失真项处理器。在二阶失真项处理器中，乘积发生器产生仅对应于当前采样的两个采样的乘积作为由其FIR滤波器使用各自的FIR滤波器特性滤波的相应的二阶失真项。在三阶失真项处理器中，乘积发生器产生仅对应于当前样本的三个样本的乘积作为使用相应的FIR滤波器特性由其FIR滤波器滤波的相应的三阶失真项。 FIR滤波器的FIR滤波器特性被配置为减少指定的奈奎斯特区域的失真。

26. 发明授权

US08638248B2 Input-independent self-calibration method and apparatus for successive approximation analog-to-digital converter with charge-redistribution digital to analog converter 有权
标题翻译：用于具有电荷再分配数模转换器的逐次逼近模数转换器的独立于输入的自校准方法和装置
公开(公告)号：US08638248B2
公开(公告)日：2014-01-28
申请号：US13269495
申请日：2011-10-07
申请人： Qiong Wu , Kevin Mahooti
发明人： Qiong Wu , Kevin Mahooti
IPC分类号： H03M1/06
CPC分类号： H03M1/1047 , H03M1/1052 , H03M1/462 , H03M1/468
摘要： A method and apparatus for correcting the offset and linearity error of a data acquisition system. A charge redistribution digital to analog convertor (CDAC) is connected to one of the differential inputs of a comparator whose second input comes from a function CDAC. The calibration algorithm is built into a digital control unit. The digital control unit detects the offset and capacitor mismatch errors sequentially, stores the calibration codes for each error in calibration mode and provides the input-dependent error correction signals synchronized with the binary search timing to adjust the differential input of the comparator and compensate the input-dependent errors present at the output of the non-ideal function CDAC during normal conversions.
摘要翻译：一种用于校正数据采集系统的偏移和线性误差的方法和装置。电荷再分配数字到模拟转换器（CDAC）连接到比较器的一个差分输入端，其比较器的第二输入来自功能CDAC。校准算法内置在数字控制单元中。数字控制单元依次检测偏移和电容器失配误差，将每个误差的校准码存储在校准模式中，并提供与二进制搜索定时同步的输入相关误差校正信号，以调整比较器的差分输入并补偿输入在正常转换期间，非理想函数CDAC的输出存在相关误差。

27. 发明授权

US08564463B2 Integrated Non-Linearity (INL) and Differential Non-Linearity (DNL) correction techniques for digital-to-analog converters (DACS) 有权
标题翻译：用于数模转换器（DACS）的集成非线性（INL）和差分非线性（DNL）校正技术
公开(公告)号：US08564463B2
公开(公告)日：2013-10-22
申请号：US13411253
申请日：2012-03-02
申请人： Iskender Agi
发明人： Iskender Agi
IPC分类号： H03M1/06
CPC分类号： H03M1/1052 , H03M1/66
摘要： INL values are determined for sub-segments of a DAC adapted to accept N bit digital input codes, and a first set of correction codes that can be used to reduce to a range of INL values (to improve linearity of the DAC) are determined and stored. Additionally, DNL values are determined for the sub-segments of the DAC, and a second set of correction codes that can be used to ensure that all values of DNL>−1 (to ensure that the DAC is monotonic) are determined and stored. This can include using one or more extra bits of resolution to remap at least some of the 2^N possible digital input codes (that can be accepted by the DAC) to more than 2^N possible digital output codes, to ensure that all values of DNL>−1. Such stored first and second sets are thereafter used when performing digital to analog conversions.
摘要翻译：确定适用于接受N位数字输入代码的DAC的子段的INL值，并且确定可用于减小到INL值的范围（以提高DAC的线性度）的第一组校正码，并且存储。另外，为DAC的子段确定DNL值，以及第二组校正码，可用于确保DNL> -1的所有值（以确保DAC是单调的）的确定和存储。这可以包括使用一个或多个额外的分辨率来将至少一些可能的数字输入代码（可被DAC接受）重新映射到超过2 ^ N个可能的数字输出代码，以确保所有值 DNL> -1。此后，在进行数模转换时使用这样存储的第一和第二组。

28. 发明授权

US08223045B2 D/A converter and electron beam exposure apparatus 有权
标题翻译： D / A转换器和电子束曝光装置
公开(公告)号：US08223045B2
公开(公告)日：2012-07-17
申请号：US12800568
申请日：2010-05-18
申请人： Hidefumi Yabara
发明人： Hidefumi Yabara
IPC分类号： H03M1/06
CPC分类号： H03M1/1052 , H03M1/687
摘要： A D/A converter includes a D/A converter base part having a first D/A converter unit performing D/A conversion of high order bits and a second D/A converter unit performing D/A conversion of low order bits and including an auxiliary bit assigned an identical weight to a least significant bit, a correction D/A converter part, an error detection processing section generating a digital code supplied to a correction D/A converter unit in the correction D/A converter part, and a control section. The control section compares one bit current source with another bit current source in a lower order than the one bit current source, and corrects a value of the one bit current source by causing to supply the digital code to the correction D/A converter unit when the value of the one bit current source changes.
摘要翻译： AD / A转换器包括具有执行高阶比特D / A转换的第一D / A转换器单元的D / A转换器基座部分和执行低位比特的D / A转换的第二D / A转换器单元，并且包括辅助比特分配与最低有效位相同的权重，校正D / A转换器部分，产生提供给校正D / A转换器部分中的校正D / A转换器单元的数字代码的错误检测处理部分，以及控制部分。控制部分将一位电流源与另一位电流源以比一位电流源低的顺序进行比较，并通过使数字代码提供给校正D / A转换器单元来校正一位电流源的值，一位电流源的值发生变化。

29. 发明申请

US20070188365A1 METHOD FOR DETERMINING AND METHOD FOR COMPENSATING A CHARACTERISTIC OF AN A/D CONVERTER, CIRCUIT ARRANGEMENT FOR DETERMINING SUCH A CHARACTERISTIC, AND A/D CONVERTER CIRCUIT ARRANGEMENT 有权
标题翻译：用于确定A / D转换器特性的确定方法和方法，用于确定这种特性的电路布置和A / D转换器电路布置
公开(公告)号：US20070188365A1
公开(公告)日：2007-08-16
申请号：US11626153
申请日：2007-01-23
申请人： Christian Bock , Miodrag Tereminac
发明人： Christian Bock , Miodrag Tereminac
IPC分类号： H03M1/12
CPC分类号： H03M1/1052
摘要： An analog-to-digital converter circuit arrangement comprising an analog-to-digital converter that receives an analog input signal and provides a digital output signal. A correction device that corrects the digital output signal using multidimensional correction coefficients indicative of a characteristic of the analog-to-digital converter to be compensated for, and provides a corrected digital output signal indicative thereof.
摘要翻译：一种模数转换器电路装置，包括接收模拟输入信号并提供数字输出信号的模拟 - 数字转换器。一种校正装置，其使用指示要补偿的模数转换器的特性的多维校正系数校正数字输出信号，并提供指示其的经校正的数字输出信号。

30. 发明授权

US06570514B1 Linearity error compensator 有权
标题翻译：线性误差补偿器
公开(公告)号：US06570514B1
公开(公告)日：2003-05-27
申请号：US10194804
申请日：2002-07-12
申请人： Scott R. Velazquez
发明人： Scott R. Velazquez
IPC分类号： H03M106
CPC分类号： H03M1/1052 , H03M1/12
摘要： In one aspect, the present invention is directed to a compensator for compensating linearity errors, such as harmonic distortion and intermodulation distortion, in devices. The compensator includes a means for phase-shifting and a means for exponentiation to generate a compensation signal such that the linearity error distortion signals are canceled in the system output while maintaining the desired fundamental signal. Another aspect of the invention is directed to methods for calibrating linearity error compensators.
摘要翻译：一方面，本发明涉及用于补偿装置中的线性误差（诸如谐波失真和互调失真）的补偿器。补偿器包括用于相移的装置和用于求幂的装置以产生补偿信号，使得线性误差失真信号在系统输出中被消除，同时保持期望的基本信号。本发明的另一方面涉及校准线性误差补偿器的方法。

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