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    • 22. 发明授权
    • Apparatus and methods for voltage comparison
    • 用于电压比较的装置和方法
    • US08810282B2
    • 2014-08-19
    • US13725631
    • 2012-12-21
    • Analog Devices, Inc.
    • Hongxing Li
    • H03K5/22
    • H03F3/45179H03F1/223H03G3/00H03K5/2481H03K5/249H03M1/12
    • Apparatus and methods for voltage comparison are provided. In one embodiment, a comparator includes a first input transistor having a gate configured to receive a first input voltage and a second input transistor having a gate configured to receive a second input voltage. The first and second input transistors can be used to compare the first input voltage to the second input voltage. Additionally, the comparator further includes a first Miller capacitor electrically connected to a drain of the first input transistor and a second Miller capacitor electrically connected to a drain of the second input transistor. Furthermore, first and second inverting amplification circuits are electrically connected across the first and second Miller capacitors, respectively, so as to increase the effective capacitance of the capacitors. The first and second Miller capacitors can be used to extend the comparator's integration time, thereby enhancing the performance of the comparator.
    • 提供了用于电压比较的装置和方法。 在一个实施例中,比较器包括具有被配置为接收第一输入电压的栅极的第一输入晶体管和具有被配置为接收第二输入电压的栅极的第二输入晶体管。 第一和第二输入晶体管可用于将第一输入电压与第二输入电压进行比较。 此外,比较器还包括电连接到第一输入晶体管的漏极的第一米勒电容器和电连接到第二输入晶体管的漏极的第二米勒电容器。 此外,第一和第二反相放大电路分别跨越第一和第二米勒电容器电连接,以增加电容器的有效电容。 第一和第二米勒电容器可用于扩展比较器的积分时间,从而提高比较器的性能。
    • 23. 发明授权
    • Semiconductor apparatus
    • 半导体装置
    • US08604835B2
    • 2013-12-10
    • US12871564
    • 2010-08-30
    • Koji KurokiRyuji Takishita
    • Koji KurokiRyuji Takishita
    • G01R25/00H03D13/00
    • H03L7/085G11C7/222H03K5/249H03L7/0814H03L7/0816
    • In a semiconductor device, there are provided first to third pairs of nMOS transistors between a GND and two sense nodes and first to third pairs of pMOS transistors between the two sense nodes and the power supply. A first internal clock signal and its inverted signal are supplied to gates of the first pair of nMOS transistors and the second pair of nMOS transistors, respectively. Complementary external clock signals are supplied to the gates of the third pairs of nMOS transistors and the third pairs of pMOS transistors. An inverted version of a second internal clock signal and the second internal clock signal are supplied to gates of the first and second pairs of pMOS transistors. The two sense nodes are connected to inputs of a differential amplifier. The output of the differential amplifier is latched by a latch circuit. Also provided an equalizing circuit precharging/equalizing the two sense nodes (FIG. 2).
    • 在半导体器件中,在GND和两个感测节点之间提供第一至第三对nMOS晶体管,并且在两个感测节点和电源之间提供第一至第三对pMOS晶体管对。 第一内部时钟信号及其反相信号分别被提供给第一对nMOS晶体管和第二对nMOS晶体管的栅极。 互补的外部时钟信号被提供给第三对nMOS晶体管和第三对pMOS晶体管的栅极。 第二内部时钟信号的反相形式和第二内部时钟信号被提供给第一和第二对pMOS晶体管的栅极。 两个感测节点连接到差分放大器的输入。 差分放大器的输出由锁存电路锁存。 还提供了均衡电路对两个感测节点进行预充电/均衡(图2)。
    • 24. 发明授权
    • Shift register and driving method thereof
    • 移位寄存器及其驱动方法
    • US08526568B2
    • 2013-09-03
    • US13039369
    • 2011-03-03
    • Mitsuaki OsameAya Anzai
    • Mitsuaki OsameAya Anzai
    • G11C19/00H03K3/00H03K5/13
    • H03K5/249G11C19/00G11C19/184H03K5/003H03K5/02H03K5/082
    • A low power consumption shift register which inputs a CK signal with a low voltage with almost no effect of variation in characteristics of transistors. In the invention, an input portion of an inverter is set at a threshold voltage thereof and a CK signal is inputted to the input portion, of the inverter through a capacitor means. In this manner, the CK signal is amplified, which is sent to the shift register. That is, by obtaining the threshold potential of the inverter, the shift register which operates with almost no effect of variation in characteristics of transistors can be provided. A level shifter of the CK signal is generated from an output pulse of the shift register, therefore, the low power consumption shift register having the level shifter which flows a shoot-through current for a short period can be provided.
    • 低功耗移位寄存器,其输入具有低电压的CK信号,几乎不影响晶体管的特性变化。 在本发明中,将逆变器的输入部分设定为阈值电压,并通过电容器装置将CK信号输入到逆变器的输入部分。 以这种方式,CK信号被放大,发送到移位寄存器。 也就是说,通过获得反相器的阈值电位,可以提供几乎不影响晶体管特性变化的移位寄存器。 可以从移位寄存器的输出脉冲产生CK信号的电平移位器,因此可以提供具有短时间流过直通电流的电平移位器的低功耗移位寄存器。
    • 26. 发明授权
    • Comparator and analog-to-digital converter
    • 比较器和模数转换器
    • US08487802B2
    • 2013-07-16
    • US13052817
    • 2011-03-21
    • Junichi NakaMasakazu Shigemori
    • Junichi NakaMasakazu Shigemori
    • H03M1/34
    • H03K5/249
    • Increase of power consumption is reduced, and the operational speed is improved. A comparator includes a comparing section which outputs a result of comparison between a first voltage and a second voltage which constitute an input differential signal, a first positive feedback section which operates in synchronism with a first clock signal, amplifies the result from the comparing section, and outputs the amplified result to an output node pair, and a second positive feedback section which operates in synchronism with a second clock signal, and provides positive feedback to the output node pair.
    • 降低功耗增加,运行速度提高。 比较器包括比较部分,其输出构成输入差分信号的第一电压和第二电压之间的比较结果,与第一时钟信号同步操作的第一正反馈部分,放大比较部分的结果, 并将放大的结果输出到输出节点对,以及与第二时钟信号同步工作的第二正反馈部分,并向输出节点对提供正反馈。
    • 28. 发明授权
    • Comparator and analog/digital converter
    • 比较器和模拟/数字转换器
    • US08362934B2
    • 2013-01-29
    • US13127141
    • 2009-10-28
    • Akira MatsuzawaMasaya Miyahara
    • Akira MatsuzawaMasaya Miyahara
    • H03M1/06
    • H03K5/2481H03K3/356139H03K5/249H03M1/0682H03M1/204H03M1/365
    • To provide a comparator and an A/D converter having the comparator. The comparator includes a differential amplifier circuit section and a differential latch circuit section. A first input voltage signal, a second input voltage signal and a clock signal are inputted to the differential amplifier circuit section. The differential amplifier circuit section operates base on the clock signal to output a first output voltage signal and a second output voltage signal which respectively correspond to the value the input voltage signal and the value of the reference voltage signal and are amplified. The differential latch circuit section operates based on the first and second output voltage signals to keep and output a comparison result between the first input voltage signal and the second input voltage signal.
    • 提供具有比较器的比较器和A / D转换器。 比较器包括差分放大器电路部分和差分锁存电路部分。 第一输入电压信号,第二输入电压信号和时钟信号被输入到差分放大器电路部分。 差分放大器电路部分基于时钟信号进行工作,以输出分别对应于输入电压信号的值和参考电压信号的值并被放大的第一输出电压信号和第二输出电压信号。 差分锁存电路部分基于第一和第二输出电压信号进行工作,以保持并输出第一输入电压信号和第二输入电压信号之间的比较结果。