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    • 21. 发明授权
    • Preprocessing circuit for measuring signal envelope flatness degree in a
reproducer
    • 用于测量再现器中信号包络平坦度的预处理电路
    • US5461305A
    • 1995-10-24
    • US61239
    • 1993-05-17
    • Hyoung-Chul Kim
    • Hyoung-Chul Kim
    • H04N5/208G01B7/28H03D1/18H04N17/00
    • H03D1/18
    • A signal envelope measurement preprocessing circuit including: input signal adjuster for interdicting a DC component contained in a signal input for measurement of the degree of flatness of an envelope or for passing only frequencies above a predetermined frequency; first and second half-wave rectifiers for separating into upper and lower portions the envelope of a signal output from the input signal adjusting means to thereafter detect the same; first and second frequency converters for converting a high frequency signal respectively from the first and second half-wave rectifiers into a low frequency signal; an analog-to-digital converters for converting a signal selected from low frequency signals output from the first and second frequency converters to a digital signal; and a system controller for comparing a data output from the analog-to-digital converter with a data stored on an internal program to thereafter measure the degree of flatness of a signal envelope.
    • 一种信号包络测量预处理电路,包括:输入信号调节器,用于截取包含在信号输入中的直流分量,用于测量包络的平坦度或仅通过高于预定频率的频率; 第一和第二半波整流器,用于将从输入信号调节装置输出的信号的包络分为上部和下部,之后检测该信号; 第一和第二频率转换器,用于将来自第一和第二半波整流器的高频信号转换成低频信号; 模数转换器,用于将从第一和第二变频器输出的低频信号中选出的信号转换为数字信号; 以及系统控制器,用于将来自模数转换器的数据输出与存储在内部程序上的数据进行比较,之后测量信号包络的平坦度。
    • 22. 发明授权
    • Receiver of amplitude modulated signals
    • 幅度调制信号接收机
    • US4730603A
    • 1988-03-15
    • US7986
    • 1987-01-28
    • Robert J. Fretz
    • Robert J. Fretz
    • A61F2/02A61B19/00
    • H03D1/10H03D1/18A61F2250/0002Y10S128/903
    • An improvement to an implantable amplitude modulated frequency receiver wherein a resistor in the demodulator portion of a prior art receiver, which provides a discharge path for a capacitor, is replaced with an active circuit portion that includes a semiconductor device that provides the discharge path wherein the conductivity level of the semiconductor device is inversely related to the level of conduction of a rectifier to which the received amplitude modulated signal is applied. The active circuit portion improves the efficiency of the receiver in that less power is lost than in the case of the resistor the active circuit portion replaces.
    • 对植入式幅度调制频率接收机的改进,其中提供用于电容器的放电路径的现有技术接收机的解调器部分中的电阻器被替换为有源电路部分,该有源电路部分包括提供放电路径的半导体器件,其中, 半导体器件的导电电平与施加接收的幅度调制信号的整流器的导通电平成反比。 有源电路部分提高了接收机的效率,因为与有源电路部分替换的电阻器相比,功率损失较少。
    • 24. 发明授权
    • Detectors
    • 探测器
    • US4373139A
    • 1983-02-08
    • US130931
    • 1980-03-17
    • Graham E. Beesley
    • Graham E. Beesley
    • G01R19/22H03D1/18H03G3/20H03G3/34G01R19/02G01R23/09
    • H03G3/3052G01R19/22H03D1/18H03G3/341
    • An averaging detector having a first transistor having a first resistor connected across the base and emitter, a first capacitor connected in a signal input line and to the base of a second transistor, the collectors of the first and second transistors being connected to a positive voltage line and the base of the first transistor being connected to an output voltage line, together with the emitter of the second transistor via a second resistor, an inhibit switch comprising a third transistor being connected between the base of the second transistor and a zero voltage line, a third resistor and second capacitor being connected in parallel between the zero voltage line and the output voltage line, the arrangement being such that on application of a voltage greater than the threshold voltage of the first transistor successive positive and negative cycles alternately reverse bias and forward bias the first and second transistors to achieve a balance between the half cycle charging through the second resistor and the continuous discharge through the third resistor to thereby provide a DC output proportional to the average input voltage waveform envelope.
    • 一种平均检测器,具有第一晶体管,其具有连接在基极和发射极两端的第一电阻器,连接在信号输入线路中的第一电容器和第二晶体管的基极,第一和第二晶体管的集电极连接到正电压 并且所述第一晶体管的基极经由第二电阻器与所述第二晶体管的发射极一起连接到输出电压线;禁止开关,包括连接在所述第二晶体管的基极和零电压线之间的第三晶体管 在所述零电压线和所述输出电压线之间并联连接的第三电阻器和第二电容器,所述布置使得在施加大于所述第一晶体管的阈值电压的电压时,连续的正和负周期交替反向偏置, 正向偏置第一和第二晶体管以实现半周期充电之间的平衡 第二电阻器和通过第三电阻器的连续放电,从而提供与平均输入电压波形包络成比例的DC输出。
    • 26. 发明授权
    • Demodulator for amplitude modulated signal having high input impedance
    • 具有高输入阻抗的幅度调制信号解调器
    • US4319195A
    • 1982-03-09
    • US83709
    • 1979-10-11
    • Eiichi Matsumura
    • Eiichi Matsumura
    • H03D1/18H03G3/10
    • H03D1/18
    • A demodulator for demodulating an amplitude modulated signal of a carrier signal. The demodulator provides a high output and is suitable for use in integrated circuitry. An input signal is connected to the base of one transistor of a pair of transistors forming an input differential amplifier. The input differential amplifier is stably biased by means of a constant current generator, diodes, input resistors and collector resistors. The two opposite phase output voltages from the differential amplifier are applied to the bases of a pair of transistors which have their collectors and emitters tied together. The output from the latter transistor pair is taken from the common emitter connection and it is applied directly to the base of an emitter follower transistor, the output from the latter constituting an output from the demodulator circuitry. The particular circuit arrangement provides significant elimination of the carrier frequency and provides filtering by parasitic capacitances of the transistors.
    • 一种用于解调载波信号的幅度调制信号的解调器。 解调器提供高输出,适用于集成电路。 输入信号连接到形成输入差分放大器的一对晶体管的一个晶体管的基极。 输入差分放大器通过恒流发生器,二极管,输入电阻和集电极电阻稳定偏置。 来自差分放大器的两相反相输出电压被施加到一对晶体管的基极,这些晶体管的集电极和发射极连接在一起。 后一晶体管对的输出取自公共发射极连接,并直接施加到射极跟随器晶体管的基极,后者的输出构成解调器电路的输出。 特定的电路布置提供了载波频率的显着消除,并且通过晶体管的寄生电容提供滤波。
    • 28. 发明授权
    • Signal rectifying circuit
    • 信号整流电路
    • US3970870A
    • 1976-07-20
    • US523857
    • 1974-11-14
    • Tetsuya Horichi
    • Tetsuya Horichi
    • G01R19/22H02M7/12H02M7/21H03D1/18H03K5/00
    • H03D1/18G01R19/22
    • A signal rectifying circuit which is capable of providing rectification either with a balanced or unbalanced input and wherein the output comprises an undelayed signal. A pair of transistors of opposite type are coupled to the input circuit such that they alternately conduct with the positive and negative half cycles of the input signal and wherein a third transistor is coupled to the pair of input transistors such that it conducts during both the positive and negative portions of the input wave so as to provide a rectified output signal. A second embodiment provides a pair of diodes interconnected with the rectifying circuit so as to remove the time delay normally resulting due to the voltage required to bias a transistor to conduction.
    • 一种信号整流电路,其能够提供具有平衡或不平衡输入的整流,并且其中所述输出包括未延迟的信号。 相反类型的一对晶体管耦合到输入电路,使得它们以输入信号的正半周和负半周交替地导通,并且其中第三晶体管耦合到所述一对输入晶体管,使得其在正向 和输入波的负极部分,以提供整流输出信号。 第二实施例提供了与整流电路互连的一对二极管,以便消除由于将晶体管偏压导通所需的电压而导致的时间延迟。
    • 30. 发明授权
    • Peak demodulator
    • 峰值解调器
    • US3651419A
    • 1972-03-21
    • US3651419D
    • 1970-07-06
    • RCA CORP
    • JANZ DONALD WALTER
    • H03D1/18
    • H03D1/18
    • A switch is connected between the output terminal of an amplifier receptive of an amplitude modulated carrier, and a charge storage means. The switch is closed only during each peak of given polarity of an unmodulated carrier of the same frequency as the modulated carrier for permitting the storage means to charge. The time constant of the storage means discharge circuit is sufficiently long so that the storage means does not discharge appreciably during the times the switch is open, whereby a voltage corresponding to the modulation on the carrier develops across the storage means.
    • 开关连接在接收调幅载波的放大器的输出端子和电荷存储装置之间。 开关仅在与调制载波相同频率的未调制载波的给定极性的每个峰值期间闭合,以允许存储装置充电。 存储装置放电电路的时间常数足够长,使得存储装置在开关断开期间不会明显放电,由此在存储装置上形成与载体上的调制相对应的电压。