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21. 发明授权

US6166973A Memory device with multiple-bit data pre-fetch function 有权
标题翻译：具有多位数据预取功能的存储器件
公开(公告)号：US6166973A
公开(公告)日：2000-12-26
申请号：US365508
申请日：1999-08-02
申请人： Naoharu Shinozaki
发明人： Naoharu Shinozaki
IPC分类号： G11C11/407 , G11C7/10 , G11C11/401 , G11C29/00 , G11C29/04 , G11C7/00
CPC分类号： G11C29/842 , G11C7/1039
摘要： The present invention is a memory device having a multiple-bit data pre-fetch function wherein the operation of a redundancy checking circuit for comparing addresses and redundant addresses and checking the coincidence or non-coincidence thereof is started with timing prior to performing the last data fetches. The address signals are supplied with the same timing as the supply of the write commands, wherefore it is not always necessary for the operation of comparing the address signals against the redundant addresses of the memory cells, where the switch to the redundant cell array was performed, to have to wait until all of the multiple-bit data to be fetched. Accordingly, with the present invention, the redundancy checking operation is started before all of the data are fetched. In the case of a 2-bit data pre-fetch, the redundancy checking operation is started after the first datum has been fetched, and before the second bit of data is fetched. That being so, it is possible to begin the decoder operation with timing that is faster by precisely the period of the redundancy checking operation, wherefore it becomes possible to perform write operations to the memory cells with faster timing.
摘要翻译：本发明是具有多位数据预取功能的存储器件，其中用于比较地址和冗余地址的冗余校验电路的操作以及检查其一致性或不一致性是在执行最后数据之前的定时开始的提取以与写入命令的供给相同的时序提供地址信号，因此对于将地址信号与存储器单元的冗余地址进行比较的操作并不总是必需的，其中执行到冗余单元阵列的切换，必须等待所有的多位数据被提取。因此，利用本发明，在获取所有数据之前开始冗余校验操作。在2位数据预取的情况下，在获取第一数据之后并且在获取第二位数据之前开始冗余校验操作。就这样，可以通过精确地进行冗余校验操作的周期的时间更快地开始解码器操作，因此可以以更快的定时对存储器单元执行写入操作。

22. 发明授权

US6097645A High speed column redundancy scheme 有权
标题翻译：高速列冗余方案
公开(公告)号：US6097645A
公开(公告)日：2000-08-01
申请号：US261990
申请日：1999-03-04
申请人： Daniel B. Penney , Jason M. Brown , Frank Alejano
发明人： Daniel B. Penney , Jason M. Brown , Frank Alejano
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/84 , G11C29/842
摘要： A redundancy circuit (300) for generating a standard column access signal (STD) and a redundant column access signal (RED) is disclosed. A modified NOR-type decoder (310) determines if an applied address is the same as a defective address. In the event the applied address is the same as the defective address, a match indication is activated. In the event the applied address is different than the defective address, a no match indication is generated. The match indication activates the RED signal and the no match indication activates the STD signal, according to the timing of a "mimic" circuit (312). The mimic circuit (312) emulates the slowest resolution of the match/no match indication by the modified NOR-type decoder (310).
摘要翻译：公开了一种用于产生标准列存取信号（STD）和冗余列存取信号（RED）的冗余电路（300）。修改的NOR型解码器（310）确定所施加的地址是否与缺陷地址相同。在应用的地址与缺陷地址相同的情况下，匹配指示被激活。在应用地址与有缺陷地址不同的情况下，产生不匹配指示。匹配指示激活RED信号，并且根据“模拟”电路（312）的定时，不匹配指示激活STD信号。仿真电路（312）模拟经修改的NOR型解码器（310）的匹配/不匹配指示的最慢分辨率。

23. 发明授权

US6067260A Synchronous semiconductor memory device having redundant circuit of high repair efficiency and allowing high speed access 失效
标题翻译：同步半导体存储器件具有高修复效率和允许高速访问的冗余电路
公开(公告)号：US6067260A
公开(公告)日：2000-05-23
申请号：US195194
申请日：1998-11-18
申请人： Tsukasa Ooishi , Shigeki Tomishima , Hiroki Shimano
发明人： Tsukasa Ooishi , Shigeki Tomishima , Hiroki Shimano
IPC分类号： G11C11/407 , G11C11/401 , G11C11/409 , G11C29/00 , G11C29/04 , G11C7/00 , G11C8/00
CPC分类号： G11C29/808 , G11C29/842
摘要： A redundant memory cell column region provided corresponding to respective regular memory cell column regions can have data read and written through a sub I/O line pair and a main I/O line pair independent to those of the regular memory cell column region. Also, one redundant memory cell column region can be connected to a corresponding global I/O line pair G-I/O of any of the regular memory cell column regions via a multiplexer to be replaceable of any of two regular memory cell column regions.
摘要翻译：与相应的常规存储单元列区相对应地提供的冗余存储单元列区域可以通过与常规存储单元列区域独立的子I / O线对和主I / O线对读取和写入数据。此外，一个冗余存储单元列区域可以经由多路复用器连接到任何常规存储器单元列区域的对应全局I / O线对G-I / O，以可替换两个常规存储器单元列区域中的任一个。

24. 发明授权

US5640365A Semiconductor memory device with a decoding peripheral circuit for improving the operation frequency 失效
标题翻译：具有用于提高操作频率的解码外围电路的半导体存储器件
公开(公告)号：US5640365A
公开(公告)日：1997-06-17
申请号：US524630
申请日：1995-09-07
申请人： Keniti Imamiya , Shinji Miyano , Katsuhiko Sato , Tomoaki Yabe
发明人： Keniti Imamiya , Shinji Miyano , Katsuhiko Sato , Tomoaki Yabe
IPC分类号： G11C7/22 , G11C8/18 , G11C29/00 , G11C7/00
CPC分类号： G11C29/842 , G11C29/844 , G11C7/22 , G11C8/18
摘要： A data register that stores the data corresponding to the selected memory cell in a memory cell array is provided near the memory cell array. A decoder that selects the data from the data register starts decoding in response to an address signal accessing the memory cells in synchronization with a clock signal determining the operation period. In the first half of an operation period of the clock signal, the decoder outputs a signal in response to a signal corresponding to the address signal determined in the preceding operation period. According to the output of the decoder, the data register is selected. In the latter half of the operation period, a signal corresponding to a new address signal for the next operation period is transferred to the decoder. By doing this, the output control signal in the decoder is caused to synchronize with a signal driving an address signal, enabling the proper address to be selected without fail.
摘要翻译：在存储单元阵列附近提供将存储单元阵列中与所选存储单元对应的数据存储的数据寄存器。从数据寄存器中选择数据的解码器响应于与确定操作周期的时钟信号同步地访问存储器单元的地址信号开始解码。在时钟信号的运算周期的前半部分中，解码器响应于与前一操作周期中确定的地址信号对应的信号输出信号。根据解码器的输出，选择数据寄存器。在操作期间的后半部分，将与下一个操作期间的新的地址信号对应的信号传送到解码器。通过这样做，使解码器中的输出控制信号与驱动地址信号的信号同步，使得能够选择合适的地址。

25. 发明授权

US5442587A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5442587A
公开(公告)日：1995-08-15
申请号：US68669
申请日：1993-05-28
申请人： Masaaki Kuwagata , Yuji Watanabe
发明人： Masaaki Kuwagata , Yuji Watanabe
IPC分类号： G06F11/20 , G11C11/401 , G11C11/407 , G11C11/408 , G11C29/00 , G11C29/04 , H01L27/10 , G11C7/00
CPC分类号： G11C29/789 , G11C29/842
摘要： In the memory cell provided with spare cells and normal cells, the time required to discriminate the spare column address from the normal column address or vice versa can be reduced, and thereby a high speed memory access can be realized. When an address is given from the counter to a memory circuit having the spare address and the normal address, before the counter outputs an address to the memory circuit, the spare/normal discriminating circuit acquires previously the address outputted from the counter and discriminates whether the address is the spare address or the normal address. On the basis of this discrimination, the select circuits switch the address to be applied from the select circuits to the memory circuit from the normal address to the spare address or vice versa.
摘要翻译：在设置有备用单元和正常单元的存储单元中，可以减少区分备用列地址与正常列地址或反之亦然的时间，从而可以实现高速存储器存取。当从计数器向具有备用地址和通常地址的存储器电路提供地址时，在计数器向存储器电路输出地址之前，备用/正常识别电路预先获取从计数器输出的地址，地址是备用地址或正常地址。基于这种鉴别，选择电路将要从选择电路施加的地址从存储器电路从正常地址切换到备用地址，反之亦然。

26. 发明授权

US4803656A Semiconductor memory device having redundancy circuit portion 失效
标题翻译：具有冗余电路部分的半导体存储器件
公开(公告)号：US4803656A
公开(公告)日：1989-02-07
申请号：US28463
申请日：1987-03-20
申请人： Yoshihiro Takemae
发明人： Yoshihiro Takemae
IPC分类号： G11C29/00 , G11C29/04 , G11C7/00
CPC分类号： G11C29/842
摘要： A semiconductor memory device including a regular memory cell array in which a plurality of word lines and bit lines are provided, and a plurality of memory cells are arranged at each intersection of the word lines and bit lines; a redundancy memory cell array in which one or more word lines and bit lines are provided, and a plurality of memory cells are arranged at each intersection of the word lines and bit lines; a control unit for generating a first control signal; a unit for programming defective address bits corresponding to a defective memory cell existing in the regular memory cell array; a unit for comparing each logic or input address bits with each of the defective address bits; a first switch for generating a second control signal when at least one logic of the input address bits does not coincide with the corresponding defective address bit and for supplying a third control signal to a predetermined word line or bit line belonging to the redundancy memory cell array without generating the second control signal when each logic of the input address bits coincides with each of the defective address bits; a unit for identifying whether or not the defective address bits are programmed in the programming means; and a second switch for supplying the second control signal input from the first switch to a selected word line or bit line belonging to the regular memory cell array when the identifying unit indicates that the defective address bits are programmed in the programming means and for supplying the first control signal input from the control unit to the selected word line or bit line when the identifying unit indicates that the defective address bits are not programmed in the programming unit.
摘要翻译：一种半导体存储器件，包括其中提供多个字线和位线的常规存储单元阵列，并且多个存储单元被布置在字线和位线的每个交叉处; 提供一个或多个字线和位线的冗余存储单元阵列，并且在字线和位线的每个交叉处布置多个存储单元; 用于产生第一控制信号的控制单元; 用于编程对应于存在于常规存储单元阵列中的有缺陷的存储单元的缺陷地址位的单元; 用于将每个逻辑或输入地址位与每个缺陷地址位进行比较的单元; 第一开关，当输入地址位的至少一个逻辑与对应的缺陷地址位不一致时，用于产生第二控制信号，并且用于将第三控制信号提供给属于冗余存储单元阵列的预定字线或位线当输入地址位的每个逻辑与每个缺陷地址位一致时，不产生第二控制信号; 用于识别在编程装置中是否对缺陷地址位进行编程的单元; 以及第二开关，用于当识别单元指示在编程装置中对缺陷地址位进行编程时，将从第一开关输入的第二控制信号提供给属于常规存储单元阵列的选定字线或位线，当所述识别单元指示所述缺陷地址位未被编程在所述编程单元中时，从所述控制单元输入到所选择的字线或位线的第一控制信号。

27. 发明授权

US4796233A Bipolar-transistor type semiconductor memory device having redundancy configuration 失效
标题翻译：具有冗余配置的双极晶体管型半导体存储器件
公开(公告)号：US4796233A
公开(公告)日：1989-01-03
申请号：US788587
申请日：1985-10-17
申请人： Tomoharu Awaya , Isao Fukushi
发明人： Tomoharu Awaya , Isao Fukushi
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/84 , G11C29/842
摘要： A bipolar-transistor type semiconductor memory device including a normal memory cell array, redundancy memory cell array, a redundancy driving circuit, and a redundancy address decision circuit. When the redundancy address decision circuit determines that the input address coincides with the address of a defective circuit portion, the redundancy driving circuit is driven to enable the redundancy memory cell array instead of the normal memory cell array.
摘要翻译：包括正常存储单元阵列，冗余存储单元阵列，冗余驱动电路和冗余地址判定电路的双极晶体管型半导体存储器件。当冗余地址判定电路确定输入地址与故障电路部分的地址一致时，驱动冗余驱动电路以使冗余存储单元阵列代替正常存储单元阵列。

28. 发明授权

US4723227A Redundant type memory circuit with an improved clock generator 失效
标题翻译：具有改进的时钟发生器的冗余型存储电路
公开(公告)号：US4723227A
公开(公告)日：1988-02-02
申请号：US607050
申请日：1984-05-04
申请人： Tatsunori Murotani
发明人： Tatsunori Murotani
IPC分类号： G11C11/407 , G11C11/401 , G11C29/00 , G11C29/04 , G11C8/00
CPC分类号： G11C29/842
摘要： A redundant type memory circuit having a normal memory cell array, a first decoder circuit for operatively accessing normal array, a redundant memory cell array, a second decoder circuit for accessing the redundant array, and a programmable timing control circuit for enabling the first decoder circuit at a first delay period when no faulty cell exists in the normal array and at a second longer delay period when a faulty cell exists in the normal array.
摘要翻译：具有正常存储单元阵列的冗余型存储器电路，用于可操作地访问正常阵列的第一解码器电路，冗余存储单元阵列，用于访问冗余阵列的第二解码器电路以及用于使能第一解码器电路的可编程定时控制电路在正常阵列中没有故障单元存在的第一延迟时段和在正常阵列中存在故障单元的第二较长延迟周期时。

29. 发明授权

US09711243B1 Redundancy schemes for memory 有权
公开(公告)号：US09711243B1
公开(公告)日：2017-07-18
申请号：US15188876
申请日：2016-06-21
申请人： ARM Limited
发明人： Vivek Nautiyal , Fakhruddin Ali Bohra , Satinderjit Singh , Jitendra Dasani , Shri Sagar Dwivedi
IPC分类号： G11C11/00 , G11C29/00 , G11C11/412 , G11C11/417
CPC分类号： G11C29/76 , G11C11/417 , G11C29/12 , G11C29/842 , G11C29/846
摘要： Various implementations described herein are directed to an integrated circuit. The integrated circuit may include a first memory cell array disposed in a first area of the integrated circuit. The first memory cell array includes first memory cells. The integrated circuit may include a second memory cell array disposed in a second area of the integrated circuit that is different than the first area. The second memory cell array includes redundant memory cells that are separate from the first memory cells.

30. 发明申请

US20100246299A1 SEMICONDUCTOR STORAGE DEVICE AND REDUNDANCY METHOD 审中-公开
标题翻译：半导体存储设备和冗余方法
公开(公告)号：US20100246299A1
公开(公告)日：2010-09-30
申请号：US12559925
申请日：2009-09-15
申请人： Takayuki IWAI , Mariko IIZUKA
发明人： Takayuki IWAI , Mariko IIZUKA
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/84 , G11C29/842
摘要： A semiconductor storage device includes a normal area that contains a plurality of memory cells and a redundancy area that contains a plurality of memory cells. The semiconductor storage device further includes a delaying unit that changes, between a first mode in which both the normal area and the redundancy area are used and a second mode in which only the normal area is used without use of the redundancy area, a timing for issuing a cell-array control signal for selecting a memory cell from among the memory cells used in a corresponding mode.
摘要翻译：半导体存储装置包括包含多个存储单元的正常区域和包含多个存储单元的冗余区域。半导体存储装置还包括延迟单元，其在使用正常区域和冗余区域的第一模式和仅使用正常区域而不使用冗余区域的第二模式之间进行改变，定时发出用于从相应模式中使用的存储单元中选择存储单元的单元阵列控制信号。

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