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21. 发明授权

US09620226B1 Data retention charge loss and read disturb compensation in solid-state data storage systems 有权
公开(公告)号：US09620226B1
公开(公告)日：2017-04-11
申请号：US14929080
申请日：2015-10-30
申请人： Western Digital Technologies, Inc.
发明人： Dale Charles Main , Abhilash Ravi Kashyap
IPC分类号： G11C11/34 , G11C16/14 , G11C16/08 , G11C16/26 , G11C16/34
CPC分类号： G11C29/50004 , G06F3/0604 , G06F3/0647 , G06F3/0652 , G06F3/0679 , G11C11/5628 , G11C11/5642 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/16 , G11C16/26 , G11C16/28 , G11C16/3427 , G11C29/50016 , G11C2029/5004
摘要： A data storage device includes a solid-state memory including memory cells and a controller configured to perform a first programming scheme that programs a first subset of the cells to a first voltage state using a first target voltage, programs a second subset to a second voltage state using a second target voltage higher than the first target voltage, programs a third subset to a third voltage state using a third target voltage higher than the second target voltage, and programs a fourth subset to a fourth voltage state using a fourth target voltage higher than the third target voltage. A difference in voltage between the fourth target voltage and the third target voltage may be greater or less than a difference in voltage between the third target voltage and the second target voltage and/or a difference in voltage between the second target voltage and the first target voltage.

22. 发明授权

US09607954B2 Method of manufacturing semiconductor device and semiconductor device 有权
公开(公告)号：US09607954B2
公开(公告)日：2017-03-28
申请号：US15154954
申请日：2016-05-14
申请人： Renesas Electronics Corporation
发明人： Akira Yajima
IPC分类号： H01L21/66 , H01L23/00
CPC分类号： H01L24/02 , G11C29/06 , G11C29/50016 , G11C29/56016 , G11C2029/0403 , G11C2029/5602 , H01L22/14 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/45 , H01L24/48 , H01L24/92 , H01L24/94 , H01L2224/02311 , H01L2224/02313 , H01L2224/02331 , H01L2224/0239 , H01L2224/0345 , H01L2224/03462 , H01L2224/03464 , H01L2224/03831 , H01L2224/0392 , H01L2224/0401 , H01L2224/04042 , H01L2224/04073 , H01L2224/05541 , H01L2224/05548 , H01L2224/05569 , H01L2224/0558 , H01L2224/05664 , H01L2224/05669 , H01L2224/05673 , H01L2224/05676 , H01L2224/05678 , H01L2224/119 , H01L2224/13022 , H01L2224/131 , H01L2224/45147 , H01L2224/48463 , H01L2224/92 , H01L2224/94 , H01L2924/1437 , H01L2924/1438 , H01L2924/01029 , H01L2924/014 , H01L2924/01028 , H01L2924/00014 , H01L2224/0231 , H01L2224/03 , H01L2224/11 , H01L2224/03848 , H01L22/10 , H01L22/12 , H01L21/78 , H01L2924/00012
摘要： Object is to prevent a coupling failure between a rewiring and a coupling member for coupling to outside. A passivation film and a first polyimide film are formed so as to cover a wiring layer. A first opening portion is formed in the first polyimide film. A rewiring is formed on the first polyimide film so as to be coupled to the wiring layer via the first opening portion. A second polyimide film that covers the rewiring and has a second opening portion communicated with the rewiring is formed. A palladium film is formed as a barrier film by sputtering on a portion of the surface of the rewiring at which the second opening portion exists. A solder ball is coupled to the palladium film.

23. 发明授权

US09564202B2 Increased refresh interval and energy efficiency in a DRAM 有权
标题翻译：增加DRAM中的刷新间隔和能量效率
公开(公告)号：US09564202B2
公开(公告)日：2017-02-07
申请号：US14371180
申请日：2013-09-01
申请人： EMPIRE TECHNOLOGY DEVELOPMENT LLC
发明人： Yan Solihin
IPC分类号： G06F12/14 , G11C11/4074 , G11C29/02 , G11C29/44 , G11C29/50 , G11C11/406 , G11C7/10 , G11C29/00 , G11C11/40
CPC分类号： G06F11/004 , G11C7/1072 , G11C11/40 , G11C11/406 , G11C11/40618 , G11C11/4074 , G11C29/023 , G11C29/028 , G11C29/44 , G11C29/50016 , G11C29/783 , G11C2211/4061
摘要： Techniques described herein generally include methods and systems related to designing and operating a DRAM device that has significantly reduced refresh energy use. A method for designing a DRAM optimizes or otherwise improves the DRAM for energy efficiency based on a measured or predicted failure probability of memory cells in the DRAM. The DRAM may be configured to operate at an increased refresh interval, thereby reducing DRAM refresh energy but causing a predictable portion of the memory cells in the DRAM to leak electrical energy too quickly to retain data. The DRAM is further configured with a selected number of spare memory cells for replacing the “leaky” memory cells, so that operation of the DRAM at the increased refresh interval may result in little or no reduction in capacity of the DRAM.
摘要翻译：本文描述的技术通常包括与设计和操作具有显着降低的刷新能量使用的DRAM设备相关的方法和系统。基于DRAM中的存储器单元的测量或预测的故障概率，用于设计DRAM的方法优化或以其他方式改进用于能量效率的DRAM。 DRAM可以被配置为以增加的刷新间隔进行操作，从而减少DRAM刷新能量，但是使DRAM中的存储器单元的可预测部分太快地泄漏电能以保留数据。 DRAM还配置有用于替换“泄漏”存储单元的选定数量的备用存储器单元，使得在增加的刷新间隔的DRAM的操作可能导致DRAM的容量很少或不降低。

24. 发明申请

US20160357458A1 DYNAMIC WINDOW TO IMPROVE NAND ENDURANCE 审中-公开
标题翻译：动态窗口提高NAND耐久性
公开(公告)号：US20160357458A1
公开(公告)日：2016-12-08
申请号：US15076963
申请日：2016-03-22
申请人： Intel Corporation
发明人： Kiran Pangal , Ravi J. Kumar
IPC分类号： G06F3/06 , G11C16/14 , G11C29/52 , G11C11/56 , G06F11/20 , G06F11/10 , G11C16/34 , G11C16/26
CPC分类号： G06F3/0616 , G06F3/064 , G06F3/0653 , G06F3/0659 , G06F3/0679 , G06F11/1068 , G06F11/2094 , G11C11/5635 , G11C11/5642 , G11C16/00 , G11C16/14 , G11C16/26 , G11C16/3436 , G11C29/021 , G11C29/026 , G11C29/028 , G11C29/50016 , G11C29/52 , G11C2029/0401
摘要： Methods and apparatus to provide dynamic window to improve NAND (Not And) memory endurance are described. In one embodiment, a program-erase window associated with a NAND memory device is dynamically varied by starting with a higher erase verify (TEV) voltage and lowering the TEV voltage with subsequent cycles over a life of the NAND memory device based on a current cycle count value. Alternatively, the program-erase window is dynamically varied by starting with a higher erase verify (PV) voltage and erase verify (TEV) voltage and lowering the PV and TEV voltages with subsequent cycles over a life of the NAND memory device based on the current cycle count value. Other embodiments are also disclosed and claimed.
摘要翻译：描述了提供动态窗口以提高NAND（Not And）存储器耐久性的方法和装置。在一个实施例中，与NAND存储器件相关联的编程擦除窗口通过从较高的擦除验证（TEV）电压开始并基于当前周期在NAND存储器件的使用寿命内随后的周期降低TEV电压而动态地改变计数值。或者，通过以更高的擦除验证（PV）电压和擦除验证（TEV）电压开始，并且基于当前的NAND存储器件的使用寿命期间的随后的周期来降低PV和TEV电压，编程擦除窗口被动态变化循环计数值。还公开并要求保护其他实施例。

25. 发明申请

US20160307620A1 SYSTEMS AND METHODS TO REFRESH DRAM BASED ON TEMPERATURE AND BASED ON CALIBRATION DATA 有权
标题翻译：基于温度和基于校准数据刷新DRAM的系统和方法
公开(公告)号：US20160307620A1
公开(公告)日：2016-10-20
申请号：US14690204
申请日：2015-04-17
申请人： QUALCOMM Incorporated
发明人： Dexter Tamio Chun , Jung Pill Kim , Yanru Li
IPC分类号： G11C11/406 , G11C29/42 , G11C29/36 , G11C11/4096
CPC分类号： G11C11/40626 , G11C7/1006 , G11C11/4076 , G11C11/4096 , G11C29/023 , G11C29/028 , G11C29/36 , G11C29/42 , G11C29/50016 , G11C2207/2245 , G11C2211/4062
摘要： A system and method of refreshing dynamic random access memory (DRAM) are disclosed. A device includes a DRAM, a bus, and a system-on-chip (SOC) coupled via the bus to the DRAM. The SOC is configured to refresh the DRAM at a particular refresh rate based on a temperature of the DRAM and based on calibration data determined based on one or more calibration tests performed while the SOC is coupled to the DRAM.
摘要翻译：公开了一种刷新动态随机存取存储器（DRAM）的系统和方法。一种器件包括通过总线耦合到DRAM的DRAM，总线和片上系统（SOC）。 SOC被配置为基于DRAM的温度以基于在SOC耦合到DRAM时执行的一个或多个校准测试确定的校准数据以特定刷新速率刷新DRAM。

26. 发明申请

US20160293238A1 SEMICONDUCTOR INTEGRATED CIRCUIT INCLUDING CAS LATENCY SETTING CIRCUIT 审中-公开
标题翻译：半导体集成电路，包括CAS LATENCY设置电路
公开(公告)号：US20160293238A1
公开(公告)日：2016-10-06
申请号：US15180268
申请日：2016-06-13
申请人： SK hynix Inc.
发明人： Seong Jun LEE
IPC分类号： G11C7/22 , G11C29/00 , G11C7/10
CPC分类号： G11C7/222 , G11C7/10 , G11C7/106 , G11C11/40 , G11C29/00 , G11C29/023 , G11C29/028 , G11C29/04 , G11C29/50016 , G11C2207/2272
摘要： A semiconductor memory apparatus includes a CAS latency setting circuit configured to change an initially-set CAS latency value in response to control signal pulses which are sequentially applied, during a test mode without changing settings of a mode register set during each test.
摘要翻译：半导体存储装置包括：CAS等待时间设定电路，被配置为响应于在测试模式期间顺序地施加的控制信号脉冲来改变初始设置的CAS等待时间值，而不改变在每次测试期间设置的模式寄存器的设置。

27. 发明授权

US09425207B2 Memory device with different memory film diameters in the same laminate level 有权
标题翻译：具有不同记忆膜直径的存储器件处于相同层压板级
公开(公告)号：US09425207B2
公开(公告)日：2016-08-23
申请号：US14521577
申请日：2014-10-23
申请人： Kabushiki Kaisha Toshiba
发明人： Naoki Yasuda
IPC分类号： H01L27/115 , G11C16/14 , G11C11/56 , G11C8/14 , G11C16/04 , G11C29/50
CPC分类号： H01L27/11582 , G11C8/14 , G11C11/5671 , G11C16/04 , G11C16/14 , G11C29/50016 , H01L27/11565
摘要： According to one embodiment, a non-volatile memory device includes first electrodes, at least one first semiconductor layer, a first memory film, second electrodes, at least one second semiconductor layer, and a second memory film. The first electrodes are stacked in a first direction. The one first semiconductor layer extends in the first direction through the first electrodes. The first memory film is provided between each of the first electrodes and the one first semiconductor layer. The second electrodes are stacked in the first direction and provided together with the first electrodes in a second direction orthogonal to the first direction. The one second semiconductor layer extends in the first direction through the second electrodes. The second memory film is provided between each of the second electrodes and the one second semiconductor layer. An outer diameter of the first memory film is larger than that of the second memory film.
摘要翻译：根据一个实施例，非易失性存储器件包括第一电极，至少一个第一半导体层，第一存储膜，第二电极，至少一个第二半导体层和第二存储膜。第一电极沿第一方向堆叠。一个第一半导体层沿第一方向延伸穿过第一电极。第一记忆膜设置在每个第一电极和一个第一半导体层之间。第二电极在第一方向上堆叠并且在与第一方向正交的第二方向上与第一电极一起设置。第一半导体层沿第一方向延伸穿过第二电极。第二记忆膜设置在每个第二电极和一个第二半导体层之间。第一存储膜的外径大于第二存储膜的外径。

28. 发明授权

US09424888B2 Signal timing alignment based on a common data strobe in memory devices configured for stacked arrangements 有权
公开(公告)号：US09424888B2
公开(公告)日：2016-08-23
申请号：US14506964
申请日：2014-10-06
申请人： III HOLDINGS 2, LLC
发明人： Michael C. Stephens, Jr.
IPC分类号： G11C5/02 , G11C11/406 , G11C5/06 , G11C5/04 , G11C29/02 , G11C29/50 , G11C5/14 , G11C16/30 , G11C11/401 , G11C7/10 , G11C15/00 , G11C29/44 , G11C7/22
CPC分类号： G11C11/4076 , G11C5/02 , G11C5/04 , G11C5/06 , G11C5/063 , G11C5/14 , G11C5/147 , G11C7/10 , G11C7/106 , G11C7/22 , G11C7/222 , G11C11/401 , G11C11/406 , G11C11/40615 , G11C11/40622 , G11C11/4093 , G11C11/4094 , G11C15/00 , G11C16/30 , G11C29/023 , G11C29/028 , G11C29/50016 , G11C2029/4402 , G11C2211/4061 , G11C2211/4067 , G11C2213/71 , H01L2224/16145
摘要： Disclosed are various embodiments related to stacked memory devices, such as DRAMs, SRAMs, EEPROMs, ReRAMs, and CAMs. For example, stack position identifiers (SPIDs) are assigned or otherwise determined, and are used by each memory device to make a number of adjustments. In one embodiment, a self-refresh rate of a DRAM is adjusted based on the SPID of that device. In another embodiment, a latency of a DRAM or SRAM is adjusted based on the SPID. In another embodiment, internal regulation signals are shared with other devices via TSVs. In another embodiment, adjustments to internally regulated signals are made based on the SPID of a particular device. In another embodiment, serially connected signals can be controlled based on a chip SPID (e.g., an even or odd stack position), and whether the signal is an upstream or a downstream type of signal.

29. 发明申请

US20160240269A1 Screening for Data Retention Loss in Ferroelectric Memories 有权
标题翻译：铁电存储器中数据保留损耗的筛选
公开(公告)号：US20160240269A1
公开(公告)日：2016-08-18
申请号：US14857873
申请日：2015-09-18
申请人： Texas Instruments Incorporated
发明人： Carl Z. Zhou , John A. Rodriguez , Richard A. Bailey
IPC分类号： G11C29/50 , G11C11/22
CPC分类号： G11C29/50016 , G11C11/2275 , G11C29/50008
摘要： A data retention reliability screen of integrated circuits including ferroelectric random access memory (FRAM) arrays. Sampled groups of cells in the FRAM array are tested at various reference voltage levels, after programming to a high polarization capacitance data state and a relaxation time at an elevated temperature. Fail bit counts of the sample groups at the various reference voltage levels are used to derive a test reference voltage, against which all of the FRAM cells in the integrated circuit are then tested after preconditioning (i.e., programming) and another relaxation interval at the elevated temperature, to determine those cells in the integrated circuit that are vulnerable to long-term data retention failure.
摘要翻译：包括铁电随机存取存储器（FRAM）阵列的集成电路的数据保留可靠性屏幕。在编程到高极化电容数据状态和升高温度下的弛豫时间之后，以各种参考电压电平测试FRAM阵列中的采样组的单元。使用各种参考电压电平下的采样组的故障位计数来导出测试参考电压，然后在预处理（即编程）之后测试集成电路中的所有FRAM单元，并在升高的其他弛豫区间以确定集成电路中易受长期数据保留故障影响的单元。

30. 发明申请

US20160240253A1 Screening for Later Life Stuck Bits in Ferroelectric Memories 有权
标题翻译：筛选铁电记忆中的后期生活扣留位
公开(公告)号：US20160240253A1
公开(公告)日：2016-08-18
申请号：US15019698
申请日：2016-02-09
申请人： Texas Instruments Incorporated
发明人： Carl Z. Zhou , John A. Rodriguez , Richard A. Bailey
IPC分类号： G11C14/00 , G11C11/22
CPC分类号： G11C14/0072 , G11C11/221 , G11C11/2273 , G11C29/50016 , G11C29/70
摘要： A reliability screen of integrated circuits including ferroelectric random access memory (FRAM) arrays for stuck bits. The FRAM devices are subjected to a high temperature bake in wafer form. A “shmoo” of the reference voltage is performed, at an elevated temperature, for each device to identify a first reference voltage at which a first cell in the device fails a read of its low polarization capacitance data state, and a second reference voltage at which a selected number of cells in the device fail the read. The slope of the line between the first and second reference voltages, in the cumulative fail bit count versus reference voltage plane, is compared with a slope limit to determine whether any stuck bits are present in the device.
摘要翻译：集成电路的可靠性屏幕，包括用于卡住位的铁电随机存取存储器（FRAM）阵列。对FRAM器件进行晶片形式的高温烘烤。在升高的温度下，对于每个器件执行参考电压的“shmoo”，以识别第一参考电压，在该第一参考电压下，器件中的第一单元不能读取其低极化电容数据状态，第二参考电压设备中选定数量的单元格读取失败。将累积故障位计数与参考电压平面中的第一和第二参考电压之间的线的斜率与斜率限制进行比较，以确定器件中是否存在任何卡位。

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