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21. 发明授权

US09634014B2 Method of making a programmable cell and structure thereof 有权
公开(公告)号：US09634014B2
公开(公告)日：2017-04-25
申请号：US14692552
申请日：2015-04-21
申请人： Broadcom Corporation
发明人： Qintao Zhang , Akira Ito
IPC分类号： H01L27/112 , H01L21/28 , H01L23/525 , H01L21/265 , H01L29/78 , H01L29/66 , H01L21/311 , H01L29/423 , H01L21/3115
CPC分类号： H01L27/11206 , G11C17/146 , H01L21/26586 , H01L21/28158 , H01L21/31111 , H01L21/31155 , H01L23/5252 , H01L29/42368 , H01L29/66795 , H01L29/7851
摘要： A programmable cell includes a split gate structure. The split gate structure includes a thin gate dielectric region and a thick gate dielectric region disposed below a gate conductor. A thickness of the thick oxide region is more than a thickness of the thin oxide region. The programmable cell can be fabricated using angle doping to dope an area associated with the thin dielectric region.

22. 发明授权

US09312009B2 Non-volatile memory and associated memory array, row decoder, column decoder, write buffer and sensing circuit 有权
标题翻译：非易失性存储器和相关存储器阵列，行解码器，列解码器，写缓冲器和感测电路
公开(公告)号：US09312009B2
公开(公告)日：2016-04-12
申请号：US14592477
申请日：2015-01-08
申请人： eMemory Technology Inc.
发明人： Tzu-Neng Lai , Chih-Hao Huang
IPC分类号： G11C7/00 , G11C16/08 , G11C17/16 , G11C17/18 , H01L27/112 , G11C16/10 , G11C16/26 , G11C17/04 , G11C17/08 , H01L23/528 , H01L27/06 , H01L29/10 , H01L29/49 , H01L29/93 , H01L27/115 , H03K3/356 , H01L23/525
CPC分类号： G11C16/08 , G11C16/10 , G11C16/26 , G11C17/04 , G11C17/08 , G11C17/146 , G11C17/16 , G11C17/18 , G11C29/76 , H01L23/5252 , H01L23/528 , H01L27/0629 , H01L27/11206 , H01L27/11524 , H01L29/1079 , H01L29/4916 , H01L29/93 , H01L2924/0002 , H03K3/356182 , H01L2924/00
摘要： A non-volatile memory includes a memory array, a row decoder, a column decoder, a write buffer and a sensing circuit. The column decoder includes a programming decoder and a reading decoder. The programming decoder is connected with n bit lines of the memory array. The reading decoder is connected with the n bit lines. During a program cycle, a programming control signal set is activated. Consequently, the programming decoder determines a selected memory cell, and a cell current generated by the selected memory cell flows to the write buffer through the programming decoder and a programming data line. During a read cycle, a reading control signal set is activated. Consequently, the reading decoder determines the selected memory cell, and the cell current generated by the selected memory cell flows to the sensing circuit through the reading decoder and a reading data line.
摘要翻译：非易失性存储器包括存储器阵列，行解码器，列解码器，写缓冲器和感测电路。列解码器包括编程解码器和读取解码器。编程解码器与存储器阵列的n位线连接。读取解码器与n位线连接。在编程周期中，编程控制信号组被激活。因此，编程解码器确定所选择的存储单元，并且由所选择的存储器单元产生的单元电流通过编程解码器和编程数据线流向写入缓冲器。在读取周期期间，读取控制信号组被激活。因此，读取解码器确定所选择的存储单元，并且由选择的存储单元产生的单元电流通过读取解码器和读取数据线流到感测电路。

23. 发明申请

US20160071582A1 Method and System of programmable resistive devices with Read Capability Using a Low Supply Voltage 有权
标题翻译：使用低电源电压的可读能力的可编程电阻器件的方法和系统
公开(公告)号：US20160071582A1
公开(公告)日：2016-03-10
申请号：US14940012
申请日：2015-11-12
申请人： Shine C. Chung
发明人： Shine C. Chung
IPC分类号： G11C13/00 , G11C11/16 , G11C17/16
CPC分类号： G11C13/004 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/0023 , G11C13/0028 , G11C13/003 , G11C13/0069 , G11C17/146 , G11C17/16 , G11C17/165 , G11C17/18 , G11C29/027 , G11C2013/0045 , G11C2013/0073 , G11C2213/72 , G11C2213/74 , H01L27/224 , H01L27/228 , H01L27/2409 , H01L27/2436 , H01L29/785 , H01L45/06 , H01L45/1233 , H01L45/144
摘要： A Programmable Resistive Device (PRD) memory that can be read under low voltage is disclosed. The PRD includes at least one Programmable Resistive Element (PRE) having one end coupled to a first supply voltage line and the other end coupled to at least one selector and at least one read selector. The read selector includes at least one read source line (SLR) and/or one read enable (ENR) coupled to a second and/or a third supply voltage lines, respectively. The read selector includes at least one MOS device built by core logic device. The PRE in the at least one PRD cells can be configured to be readable by applying voltages to the first, second, and/or the third voltage supply lines to thereby sense the PRE resistance to a logic state. The programmable resistive element can have at least one element in an OTP, MTP, floating gate device, anti-fuse, or emerging memory such as PCRAM, RRAM, or MRAM, etc.
摘要翻译：公开了一种可在低电压下读取的可编程电阻器件（PRD）存储器。 PRD包括至少一个可编程电阻元件（PRE），其中一端耦合到第一电源电压线，另一端耦合到至少一个选择器和至少一个读取选择器。读取选择器分别包括耦合到第二和/或第三电源电压线的至少一个读取源极线（SLR）和/或一个读取使能（ENR）。读选择器包括由核心逻辑器件构建的至少一个MOS器件。至少一个PRD单元中的PRE可以被配置为通过向第一，第二和/或第三电压供应线施加电压来读取，从而将PRE电阻感测到逻辑状态。可编程电阻元件可以在OTP，MTP，浮动栅极器件，反熔丝或新兴存储器（例如PCRAM，RRAM或MRAM等）中具有至少一个元件。

24. 发明授权

US09269459B2 Mechanisms for built-in self test and repair for memory devices 有权
标题翻译：用于内存自检和修复内存设备的机制
公开(公告)号：US09269459B2
公开(公告)日：2016-02-23
申请号：US14585726
申请日：2014-12-30
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Saman M. I. Adham , Chao-Jung Hung
IPC分类号： G11C29/00 , G11C29/44 , G11C17/14 , G11C17/16
CPC分类号： G11C29/4401 , G11C17/146 , G11C17/16 , G11C29/785 , G11C2029/4402
摘要： A method of storing repair data of a memory array in a one-time programming memory (OTPM) includes performing a first test and repair of the memory array using a built-in self-test-and-repair (BISTR) module to determine first repair data. The method includes loading the first repair data in a repair memory and in a duplicated repair memory of the BISTR module. The method includes performing a second test and repair to determine second repair data. The method includes storing the second repair data in the repair memory of the BISTR module and in the repair memory of the memory array. The method includes processing the repair data in the repair memory and the duplicated repair memory of the BISTR module. The method includes storing the output of the logic gate in the repair memory of the memory array. The method includes storing content of the repair memory in the OTPM.
摘要翻译：一种将一个存储器阵列的修复数据存储在一次性编程存储器（OTPM）中的方法包括使用内置的自检和修复（BISTR）模块执行存储器阵列的第一次测试和修复，以确定第一修复数据。该方法包括将第一修复数据加载到BISTR模块的修复存储器和复制修复存储器中。该方法包括执行第二次测试和修复以确定第二修复数据。该方法包括将第二修复数据存储在BISTR模块的修复存储器和存储器阵列的修复存储器中。该方法包括处理修复存储器中的修复数据和BISTR模块的重复修复存储器。该方法包括将逻辑门的输出存储在存储器阵列的修复存储器中。该方法包括将修复存储器的内容存储在OTPM中。

25. 发明授权

US09269454B1 Counter using one-time-programmable memory 有权
标题翻译：计数器使用一次性可编程存储器
公开(公告)号：US09269454B1
公开(公告)日：2016-02-23
申请号：US14558818
申请日：2014-12-03
申请人： Winbond Electronics Corporation
发明人： Uri Kaluzhny , David Harbater
IPC分类号： G11C17/00 , G11C17/18 , G11C17/16
CPC分类号： G11C17/18 , G11C17/146
摘要： A method, including receiving a sequence of events to be counted. The method further includes, in response to each event, setting a respective bit in a memory that consists of multiple words organized in tiers, such that a number of set bits in the memory is indicative of a count of the received events, and such that each set bit in a first tier corresponds to a respective word in a second tier and is indicative of whether the corresponding word is fully populated with set bits.
摘要翻译：一种方法，包括接收要计数的事件序列。该方法还包括响应于每个事件，设置由层级组织的多个单词组成的存储器中的相应位，使得存储器中的设置位的数量表示接收到的事件的计数，并且使得第一层中的每个集合位对应于第二层中的相应字，并且指示相应的字是否用设置位完全填充。

26. 发明申请

US20160013199A1 HIGHLY SCALABLE SINGLE-POLY NON-VOLATILE MEMORY CELL 有权
标题翻译：高可扩展的单波非易失性存储单元
公开(公告)号：US20160013199A1
公开(公告)日：2016-01-14
申请号：US14719342
申请日：2015-05-22
申请人： eMemory Technology Inc.
发明人： Te-Hsun Hsu , Chun-Hsiao Li , Hsuen-Wei Chen
IPC分类号： H01L27/115
CPC分类号： G11C16/08 , G11C16/10 , G11C16/26 , G11C17/04 , G11C17/08 , G11C17/146 , G11C17/16 , G11C17/18 , G11C29/76 , H01L23/5252 , H01L23/528 , H01L27/0629 , H01L27/11206 , H01L27/11524 , H01L29/1079 , H01L29/4916 , H01L29/93 , H01L2924/0002 , H03K3/356182 , H01L2924/00
摘要： A nonvolatile memory cell includes a semiconductor substrate, a first OD region, a second OD region, an isolation region separating the first OD region from the second OD region, a PMOS select transistor disposed on the first OD region, and a PMOS floating gate transistor serially connected to the select transistor and disposed on the first OD region. The PMOS floating gate transistor includes a floating gate overlying the first OD region. A memory P well is disposed in the semiconductor substrate. A memory N well is disposed in the memory P well. The memory P well overlaps with the first OD region and the second OD region. The memory P well has a junction depth that is deeper than a trench depth of the isolation region. The memory N well has a junction depth that is shallower than the trench depth of the isolation region.
摘要翻译：非易失性存储单元包括半导体衬底，第一OD区域，第二OD区域，将第一OD区域与第二OD区域分离的隔离区域，设置在第一OD区域上的PMOS选择晶体管和PMOS浮栅晶体管串联连接到选择晶体管并且设置在第一OD区域上。 PMOS浮栅晶体管包括覆盖第一OD区的浮置栅极。存储器P阱设置在半导体衬底中。存储器N阱设置在存储器P中。存储器P与第一OD区和第二OD区很好地重叠。存储器P阱具有比隔离区域的沟槽深度更深的结深度。存储器N阱具有比隔离区的沟槽深度浅的结深度。

27. 发明申请

US20160005492A1 OTP READ SENSOR ARCHITECTURE WITH IMPROVED RELIABILITY 有权
标题翻译： OTP阅读传感器架构具有改进的可靠性
公开(公告)号：US20160005492A1
公开(公告)日：2016-01-07
申请号：US14789666
申请日：2015-07-01
申请人： Texas Instruments Incorporated
发明人： Mandy Barsilai
IPC分类号： G11C17/08
CPC分类号： G11C17/08 , G11C17/146 , G11C17/18 , G11C29/027
摘要： Circuits and methods for reading an OTP memory cell with improved reliability. To read a first OTP memory cell, a first current amount generated by a second, programmed, OTP memory cell is received. A second current amount generated by a third, unprogrammed, OTP memory cell is received. Current generated by the first OTP memory cell is sunk. The amount of current sunk from the first OTP memory cell is equal to a sum of a third current amount that is proportional to the first current amount plus a fourth current amount that is proportional to the second current amount. While sinking said current from the first OTP memory cell a voltage at a current output of the first OTP memory cell is compared to a threshold voltage.
摘要翻译：读取OTP存储单元的可靠性提高的电路和方法。为了读取第一OTP存储单元，接收由第二编程的OTP存储单元产生的第一电流量。接收由第三未编程的OTP存储器单元产生的第二电流量。由第一个OTP存储单元产生的电流是沉没的。从第一OTP存储单元沉没的电流量等于与第一电流量加上与第二电流量成比例的第四电流量成比例的第三电流量的和。当从第一OTP存储单元吸收电流时，将第一OTP存储单元的电流输出端的电压与阈值电压进行比较。

28. 发明申请

US20150070963A1 MEMORY PROGRAMMING METHOD AND APPARATUS 有权
标题翻译：记忆编程方法和装置
公开(公告)号：US20150070963A1
公开(公告)日：2015-03-12
申请号：US14338426
申请日：2014-07-23
申请人： MAGNACHIP SEMICONDUCTOR, LTD.
发明人： Beomseon RYU , Taeil YUN , Daeyoung YOO
IPC分类号： G11C17/16 , G11C17/18
CPC分类号： G11C17/16 , G11C13/0069 , G11C17/146 , G11C17/18 , G11C29/027 , G11C2013/0076 , G11C2013/0083 , G11C2029/4402
摘要： The memory programming apparatus includes a memory reader configured to read a read data in a plurality of cells related with an address of a programmable memory; and a memory writer configured to record a write data on the plurality of cells to compare the write data with the read data, to generate a re-writing pattern, and to correct at least one mismatch cell among the plurality of cells. Accordingly, it may be possible to reduce a programming processing time and to increase a yield rate.
摘要翻译：存储器编程装置包括存储器读取器，其被配置为读取与可编程存储器的地址相关的多个单元中的读取数据; 以及存储器写入器，被配置为在所述多个单元上记录写入数据，以将所述写入数据与所述读取的数据进行比较，以生成重新写入模式，并且校正所述多个单元中的至少一个错误单元。因此，可以减少编程处理时间并提高成品率。

29. 发明授权

US08885384B2 Mask-programmed read-only memory with reserved space 有权
标题翻译：带保留空间的掩码编程只读存储器
公开(公告)号：US08885384B2
公开(公告)日：2014-11-11
申请号：US13846928
申请日：2013-03-18
申请人： ChengDu HaiCan IP Technology LLC
发明人： Guobiao Zhang
IPC分类号： G11C17/10
CPC分类号： G06F12/0246 , G11C17/10 , G11C17/146 , H01L21/8221 , H01L27/0207 , H01L27/0688 , H01L27/1021 , H01L27/112 , H01L27/11253
摘要： The present invention discloses a mask-ROM with reserved space (mask-ROMRS). For small content revision, the present invention salvages the original data-mask by writing the data-pattern of new content into a reserved mask-region which originally has no data-pattern.
摘要翻译：本发明公开了一种具有保留空间的掩模ROM（mask-ROMRS）。对于小内容修订，本发明通过将新内容的数据模式写入原始不具有数据模式的保留掩码区域来挽救原始数据掩码。

30. 发明授权

US08854877B2 Nonvolatile semiconductor memory device and method of reusing same 有权
标题翻译：非易失性半导体存储器件及其使用方法
公开(公告)号：US08854877B2
公开(公告)日：2014-10-07
申请号：US13179206
申请日：2011-07-08
申请人： Yuji Nagashima , Bunsho Kuramori , Hiroyuki Tanikawa
发明人： Yuji Nagashima , Bunsho Kuramori , Hiroyuki Tanikawa
IPC分类号： G11C11/34 , G11C8/06 , G11C16/10 , G11C16/04 , G11C29/00 , G11C17/14
CPC分类号： G11C8/06 , G11C16/0475 , G11C16/0491 , G11C16/10 , G11C17/146 , G11C29/883
摘要： A nonvolatile semiconductor memory device and a method of reusing the same that allow a good use of the semiconductor device without degrading characteristics even when reused. The semiconductor memory device comprises information holding means for holding information that indicates an operation mode of said memory cell array, a decoder for generating, to said memory cell array, a selection signal to designate at least a read address of said memory cell array in accordance with an address signal that comprises plural bits; and mode setting means for fixing a logical value of at least one bit of said plural bits of said address signal in accordance with the information held by said information holding means, and supplying said address signal, on which fixing of the logical value is effected, to said decoder.
摘要翻译：一种非易失性半导体存储器件及其再利用方法，即使在再利用时也能够良好地利用半导体器件而不劣化特性。半导体存储器件包括用于保存指示所述存储单元阵列的操作模式的信息的信息保持装置，用于向所述存储单元阵列生成至少指定所述存储单元阵列的读地址的选择信号的解码器具有包括多个位的地址信号; 以及模式设定装置，用于根据由所述信息保持装置保存的信息来固定所述地址信号的所述多个比特的至少一个比特的逻辑值，并且提供实现该逻辑值固定的所述地址信号，到所述解码器。

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