专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明授权

US09196374B1 System and method for detecting data stored in multi-bit memory cells 有权
标题翻译：用于检测存储在多位存储单元中的数据的系统和方法
公开(公告)号：US09196374B1
公开(公告)日：2015-11-24
申请号：US14492418
申请日：2014-09-22
申请人： Marvell International Ltd.
发明人： Xueshi Yang , Zining Wu
IPC分类号： G11C16/04 , G11C16/26 , G11C11/56
CPC分类号： G11C16/26 , G11C11/5642 , G11C16/3436
摘要： A control module for a memory system including a plurality of multi-bit memory cells. The control module includes a read module configured to receive, from a first storage region of a first memory cell of the plurality of multi-bit memory cells, a first signal, and generate a second signal based on the first signal. A signal detection module is configured to determine distances between the second signal and respective estimates of a plurality of noiseless signals associated with the first memory cell. The noiseless signals correspond to a combination of an ideal signal and an interference signal. The signal detection module is further configured to determine, from the estimates of the plurality of noiseless signals, a noiseless signal that matches most closely to the second signal. A data conversion module is configured to detect data stored in the first storage region based on the noiseless signal that matches most closely to the second signal.
摘要翻译：一种用于包括多个多位存储器单元的存储器系统的控制模块。控制模块包括读取模块，其被配置为从多个多位存储器单元中的第一存储单元的第一存储区域接收第一信号，并且基于第一信号生成第二信号。信号检测模块被配置为确定第二信号与与第一存储器单元相关联的多个无噪声信号的相应估计之间的距离。无噪声信号对应于理想信号和干扰信号的组合。信号检测模块还被配置为从多个无噪声信号的估计中确定与第二信号最紧密匹配的无噪声信号。数据转换模块被配置为基于与第二信号最紧密匹配的无噪声信号来检测存储在第一存储区域中的数据。

22. 发明授权

US09183924B2 Methods of operating nonvolatile memory devices that support efficient error detection 有权
公开(公告)号：US09183924B2
公开(公告)日：2015-11-10
申请号：US14712939
申请日：2015-05-15
申请人： Samsung Electronics Co., Ltd.
发明人： Ji-Sang Lee , Moosung Kim , Kihwan Choi
IPC分类号： G11C29/00 , G11C11/56 , G11C16/34 , G06F11/10
CPC分类号： G11C11/5635 , G06F11/1048 , G11C11/5628 , G11C11/5642 , G11C16/02 , G11C16/0483 , G11C16/3413 , G11C16/3436 , G11C16/3454 , G11C29/04 , G11C2029/0411 , G11C2211/5621
摘要： Methods of operating nonvolatile memory devices may include identifying one or more multi-bit nonvolatile memory cells in a nonvolatile memory device that have undergone unintentional programming from an erased state to an at least partially programmed state. Errors generated during an operation to program a first plurality of multi-bit nonvolatile memory cells may be detected by performing a plurality of reading operations to generate error detection data and then decoding the error detection data to identify specific cells having errors. A programmed first plurality of multi-bit nonvolatile memory cells and a force-bit data vector, which was modified during the program operation, may be read to support error detection. This data, along with data read from a page buffer associated with the first plurality of multi-bit nonvolatile memory cells, may then be decoded to identify which of the first plurality of multi-bit nonvolatile memory cells are unintentionally programmed cells.

23. 发明申请

US20150227459A1 STORAGE CONTROL APPARATUS, STORAGE APPARATUS, INFORMATION PROCESSING SYSTEM AND PROCESSING METHOD THEREFOR 审中-公开
标题翻译：存储控制装置，存储装置，信息处理系统及其处理方法
公开(公告)号：US20150227459A1
公开(公告)日：2015-08-13
申请号：US14692233
申请日：2015-04-21
申请人： Sony Corporation
发明人： Naohiro Adachi , Keiichi Tsutsui , Kenichi Nakanishi , Hideaki Okubo , Yasushi Fujinami , Ken Ishii
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F9/3004 , G06F12/0238 , G06F2212/7201 , G06F2212/7202 , G06F2212/7203 , G06F2212/7205 , G06F2212/7207 , G06F2212/7209 , G06F2212/7211 , G11C13/0069 , G11C13/0097 , G11C16/3436 , G11C2013/0076
摘要： A storage control apparatus includes: a pre-processing-execution determining block for determining whether or not either one of an erase operation and a program operation is to be executed as pre-processing in a write operation to be carried out on a predetermined data area to serve as a write-operation object; and a pre-read processing block for reading out pre-read data from the data area prior to the write operation if a result of the determination indicates that the pre-processing is to be executed. The apparatus further includes a bit operating block for carrying out: the pre-processing and one of the erase and program operations which is not the pre-processing as post-processing if a result of the determination indicates that the pre-processing is to be executed; and the post-processing without carrying out the pre-processing if a determination result indicates that the pre-processing is not to be executed.
摘要翻译：存储控制装置包括：预处理执行确定块，用于确定是否将在执行预定数据区域的写入操作中执行擦除操作和编程操作中的任一个作为预处理作为写操作对象; 以及如果所述确定的结果指示要执行所述预处理，则在所述写入操作之前从所述数据区读出预读数据的预读处理块。该装置还包括一个位操作块，用于执行预处理和擦除和编程操作中的一个，如果确定的结果指示预处理将被作为后处理，则不是预处理作为后处理执行以及如果确定结果指示不执行预处理，则不进行预处理的后处理。

24. 发明申请

US20150205665A1 ECC METHOD FOR FLASH MEMORY 有权
标题翻译：闪存存储器的ECC方法
公开(公告)号：US20150205665A1
公开(公告)日：2015-07-23
申请号：US14158613
申请日：2014-01-17
申请人： Macronix International Co., Ltd.
发明人： Nai-Ping Kuo , Shih-Chang Huang , Chin-Hung Chang , Ken-Hui Chen , Kuen-Long Chang , Chun-Hsiung Hung
IPC分类号： G06F11/10
CPC分类号： G06F11/1048 , G06F2212/1036 , G11C16/3436
摘要： A method of operating a memory storing data sets, and ECCs for the data sets is provided. The method includes when writing new data in a data set, computing and storing an ECC, if a number of addressable segments storing the new data and data previously programmed in the data set includes at least a predetermined number of addressable segments. The method includes storing indications for whether to enable or disable use of the ECCs, using the ECC and a first additional ECC bit derived from the ECC. The method includes reading from a data set an extended ECC including an ECC and a first additional ECC bit derived from the ECC, and enabling or disabling use of the ECC according to the indications stored for the data set. The method includes enabling use of ECCs for blank data sets, using the indications and a second additional ECC bit.
摘要翻译：提供了一种操作存储数据集的存储器和数据集的ECC的方法。如果存储新数据的多个可寻址段和先前在数据集中编程的数据包括至少预定数量的可寻址段，则该方法包括在将新数据写入数据集时，计算和存储ECC。该方法包括使用ECC和从ECC导出的第一附加ECC比特来存储是否启用或禁止使用ECC的指示。该方法包括从数据集读取包括ECC的扩展ECC和从ECC导出的第一附加ECC位，以及根据为数据集存储的指示启用或禁用ECC的使用。该方法包括使用所述指示和第二附加ECC位使能ECC空白数据集。

25. 发明授权

US09070463B2 Flash memory module for realizing high reliability 有权
标题翻译：闪存模块，实现高可靠性
公开(公告)号：US09070463B2
公开(公告)日：2015-06-30
申请号：US14560313
申请日：2014-12-04
申请人： Hitachi, Ltd.
发明人： Akifumi Suzuki
IPC分类号： G11C16/04 , G11C16/16
CPC分类号： G11C16/16 , G06F3/0616 , G06F3/0619 , G06F3/064 , G06F3/0679 , G06F12/0246 , G06F2212/7211 , G11C16/3431 , G11C16/3436
摘要： A flash memory module may include a plurality of flash memory chips. The memory chips may include one or more blocks. Each block may be a unit of erasing data. A flash controller may be coupled to the plurality of flash memory chips. The flash controller may program data to block and erase data from a block. The flash controller may manage a recent programming time for each of the plurality of blocks. The flash controller may erase data stored in a block for which an elapsed programming time is larger than a first value.
摘要翻译：闪存模块可以包括多个闪存芯片。存储器芯片可以包括一个或多个块。每个块可以是擦除数据的单元。闪存控制器可以耦合到多个闪存芯片。闪存控制器可以编程数据来阻止和擦除块中的数据。闪存控制器可以管理多个块中的每一个的最近的编程时间。闪存控制器可以擦除存储在经过编程时间大于第一值的块中的数据。

26. 发明授权

US09058162B2 Storage control apparatus, storage apparatus, information processing system and processing method therefor 有权
标题翻译：存储控制装置，存储装置，信息处理系统及其处理方法
公开(公告)号：US09058162B2
公开(公告)日：2015-06-16
申请号：US13780774
申请日：2013-02-28
申请人： Sony Corporation
发明人： Naohiro Adachi , Keiichi Tsutsui , Kenichi Nakanishi , Hideaki Okubo , Yasushi Fujinami , Ken Ishii
IPC分类号： G06F12/00 , G06F9/30 , G06F12/02 , G11C16/34 , G11C13/00
CPC分类号： G06F12/0246 , G06F9/3004 , G06F12/0238 , G06F2212/7201 , G06F2212/7202 , G06F2212/7203 , G06F2212/7205 , G06F2212/7207 , G06F2212/7209 , G06F2212/7211 , G11C13/0069 , G11C13/0097 , G11C16/3436 , G11C2013/0076
摘要： A storage control apparatus includes: a pre-processing-execution determining block for determining whether or not either one of an erase operation and a program operation is to be executed as pre-processing in a write operation to be carried out on a predetermined data area to serve as a write-operation object; and a pre-read processing block for reading out pre-read data from the data area prior to the write operation if a result of the determination indicates that the pre-processing is to be executed. The apparatus further includes a bit operating block for carrying out: the pre-processing and one of the erase and program operations which is not the pre-processing as post-processing if a result of the determination indicates that the pre-processing is to be executed; and the post-processing without carrying out the pre-processing if a determination result indicates that the pre-processing is not to be executed.
摘要翻译：存储控制装置包括：预处理执行确定块，用于确定是否将在执行预定数据区域的写入操作中执行擦除操作和编程操作中的任一个作为预处理作为写操作对象; 以及如果所述确定的结果指示要执行所述预处理，则在所述写入操作之前从所述数据区读出预读数据的预读处理块。该装置还包括一个位操作块，用于执行预处理和擦除和编程操作中的一个，如果确定的结果指示预处理将被作为后处理，则不是预处理作为后处理执行以及如果确定结果指示不执行预处理，则不进行预处理的后处理。

27. 发明授权

US09030875B2 Non-volatile memory device 有权
标题翻译：非易失性存储器件
公开(公告)号：US09030875B2
公开(公告)日：2015-05-12
申请号：US13716511
申请日：2012-12-17
申请人： Samsung Electronics Co., Ltd.
发明人： Tomohisa Miyamoto
IPC分类号： G11C16/04 , G11C16/06 , G11C16/08 , G11C16/26 , G11C16/32 , G11C16/34
CPC分类号： G11C16/06 , G11C16/0483 , G11C16/08 , G11C16/26 , G11C16/32 , G11C16/3436
摘要： A non-volatile memory device includes a memory cell array in which a plurality of bit lines intersect a plurality of word lines and a non-volatile memory cell is disposed at each intersection, a page buffer which is provided for each bit line and which includes a latch configured to store data to be written to a memory cell connected to a word line selected from among the plurality of word lines or data read from the memory cell, and a control circuit configured to control a data input time from the bit line to the page buffer and a data detection time of the latch according to a voltage level of a common source line connected to sources of the respective bit lines during an operation of reading data from the memory cell.
摘要翻译：非易失性存储器件包括存储单元阵列，其中多个位线与多条字线相交，并且非易失性存储单元设置在每个交叉点处，为每个位线提供的页缓冲器，其包括锁存器，被配置为存储要写入到与从所述多个字线中选择的字线连接的存储器单元或从所述存储单元读取的数据的数据;以及控制电路，被配置为控制从所述位线到所述页缓冲器和所述锁存器的数据检测时间根据在从所述存储器单元读取数据的操作期间连接到各个位线的源的公共源极线的电压电平。

28. 发明授权

US09019773B2 Nonvolatile memory device and method of operating the same 有权
标题翻译：非易失存储器件及其操作方法
公开(公告)号：US09019773B2
公开(公告)日：2015-04-28
申请号：US14037582
申请日：2013-09-26
申请人： Samsung Electronics Co., Ltd.
发明人： Il Han Park , Seung-Bum Kim
IPC分类号： G11C16/04 , G11C16/06 , G11C16/34 , G11C11/56
CPC分类号： G11C16/3445 , G11C11/5635 , G11C16/0483 , G11C16/3436 , G11C16/344
摘要： A nonvolatile memory device includes a memory cell array and control logic. The memory cell array includes multiple memory blocks, each memory block including memory cells connected to word lines and bit lines. The control logic is configured to perform an erase operation in which an erase voltage is applied to a memory block of the multiple memory blocks to erase the memory cells of the memory block, and in which an erase verification voltage is applied a selected word line of the memory block to verify respective erase states of memory cells connected to the selected word line. The control logic is further configured to apply a read voltage to the selected word line to extract erase state information of the memory cells, and to control a level of the erase verification voltage based on the erase state information.
摘要翻译：非易失性存储器件包括存储单元阵列和控制逻辑。存储单元阵列包括多个存储块，每个存储块包括连接到字线和位线的存储器单元。控制逻辑被配置为执行擦除操作，其中擦除电压被施加到多个存储块的存储块以擦除存储块的存储单元，并且其中擦除验证电压被施加到所选择的字线所述存储块用于验证连接到所选字线的存储单元的相应擦除状态。控制逻辑还被配置为向所选字线施加读取电压以提取存储器单元的擦除状态信息，并且基于擦除状态信息来控制擦除验证电压的电平。

29. 发明授权

US09013925B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US09013925B2
公开(公告)日：2015-04-21
申请号：US13947196
申请日：2013-07-22
申请人： Elite Semiconductor Memory Technology Inc.
发明人： Cheng-Hung Tsai
IPC分类号： G11C16/06 , G11C16/24 , G11C16/30 , G11C16/00 , G11C16/12
CPC分类号： G11C16/24 , G11C16/00 , G11C16/0483 , G11C16/12 , G11C16/30 , G11C16/3436
摘要： A nonvolatile semiconductor memory device comprises a memory cell array, a staircase voltage generator, and a decode and level shift circuit. The memory cell array comprises a plurality of memory cells and a plurality of bit lines coupled to the plurality of memory cells. The staircase voltage generator generates a staircase voltage having a staircase waveform that varies in at least two steps. The decode and level shift circuit selects one of said plurality of bit lines and applies the staircase voltage as a program voltage to the selected bit line.
摘要翻译：非易失性半导体存储器件包括存储单元阵列，阶梯电压发生器和解码和电平移位电路。存储单元阵列包括耦合到多个存储单元的多个存储单元和多个位线。楼梯电压发生器产生具有至少两个步骤变化的阶梯波形的阶梯电压。解码和电平移位电路选择所述多个位线之一，并将阶梯电压作为编程电压施加到所选择的位线。

30. 发明授权

US08934302B2 Nonvolatile memory having stacked structure and related method of operation 有权
标题翻译：具有层叠结构和相关操作方法的非易失性存储器
公开(公告)号：US08934302B2
公开(公告)日：2015-01-13
申请号：US13600327
申请日：2012-08-31
申请人： Dong-Hun Kwak
发明人： Dong-Hun Kwak
IPC分类号： G11C16/04 , G11C7/00 , H01L27/115
CPC分类号： G11C7/00 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/3436 , G11C16/3454 , G11C2211/5621 , G11C2211/5644 , G11C2211/5648 , H01L27/1157 , H01L27/11582
摘要： A method is provided for operating a nonvolatile memory comprising memory cells stacked on a substrate. The method comprises counting a number of program loops performed in a first program operation of selected memory cells connected to a selected wordline, and controlling an increment of a program voltage between successive program loops of a second program operation of the selected memory cells according to the counted number.
摘要翻译：提供一种用于操作包括堆叠在基板上的存储单元的非易失性存储器的方法。该方法包括对连接到所选字线的选定存储单元的第一编程操作中执行的程序循环数进行计数，以及根据所选择的存储单元的所选存储单元的第二程序操作的连续程序循环之间的程序电压的增量计数

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式