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1. 发明授权

US10528287B2 Memory, memory controller, storage apparatus, information processing system, and control method for tracking erase count and rewrite cycles of memory pages 有权
公开(公告)号：US10528287B2
公开(公告)日：2020-01-07
申请号：US15761590
申请日：2016-07-01
申请人： SONY CORPORATION
发明人： Kenichi Nakanishi
IPC分类号： G06F3/06 , G06F12/16 , G11C13/00 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/34 , G11C11/16 , G11C7/10
摘要： To enhance accuracy of counting the number of rewrite cycles in a non-volatile memory that is overwritable. A memory outputs erase information that is information regarding whether or not erase processing has been performed in writing of data in units of pages each including a plurality of memory cells in which data is rewritten by program processing of shifting a memory cell that stores data from an initial state to a data-storing state and erase processing of shifting the memory cell from the data-storing state to the initial state. The number of rewrite cycles is counted by updating the number of rewrite cycles on a basis of the output erase information.

2. 发明授权

US10481971B2 Encoding device, memory controller, communication system, and encoding method 有权
公开(公告)号：US10481971B2
公开(公告)日：2019-11-19
申请号：US15736079
申请日：2016-04-15
申请人： Sony Corporation
发明人： Tatsuo Shinbashi , Kenichi Nakanishi , Yasushi Fujinami , Hiroyuki Iwaki , Ken Ishii , Hideaki Okubo
IPC分类号： G06F11/10 , G06F12/16 , H03M13/09 , H03M13/35 , H03M13/00 , G11C16/02 , G11C16/06 , H03M13/15 , H03M13/19
摘要： A data holding characteristic of a memory cell is improved in a memory system in which data is encoded and written to a memory cell.A first candidate parity generation unit generates, as a first candidate parity, a parity for detecting an error in an information section in which a predetermined value is assigned in a predetermined variable area. A second candidate parity generation unit generates, as a second candidate parity, a parity for detecting an error in the information section in which a value different from the predetermined value is assigned in the predetermined variable area. A selection unit selects a parity that satisfies a predetermined condition from among the first and second candidate parities as a selection parity. An output unit outputs a codeword constituted by the information section corresponding to the selection parity and the selection parity.

3. 发明申请

US20170293513A1 MEMORY CONTROLLER, MEMORY SYSTEM, AND MEMORY CONTROLLER CONTROL METHOD 审中-公开
公开(公告)号：US20170293513A1
公开(公告)日：2017-10-12
申请号：US15507413
申请日：2015-07-22
申请人： Sony Corporation
发明人： Tatsuo Shinbashi , Keiichi Tsutsui , Hideaki Okubo , Lui Sakai , Kenichi Nakanishi , Yasushi Fujinami
IPC分类号： G06F11/00 , G06F3/06 , G11C29/52
CPC分类号： G06F11/004 , G06F3/0619 , G06F12/16 , G11C7/1006 , G11C13/00 , G11C16/3418 , G11C16/3427 , G11C16/3431 , G11C29/52
摘要： [Object] To sufficiently reduce frequency of error occurrence in memory cells.[Solution] A reading unit reads read data from a memory cell, the read data including an information bit and reversal information for determining whether or not the information bit has been reversed. In addition, an error detection/correction unit detects the presence or absence of an error in the information bit and corrects the error. A data reversing unit reverses the information bit that has the error corrected and the reversal information. Furthermore, a writing unit writes the reversed information bit and the reversed reversal information in the memory cell.

4. 发明授权

US08898541B2 Storage controller, storage device, information processing system, and storage controlling method 有权
标题翻译：存储控制器，存储设备，信息处理系统和存储控制方法
公开(公告)号：US08898541B2
公开(公告)日：2014-11-25
申请号：US13675768
申请日：2012-11-13
申请人： Sony Corporation
发明人： Hideaki Okubo , Keiichi Tsutsui , Kenichi Nakanishi , Yasushi Fujinami , Makiko Yamamoto , Naohiro Adachi
IPC分类号： G11C29/00
CPC分类号： G06F11/1048
摘要： A storage controller includes an error correcting code managing portion, an address managing portion and an error correcting portion. The error correcting code managing portion manages a correspondence relationship between predetermined plural pieces of unit data, and a second error code corresponding to the plural pieces of unit data every entry when plural pieces of unit data and a second error correcting code are stored in a storage portion. The address managing portion manages a correspondence relationship between logical addresses and the entries in the error correcting code managing portion. The error correcting portion acquires the entry in the error correction managing portion corresponding to the logical address as an object of read from the address managing portion, and carries out error correction based on the plural pieces of unit data managed in the entry concerned, and the second error correcting code.
摘要翻译：存储控制器包括纠错码管理部分，地址管理部分和纠错部分。当多个单位数据和第二纠错码存储在存储器中时，纠错码管理部分管理预定的多个单位数据与每个条目对应的多个单位数据的第二错误代码的对应关系一部分。地址管理部分管理逻辑地址与纠错码管理部分中的条目之间的对应关系。纠错部从地址管理部获取与作为读取对象的逻辑地址相对应的纠错管理部中的条目，并根据在该条目中管理的多个单位数据进行纠错，第二个纠错码。

5. 发明申请

US20140229761A1 STORAGE CONTROLLER, STORAGE DEVICE, INFORMATION PROCESSING SYSTEM, AND STORAGE CONTROL METHOD 有权
标题翻译：存储控制器，存储设备，信息处理系统和存储控制方法
公开(公告)号：US20140229761A1
公开(公告)日：2014-08-14
申请号：US14167616
申请日：2014-01-29
申请人： SONY CORPORATION
发明人： Hideaki Okubo , Kenichi Nakanishi , Yasushi Fujinami , Keiichi Tsutsui
IPC分类号： G06F11/07 , G11C11/406
CPC分类号： G06F11/073 , G06F11/076 , G06F11/1004 , G06F11/1016 , G06F11/1044 , G06F11/1048 , G11C16/3431
摘要： A storage controller includes: an error information management section configured to manage information in a plurality of addresses of a memory; and a refresh object determination section configured to determine a refresh object address in the memory based on the error information.
摘要翻译：存储控制器包括：错误信息管理部件，被配置为管理存储器的多个地址中的信息; 以及刷新对象确定部，被配置为基于所述错误信息来确定所述存储器中的刷新对象地址。

6. 发明申请

US20130262737A1 STORAGE CONTROL APPARATUS , STORAGE APPARATUS, INFORMATION PROCESSING SYSTEM AND PROCESSING METHOD 审中-公开
标题翻译：存储控制装置，存储装置，信息处理系统和处理方法
公开(公告)号：US20130262737A1
公开(公告)日：2013-10-03
申请号：US13781260
申请日：2013-02-28
申请人： SONY CORPORATION
发明人： Kenichi Nakanishi , Keiichi Tsutsui , Yasushi Fujinami , Naohiro Adachi , Ken Ishii , Hideaki Okubo , Tatsuo Shinbashi
IPC分类号： G06F12/06
CPC分类号： G06F12/0623 , G06F12/06 , G06F12/0607
摘要： Disclosed herein is a storage control apparatus including: a command processing section configured to receive a command requesting accesses to a plurality of access units by specifying an address in a memory space including a plurality of banks; and an address generating section configured to generate an address of an access unit serving as an object of the accesses in a bank selected from the banks as a bank determined in advance for the specified address.
摘要翻译：这里公开了一种存储控制装置，包括：命令处理部，被配置为通过在包括多个存储体的存储空间中指定地址来接收请求对多个访问单元的访问的命令; 以及地址生成部，被配置为生成作为从所述存储体中选择的存储体中的访问对象的访问单元的地址作为对于所述指定地址预先确定的存储体。

7. 发明申请

US20130117632A1 STORAGE CONTROL APPARATUS 审中-公开
标题翻译：存储控制装置
公开(公告)号：US20130117632A1
公开(公告)日：2013-05-09
申请号：US13666738
申请日：2012-11-01
申请人： Sony Corporation
发明人： Yasushi Fujinami , Keiichi Tsutsui , Kenichi Nakanishi , Naohiro Adachi , Hideaki Okubo , Makiko Yamamoto
IPC分类号： H03M13/05
CPC分类号： G06F11/1012
摘要： Embodiments of the technology disclosed herein are intended to flexibly set the rules of attaching error correction codes to a group of data sequences stored in a memory. A storage control apparatus has an error correction code attachment rule hold block and an error correction portion. The error correction code attachment rule hold block holds the rules of attaching error correction codes to a group of data sequences stored in a memory by relating the rules with the data for each address of the group of data sequences. If an access occurs to the memory, the error correction portion executes error correction processing on a group of data sequences stored in the memory in accordance with the attachment rules related to the address at which the access occurred.
摘要翻译：本文公开的技术的实施例旨在灵活地设置将纠错码附加到存储在存储器中的一组数据序列的规则。存储控制装置具有纠错码附着规则保持块和纠错部。纠错码附着规则保持块通过将规则与数据序列组的每个地址的数据相关联，将纠错码附加到存储在存储器中的一组数据序列的规则。如果对存储器进行访问，则纠错部分根据与访问发生的地址相关的附件规则对存储在存储器中的一组数据序列进行纠错处理。

8. 发明授权

US11262936B2 Memory controller, storage device, information processing system, and memory control method 有权
公开(公告)号：US11262936B2
公开(公告)日：2022-03-01
申请号：US15768597
申请日：2016-07-27
申请人： SONY CORPORATION
发明人： Ken Ishii , Hiroyuki Iwaki , Kenichi Nakanishi , Yasushi Fujinami , Tatsuo Shinbashi
IPC分类号： G06F12/00 , G06F3/06 , G06F12/06
摘要： The write time is to be shortened in a storage device using memories that require different write times from each other, such as nonvolatile memories.
In a memory controller including a plurality of write request holding units and a selection unit, the write request holding units holds a write request with respect to each of a plurality of memory modules that require different write times from one another. The selection unit selects one of the plurality of write request holding units in accordance with memory state information indicating whether each of the plurality of memory modules is in a busy state, and causes outputting of the write request.

9. 发明申请

US20180143871A1 ENCODING DEVICE, MEMORY CONTROLLER, COMMUNICATION SYSTEM, AND ENCODING METHOD 审中-公开
公开(公告)号：US20180143871A1
公开(公告)日：2018-05-24
申请号：US15736079
申请日：2016-04-15
申请人： Sony Corporation
发明人： Tatsuo Shinbashi , Kenichi Nakanishi , Yasushi Fujinami , Hiroyuki Iwaki , Ken Ishii , Hideaki Okubo
IPC分类号： G06F11/10 , G06F12/16 , H03M13/15 , H03M13/09
CPC分类号： G06F11/10 , G06F11/1012 , G06F12/16 , G11C16/02 , G11C16/06 , H03M13/09 , H03M13/095 , H03M13/1515 , H03M13/152 , H03M13/19 , H03M13/35 , H03M13/611
摘要： A data holding characteristic of a memory cell is improved in a memory system in which data is encoded and written to a memory cell.A first candidate parity generation unit generates, as a first candidate parity, a parity for detecting an error in an information section in which a predetermined value is assigned in a predetermined variable area. A second candidate parity generation unit generates, as a second candidate parity, a parity for detecting an error in the information section in which a value different from the predetermined value is assigned in the predetermined variable area. A selection unit selects a parity that satisfies a predetermined condition from among the first and second candidate parities as a selection parity. An output unit outputs a codeword constituted by the information section corresponding to the selection parity and the selection parity.

10. 发明授权

US09978448B2 Memory controller, storage device, information processing system, and memory controlling method 有权
公开(公告)号：US09978448B2
公开(公告)日：2018-05-22
申请号：US15520263
申请日：2015-10-06
申请人： SONY CORPORATION
发明人： Kenichi Nakanishi
IPC分类号： G11C7/00 , G11C13/00 , G11C8/12 , G11C11/406
CPC分类号： G11C13/0069 , G06F12/16 , G11C8/12 , G11C11/406 , G11C13/0023 , G11C13/0026 , G11C13/003 , G11C13/0033 , G11C13/0035 , G11C13/0061 , G11C16/32 , G11C16/3418 , G11C16/349 , G11C29/42 , G11C29/52 , G11C2211/4061 , G11C2213/79 , G11C2213/82
摘要： To perform refresh without saving data, and prevent corruption of data in non-volatile memories. A number-of-write-operations information holding unit holds number-of-write-operations information, which is the number of write operations of a non-volatile memory to which access is made in units of pages which are divided by a page size. A determination unit determines whether or not refresh, which is reversing of values of all memory cells constituting the pages, is necessary on the basis of the held number-of-write-operations information. A write control unit further performs the refresh in addition to writing when the refresh is necessary on the basis of a result of the determination at a time of the writing with respect to the pages.

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