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21. 发明申请

US20140189304A1 BIT-LEVEL REGISTER FILE UPDATES IN EXTENSIBLE PROCESSOR ARCHITECTURE 有权
标题翻译：可扩展处理器架构中的双层级注册文件更新
公开(公告)号：US20140189304A1
公开(公告)日：2014-07-03
申请号：US13732155
申请日：2012-12-31
申请人： TENSILICA INC.
发明人： Fei Sun
IPC分类号： G06F9/30
CPC分类号： G06F9/30098 , G06F9/30018 , G06F9/30112 , G06F9/30141
摘要： This document discusses, among other things, systems and methods to receive an instruction to selectively update a value of one or more selected bits of a first register, to receive the one or more selected bits of the first register to be updated and one or more selected bits of the first register to remain unchanged, and to selectively update the value of the one or more selected bits of the first register using a first write port without receiving the value of the one or more selected bits of the first register. In an example, the value of the one or more selected bits of the first register can be updated without receiving the value of the first register, in certain applications, reducing the number of read ports required to update the value of the first register.
摘要翻译：本文件尤其涉及接收用于选择性地更新第一寄存器的一个或多个选定位的值的指令的系统和方法，以接收要更新的第一寄存器的一个或多个选定位，以及一个或多个第一寄存器的选择位保持不变，并且使用第一写入端口选择性地更新第一寄存器的一个或多个选定位的值，而不接收第一寄存器的一个或多个选择位的值。在一个示例中，在某些应用中，可以更新第一寄存器的一个或多个所选位的值，而不接收第一寄存器的值，从而减少更新第一寄存器的值所需的读端口数。

22. 发明申请

US20140115227A1 SELECTIVE COUPLING OF AN ADDRESS LINE TO AN ELEMENT BANK OF A VECTOR REGISTER FILE 有权
标题翻译：地址线的选择性耦合到矢量寄存器文件的元素银行
公开(公告)号：US20140115227A1
公开(公告)日：2014-04-24
申请号：US13654730
申请日：2012-10-18
申请人： QUALCOMM INCORPORATED
发明人： Ajay Anant Ingle , Marc M. Hoffman , Deepak Mathew
IPC分类号： G06F12/00
CPC分类号： G06F9/30141 , G06F9/30018 , G06F9/30036 , G06F9/30043 , G06F9/30109 , G06F9/3012
摘要： A method includes selectively coupling a first address line of a plurality of address lines and a second address line of the plurality of address lines to a first element bank of a plurality of element banks of a vector register file according to a selection pattern. The method also includes accessing data stored within the first element bank that is selectively addressed by the first address line via a single read port.
摘要翻译：一种方法包括根据选择模式将多个地址线的第一地址线和多个地址线的第二地址线选择性地耦合到向量寄存器堆的多个元素组的第一元素组。该方法还包括通过单个读取端口访问由第一地址线选择性寻址的存储在第一元素库内的数据。

23. 发明授权

US08645588B2 Pipelined serial ring bus 有权
标题翻译：流水线串联环形总线
公开(公告)号：US08645588B2
公开(公告)日：2014-02-04
申请号：US12916664
申请日：2010-11-01
申请人： Christopher D. Bryant , David Kaplan
发明人： Christopher D. Bryant , David Kaplan
IPC分类号： G06F3/00 , G06F13/00 , G06F15/00 , G06F15/76 , G06F11/00
CPC分类号： G06F9/30141 , G06F9/34 , G06F9/3867 , G06F13/4282
摘要： The present invention provides embodiments of an apparatus used to implement a pipelined serial ring bus. One embodiment of the apparatus includes one or more ring buses configured to communicatively couple registers associated with logical elements in a processor. The ring bus(s) are configured to concurrently convey information associated with a plurality of load or store operations.
摘要翻译：本发明提供了用于实现流水线串行环形总线的装置的实施例。该装置的一个实施例包括一个或多个环总线，其被配置为在处理器中通信地耦合与逻辑元件相关联的寄存器。环形总线被配置为同时传送与多个加载或存储操作相关联的信息。

24. 发明申请

US20140025929A1 MANAGING REGISTER PAIRING 有权
标题翻译：管理注册配对
公开(公告)号：US20140025929A1
公开(公告)日：2014-01-23
申请号：US13552109
申请日：2012-07-18
申请人： Jonathan D. Bradbury , Michael K. Gschwind
发明人： Jonathan D. Bradbury , Michael K. Gschwind
IPC分类号： G06F9/30
CPC分类号： G06F9/30112 , G06F9/30141 , G06F9/3838
摘要： Embodiments relate to reducing a number of read ports for register pairs. An aspect includes maintaining an active pairing indicator that is configured to have a first value or a second value. The first value indicates that the wide operand is stored in a wide register. The second value indicates that the wide operand is not stored in the wide register. The operand is read from either the wide register or a pair of registers based on the active pairing indicator. The active pairing indicator and the values of the set of wide registers are stored to a storage based on a request to store a register pairing status. A saved pairing indicator and saved values of the set of wide registers is loaded from the storage respectively into an active pairing register and wide registers.
摘要翻译：实施例涉及减少用于寄存器对的多个读端口。一个方面包括维持被配置为具有第一值或第二值的活动配对指示符。第一个值表示宽操作数存储在一个宽的寄存器中。第二个值表示宽操作数不存储在宽寄存器中。基于活动配对指示器，从宽寄存器或一对寄存器读取操作数。基于存储寄存器配对状态的请求，将活动配对指示符和宽寄存器组的值存储到存储器中。一组保存的配对指示器和一组宽寄存器的保存值分别从存储器加载到有源配对寄存器和宽寄存器中。

25. 发明申请

US20130290681A1 REGISTER FILE POWER SAVINGS 有权
标题翻译：注册文件节电
公开(公告)号：US20130290681A1
公开(公告)日：2013-10-31
申请号：US13460178
申请日：2012-04-30
申请人： James B. Keller , John H. Mylius , Conrado Blasco-Allue , Gerard R. Williams, III , Sandeep Gupta
发明人： James B. Keller , John H. Mylius , Conrado Blasco-Allue , Gerard R. Williams, III , Sandeep Gupta
IPC分类号： G06F9/30
CPC分类号： G06F9/30141 , G06F1/3234 , G06F9/30112 , G06F9/384
摘要： A system and method for efficiently reducing the power consumption of register file accesses. A processor is operable to execute instructions with two or more data types, each with an associated size and alignment. Data operands for a first data type use operand sizes equal to an entire width of a physical register within a physical register file. Data operands for a second data type use operand sizes less than an entire width of a physical register. Accesses of the physical register file for operands associated with a non-full-width data type do not access a full width of the physical registers. A given numerical value may be bypassed for the portion of the physical register that is not accessed.
摘要翻译：一种有效降低寄存器文件访问功耗的系统和方法。处理器可操作以执行具有两个或多个数据类型的指令，每个数据类型具有相关联的大小和对齐。第一种数据类型的数据操作数使用等于物理寄存器文件中物理寄存器的整个宽度的操作数大小。第二种数据类型的数据操作数使用小于物理寄存器整个宽度的操作数大小。访问与非全宽数据类型相关的操作数的物理寄存器文件不能访问物理寄存器的全部宽度。对于未访问的物理寄存器的部分，可以忽略给定的数值。

26. 发明申请

US20130262828A1 PROCESSOR AND METHOD FOR DRIVING THE SAME 有权
标题翻译：处理器及其驱动方法
公开(公告)号：US20130262828A1
公开(公告)日：2013-10-03
申请号：US13796063
申请日：2013-03-12
申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
发明人： Seiichi Yoneda
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , G06F1/32 , G06F1/3287 , G06F9/30083 , G06F9/30141 , G06F11/14 , G11C5/00 , Y02D10/171 , Y02D50/20
摘要： A low-power processor that does not easily malfunction is provided. Alternatively, a low-power processor having high processing speed is provided. Alternatively, a method for driving the processor is provided. In power gating, the processor performs part of data backup in parallel with arithmetic processing and performs part of data recovery in parallel with arithmetic processing. Such a driving method prevents a sharp increase in power consumption in a data backup period and a data recovery period and generation of instantaneous voltage drops and inhibits increases of the data backup period and the data recovery period.
摘要翻译：提供了一个不容易发生故障的低功耗处理器。或者，提供具有高处理速度的低功率处理器。或者，提供用于驱动处理器的方法。在电源门控中，处理器与算术处理并行执行部分数据备份，并与算术处理并行执行部分数据恢复。这种驱动方法防止数据备份期间和数据恢复期间的功率消耗急剧增加，并且产生瞬时电压下降并且阻止数据备份周期和数据恢复期间的增加。

27. 发明申请

US20130227249A1 Three-Dimensional Permute Unit for a Single-Instruction Multiple-Data Processor 审中-公开
标题翻译：单指令多数据处理器的三维许可单位
公开(公告)号：US20130227249A1
公开(公告)日：2013-08-29
申请号：US13775355
申请日：2013-02-25
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Harry Barowski , Tim Niggemeier
IPC分类号： G06F15/80
CPC分类号： G06F15/803 , G06F9/30032 , G06F9/30036 , G06F9/30109 , G06F9/30141 , G06F15/8053
摘要： A three-dimensional (3D) permute unit for a single-instruction-multiple-data stacked processor includes a first vector permute subunit and a second vector permute subunit. The first and second vector permute subunits are arranged in different layers of a 3D chip package. The vector permute subunits are each configured to process a portion of at least two input vectors. A first contact sub-field of the first vector permute subunit is configured to connect output ports of a first crossbar of the first vector permute subunit, holding an intermediate result of the first vector permute subunit, to a second contact sub-field of the second vector permute subunit. A first contact sub-field of the second vector permute subunit is configured to connect output ports of a first crossbar of the second vector permute subunit, holding an intermediate result of the second vector permute subunit, to a second contact sub-field of the first vector permute subunit.
摘要翻译：用于单指令多数据堆叠处理器的三维（3D）置换单元包括第一向量置换子单元和第二向量置换子单元。第一和第二矢量置换子单元布置在3D芯片封装的不同层中。向量置换子单元被配置为处理至少两个输入向量的一部分。第一矢量置换子单元的第一接触子场被配置为将保持第一矢量置换子单元的中间结果的第一矢量置换子单元的第一交叉开关的输出端口连接到第二矢量置换子单元的第二接触子场，载体置换亚基。第二矢量置换子单元的第一接触子场被配置为将保持第二矢量置换子单元的中间结果的第二矢量置换子单元的第一交叉开关的输出端口连接到第一矢量置换子单元的第一接触子场，载体置换亚基。

28. 发明申请

US20130173865A1 REGISTER FILE ORGANIZATION TO SHARE PROCESS CONTEXT FOR HETEROGENEOUS MULTIPLE PROCESSORS OR JOINT PROCESSOR 有权
标题翻译：注册文件组织分享异构多处理器或联合处理器的过程
公开(公告)号：US20130173865A1
公开(公告)日：2013-07-04
申请号：US13692744
申请日：2012-12-03
申请人： STMicroelectronics (Beijing) R&D Company Ltd. , STMicroelectronics, s.r.l.
发明人： YongQiang WU , PengFei ZHU , HongXia SUN , Elio GUIDETTI
IPC分类号： G06F12/08
CPC分类号： G06F12/0802 , G06F9/30098 , G06F9/3012 , G06F9/30141
摘要： A register file organization is used to support multiple accesses from more than one processor or pipeline. This shared register file is organized for a multiple processor device that includes a high performance (HP) and a low power (LP) core. The shared register file includes separate HP and LP storage units coupled to separate HP and LP write and read ports.
摘要翻译：注册文件组织用于支持来自多个处理器或管道的多个访问。该共享寄存器文件针对包含高性能（HP）和低功耗（LP）内核的多处理器设备进行组织。共享寄存器文件包括单独的HP和LP存储单元，耦合到单独的HP和LP写入和读取端口。

29. 发明授权

US08447931B1 Processor with a register file that supports multiple-issue execution 有权
标题翻译：具有支持多次执行的寄存器文件的处理器
公开(公告)号：US08447931B1
公开(公告)日：2013-05-21
申请号：US11173110
申请日：2005-07-01
申请人： Shailender Chaudhry , Paul Caprioli , Marc Tremblay
发明人： Shailender Chaudhry , Paul Caprioli , Marc Tremblay
IPC分类号： G06F12/00
CPC分类号： G06F9/30141 , G06F9/383 , G06F9/3867 , G11C7/1006 , G11C7/1012 , G11C7/1039 , G11C7/1051 , G11C7/1075 , G11C8/08 , G11C2207/107 , G11C2207/108
摘要： One embodiment of the present invention provides a processor that supports multiple-issue execution. This processor includes a register file, which contains an array of memory cells, wherein the memory cells contain bits for architectural registers of the processor. The register file also includes multiple read ports and multiple write ports to support multiple-issue execution. During operation, if multiple read ports simultaneously read from a given register, the register file is configured to: read each bit of the given register out of the array of memory cells through a single bitline associated with the bit; and to use a driver located outside of the array of memory cells to drive the bit to the multiple read ports. In this way, each memory cell only has to drive a single bitline (instead of multiple bitlines) during a multiple-port read operation, thereby allowing memory cells to use smaller and more power-efficient drivers for read operations.
摘要翻译：本发明的一个实施例提供一种支持多次执行的处理器。该处理器包括一个寄存器文件，该寄存器文件包含一个存储单元阵列，其中存储单元包含处理器结构寄存器的位。注册文件还包括多个读取端口和多个写入端口，以支持多次执行。在操作期间，如果从给定寄存器同时读取多个读取端口，则寄存器文件被配置为：通过与该位相关联的单个位线，将给定寄存器的每个位从存储器单元阵列中读出; 并使用位于存储器单元阵列之外的驱动器将该位驱动到多个读取端口。以这种方式，每个存储器单元仅在多端口读取操作期间仅驱动单个位线（而不是多个位线），从而允许存储器单元使用较小且更省电的驱动器进行读取操作。

30. 发明申请

US20120216016A1 INSTRUCTION SCHEDULING APPROACH TO IMPROVE PROCESSOR PERFORMANCE 有权
标题翻译：指导性调度方法，以提高处理器性能
公开(公告)号：US20120216016A1
公开(公告)日：2012-08-23
申请号：US13459128
申请日：2012-04-28
申请人： Juergen Koehl , Jens Leenstra , Philipp Panitz , Hans Schlenker
发明人： Juergen Koehl , Jens Leenstra , Philipp Panitz , Hans Schlenker
IPC分类号： G06F15/76 , G06F9/06
CPC分类号： G06F9/30141 , G06F8/443 , G06F9/3012 , G06F9/3855 , G06F17/505 , G06F2217/68
摘要： A processor instruction scheduler comprising an optimization engine which uses an optimization model for a processor architecture with: means to generate an optimization model for the optimization engine from a design of a processor and data representing optimization goals and constraints and a code stream, wherein the processor has at least two execution pipes and at least two registers, and wherein the design comprises data for processor instruction latency and execution pipes, and wherein the code stream comprises processor instructions with corresponding register selections; and reordering means to generate an optimized code stream from the code stream with the optimal solution provided by the optimization engine for the optimization model by reordering the code stream, such that optimum values for the optimization goals under the given constraints are achieved without affecting the operation results of the code stream.
摘要翻译：一种处理器指令调度器，其包括使用用于处理器架构的优化模型的优化引擎，其具有：从处理器的设计和表示优化目标和约束的代码流以及代码流生成优化引擎的优化模型的装置，其中所述处理器具有至少两个执行管道和至少两个寄存器，并且其中所述设计包括用于处理器指令等待时间和执行管道的数据，并且其中所述代码流包括具有相应寄存器选择的处理器指令; 以及重新排序装置，用于通过重新排序代码流，从优化引擎为优化模型提供的优化解决方案，从代码流生成优化代码流，从而实现给定约束条件下优化目标的最优值，而不影响操作代码流的结果。

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