专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明申请

US20140298094A1 PROCESSOR POWER MEASUREMENT 有权
标题翻译：处理器功率测量
公开(公告)号：US20140298094A1
公开(公告)日：2014-10-02
申请号：US14223665
申请日：2014-03-24
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： JAMES H. ALIBERTI
IPC分类号： G06F11/27
CPC分类号： G06F11/24 , G01R31/275 , G01R31/28 , G01R31/3004 , G06F1/28 , G06F11/26
摘要： A system can include a processing core to execute machine readable instructions. The system can also include a memory accessible by the processor core. The memory can include preprogrammed test data that characterizes one of an impedance of a processor and a current output to the processor during execution of a test routine. The processor can include the processing core and the one of the impedance of the processor and the current output to the processor is based on a power measurement taken during execution of a test routine. The power measurement can be taken with a current sensor that is at least one of lossy or at least about 98% accurate.
摘要翻译：系统可以包括执行机器可读指令的处理核心。该系统还可以包括可由处理器核心访问的存储器。存储器可以包括预处理的测试数据，其表征处理器的阻抗之一，以及在执行测试例程期间到处理器的当前输出。处理器可以包括处理核心，并且处理器的阻抗和处理器的当前输出中的一个基于在执行测试例程期间所进行的功率测量。功率测量可以用至少有损耗或至少约98％精度的电流传感器来进行。

22. 发明申请

US20140266750A1 APPARATUS AND METHOD FOR TESTING WORKING VOLTAGE OF CPU 审中-公开
标题翻译：用于测试CPU工作电压的装置和方法
公开(公告)号：US20140266750A1
公开(公告)日：2014-09-18
申请号：US14063112
申请日：2013-10-25
申请人： HON HAI PRECISION INDUSTRY CO., LTD. , HONG FU JIN PRECISION INDUSTRY (ShenZhen) CO., LTD.
发明人： MING YU
IPC分类号： G01R31/30
CPC分类号： G01R31/3004 , G06F11/24
摘要： An apparatus for testing working voltage of a central processing unit (CPU) includes a programmable logic device (PLD) having a dummy load, a voltage regulating controller, a CPU socket and a south bridge. The CPU socket is electrically connected to the voltage regulating controller via a series voltage identification (SVID) bus. The south bridge outputs a CPU voltage determining signal. The dummy load is electrically connected to the voltage regulating controller via the SVID bus. The PLD receives the CPU voltage determining signal, and outputs a voltage requesting signal via the SVID bus. The voltage regulating controller receives the voltage requesting signal, and outputs a CPU working voltage to the CPU socket accordingly. The PLD detects the CPU working voltage on the CPU socket, and determines whether the CPU working voltage meets requirements of specification.
摘要翻译：用于测试中央处理单元（CPU）的工作电压的装置包括具有虚拟负载的可编程逻辑器件（PLD），调压控制器，CPU插座和南桥。 CPU插座通过串联电压识别（SVID）总线电连接到电压调节控制器。南桥输出CPU电压确定信号。虚拟负载通过SVID总线电连接到电压调节控制器。 PLD接收CPU电压确定信号，并通过SVID总线输出电压请求信号。电压调节控制器接收电压请求信号，并相应地向CPU插座输出CPU工作电压。 PLD检测CPU插座上的CPU工作电压，并确定CPU工作电压是否符合规范要求。

23. 发明申请

US20140210503A1 STARTUP BOOT CYCLE TESTING OF A MOBILE DEVICE AT DIMINISHED POWER SUPPLY CURRENT 审中-公开
标题翻译：移动电源启动启动循环测试
公开(公告)号：US20140210503A1
公开(公告)日：2014-07-31
申请号：US13972734
申请日：2013-08-21
申请人： Apple Inc.
发明人： Ching-Yu John Tam
IPC分类号： G01R19/00
CPC分类号： G01R19/0092 , G01R31/3004 , G06F11/24
摘要： A startup boot cycle test system for testing a mobile multi-function device under test (DUT) that has a power manager and a main system processor is described. The system includes an external power source and a tester device. The external power source provides an input current to the power manager, which in turn provides a boot current, drawn from the input current, to the main system processor. The tester device connects to a test point in the DUT using a contact test probe to draw a margin current from the boot current. The resulting diminished boot current is used by the processor to boot. The tester device detects whether the processor successfully boots using the diminished boot current using a data input connector connected between the DUT and tester device. Other embodiments are also described and claimed.
摘要翻译：描述了一种用于测试具有电源管理器和主系统处理器的被测移动多功能设备（DUT）的启动引导周期测试系统。该系统包括外部电源和测试仪器。外部电源向功率管理器提供输入电流，电源管理器又将从输入电流引出的引导电流提供给主系统处理器。测试器设备使用接触测试探头连接到DUT中的测试点，以从引导电流绘制余量电流。处理器使用导致的引导电流减少引导。测试仪器使用连接在DUT和测试仪器之间的数据输入连接器，检测处理器是否成功引导使用减小的引导电流。还描述和要求保护其他实施例。

24. 发明申请

US20140089739A1 SERIAL ADVANCED TECHNOLOGY ATTACHMENT DUAL IN-LINE MEMORY MODULE DEVICE HAVING TESTING CIRCUIT FOR CAPACITOR 审中-公开
标题翻译：串行高级技术附件具有电容器测试电路的双列直插式存储器模块器件
公开(公告)号：US20140089739A1
公开(公告)日：2014-03-27
申请号：US13663639
申请日：2012-10-30
申请人： XIAO-GANG YIN , GUO-YI CHEN
发明人： XIAO-GANG YIN , GUO-YI CHEN
IPC分类号： G06F11/27
CPC分类号： G06F11/24 , G11C5/04 , G11C29/04 , G11C29/50 , G11C2029/5002
摘要： A serial advanced technology attachment dual in-line memory module device includes a capacitor to be tested, a control chip, a display device, a testing chip, and a selecting chip. Voltage pins of the testing chip and the selecting chip are connected to a power source. A testing pin of the testing chip is connected to the capacitor. A first input output (I/O) pin of the selecting chip is connected to a first I/O pin of the testing chip. A second I/O pin of the selecting chip is connected to a second I/O pin of the testing chip. A third I/O pin of the selecting chip is connected to an input pin of the control chip. A fourth I/O pin of the selecting chip is connected to an output pin of the control chip. A fifth I/O pin of the selecting chip is connected to the display device.
摘要翻译：串行高级技术附件双列直插式存储模块装置包括待测电容器，控制芯片，显示装置，测试芯片和选择芯片。测试芯片和选择芯片的电压引脚连接到电源。测试芯片的测试引脚连接到电容器。选择芯片的第一个输入输出（I / O）引脚连接到测试芯片的第一个I / O引脚。选择芯片的第二个I / O引脚连接到测试芯片的第二个I / O引脚。选择芯片的第三个I / O引脚连接到控制芯片的输入引脚。选择芯片的第四个I / O引脚连接到控制芯片的输出引脚。选择芯片的第五I / O引脚连接到显示装置。

25. 发明申请

US20140070840A1 Semiconductor Integrated Circuit, Operating Method of Semiconductor Integrated Circuit, and Debug System 有权
标题翻译：半导体集成电路，半导体集成电路的工作方法和调试系统
公开(公告)号：US20140070840A1
公开(公告)日：2014-03-13
申请号：US14080844
申请日：2013-11-15
申请人： Spansion LLC
发明人： Takashi SATO , Toshiaki Saruwatari , Ken Ryu
IPC分类号： G01R31/28
CPC分类号： G01R31/28 , G06F1/26 , G06F11/24 , G06F11/3024 , G06F11/3062 , G06F11/3636 , G06F11/3648
摘要： A current measurement unit measuring power supply currents each consumed in a plurality of circuit blocks of which at least one of the circuit blocks includes a processor, and outputting the measurement result as the power supply current values. A selection unit selecting at least one of the power supply current values according to selection information. A trace buffer sequentially holding the power supply current values being selected by the selection unit together with execution information of the processor, and sequentially outputting the held information. By selecting the power supply current values of the circuit blocks required for debugging according to the selection information, the number of external terminals of a semiconductor integrated circuit required for the debugging which includes tracing the power supply current values may be reduced. As a result, a chip size of the semiconductor integrated circuit with a debug function may be reduced.
摘要翻译：电流测量单元，测量在多个电路块中消耗的电源电流，其中至少一个电路块包括处理器，并输出测量结果作为电源电流值。选择单元根据选择信息选择电源电流值中的至少一个。顺序地保持由选择单元选择的电源电流值与跟随执行信息的跟踪缓冲器，并顺序地输出保持的信息。通过根据选择信息选择调试所需的电路块的电源电流值，可以减少包括跟踪电源电流值的调试所需的半导体集成电路的外部端子的数量。结果，可以减少具有调试功能的半导体集成电路的芯片尺寸。

26. 发明授权

US08595562B2 Semiconductor integrated circuit, operating method of semiconductor integrated circuit, and debug system 有权
标题翻译：半导体集成电路，半导体集成电路的操作方法和调试系统
公开(公告)号：US08595562B2
公开(公告)日：2013-11-26
申请号：US13014318
申请日：2011-01-26
申请人： Takashi Sato , Toshiaki Saruwatari , Ken Ryu
发明人： Takashi Sato , Toshiaki Saruwatari , Ken Ryu
IPC分类号： G06F11/00
CPC分类号： G01R31/28 , G06F1/26 , G06F11/24 , G06F11/3024 , G06F11/3062 , G06F11/3636 , G06F11/3648
摘要： A current measurement unit measuring power supply currents each consumed in a plurality of circuit blocks of which at least one of the circuit blocks includes a processor, and outputting the measurement result as the power supply current values. A selection unit selecting at least one of the power supply current values according to selection information. A trace buffer sequentially holding the power supply current values being selected by the selection unit together with execution information of the processor, and sequentially outputting the held information. By selecting the power supply current values of the circuit blocks required for debugging according to the selection information, the number of external terminals of a semiconductor integrated circuit required for the debugging which includes tracing the power supply current values may be reduced. As a result, a chip size of the semiconductor integrated circuit with a debug function may be reduced.
摘要翻译：电流测量单元，测量在多个电路块中消耗的电源电流，其中至少一个电路块包括处理器，并输出测量结果作为电源电流值。选择单元根据选择信息选择电源电流值中的至少一个。顺序地保持由选择单元选择的电源电流值与跟随执行信息的跟踪缓冲器，并顺序地输出保持的信息。通过根据选择信息选择调试所需的电路块的电源电流值，可以减少包括跟踪电源电流值的调试所需的半导体集成电路的外部端子的数量。结果，可以减少具有调试功能的半导体集成电路的芯片尺寸。

27. 发明授权

US08570182B2 Server with voltage test system 有权
标题翻译：服务器带电压测试系统
公开(公告)号：US08570182B2
公开(公告)日：2013-10-29
申请号：US13442931
申请日：2012-04-10
申请人： Zuo-Lin Hou , Song Yu
发明人： Zuo-Lin Hou , Song Yu
IPC分类号： G08B21/00
CPC分类号： G06F11/24 , G01R19/1659 , G06F11/325
摘要： A server includes a motherboard, a first test unit, and an indication device. The first test unit is connected to a first voltage terminal of the motherboard to receive a first voltage. The first test unit determines whether the received first voltage is within a range between a first predetermined voltage and a second predetermined voltage. If the first voltage is not within the range between the first predetermined voltage and the second predetermined voltage, the indication device indicates that the first voltage is abnormal.
摘要翻译：服务器包括主板，第一测试单元和指示设备。第一测试单元连接到主板的第一电压端子以接收第一电压。第一测试单元确定所接收的第一电压是否在第一预定电压和第二预定电压之间的范围内。如果第一电压不在第一预定电压和第二预定电压之间的范围内，则指示装置指示第一电压异常。

28. 发明申请

US20130226500A1 DETERMINATION OF VALIDITY OF BI-LEVEL DIGITAL SIGNAL VIA DIGITAL DATA ACQUISITION 审中-公开
标题翻译：通过数字数据采集确定双电平数字信号的有效性
公开(公告)号：US20130226500A1
公开(公告)日：2013-08-29
申请号：US13405652
申请日：2012-02-27
申请人： Kevin D. Russo
发明人： Kevin D. Russo
IPC分类号： G06F19/00
CPC分类号： G06F11/24
摘要： A system for testing the output of a digital gauge controller is disclosed. The system is configured to receive a multi-component digital signal and test if a plurality of thresholds are reached for individual components of the digital signal. If a first expected level is met, the system then determines if a second component of the multi-component signal meets a second expected level.
摘要翻译：公开了一种用于测试数字量规控制器的输出的系统。该系统被配置为接收多分量数字信号并测试是否达到数字信号的各个分量的多个阈值。如果满足第一预期电平，则系统然后确定多分量信号的第二分量是否满足第二预期电平。

29. 发明申请

US20130207809A1 SERVER WITH VOLTAGE TEST SYSTEM 有权
标题翻译：具有电压测试系统的服务器
公开(公告)号：US20130207809A1
公开(公告)日：2013-08-15
申请号：US13442931
申请日：2012-04-10
申请人： ZUO-LIN HOU , SONG YU
发明人： ZUO-LIN HOU , SONG YU
IPC分类号： G08B21/00 , G01R31/28
CPC分类号： G06F11/24 , G01R19/1659 , G06F11/325
摘要： A server includes a motherboard, a first test unit, and an indication device. The first test unit is connected to a first voltage terminal of the motherboard to receive a first voltage. The first test unit determines whether the received first voltage is within a range between a first predetermined voltage and a second predetermined voltage. If the first voltage is not within the range between the first predetermined voltage and the second predetermined voltage, the indication device indicates that the first voltage is abnormal.
摘要翻译：服务器包括主板，第一测试单元和指示设备。第一测试单元连接到主板的第一电压端子以接收第一电压。第一测试单元确定所接收的第一电压是否在第一预定电压和第二预定电压之间的范围内。如果第一电压不在第一预定电压和第二预定电压之间的范围内，则指示装置指示第一电压异常。

30. 发明申请

US20130191690A1 IN SITU PROCESSOR RE-CHARACTERIZATION 有权
公开(公告)号：US20130191690A1
公开(公告)日：2013-07-25
申请号：US13681050
申请日：2012-11-19
申请人： International Business Machines Corporation
发明人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , Brian R. Prasky , Chung-Lung K. Shum
IPC分类号： G06F11/26
CPC分类号： G06F11/24 , G06F1/206 , G06F1/32 , G06F1/324
摘要： A re-characterization process is provided that adjusts one or more operating parameters of a processor to improve the health (e.g., reduce errors) of the processor. The parameters include voltage and/or clock frequency, as examples. The processor can be an inactive or active processor for which the re-characterization process is performed. It is performed, in one instance, by a hardware controller in real-time.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式